Siemens HYM321000GS-50, HYM321000GS-60, HYM321000S-50, HYM321000S-60 Datasheet
1M × 32-Bit Dynamic RAM Module
(2M × 16-Bit Dynamic RAM Module)
Advanced Inf ormation
• 1 048 576 words by 32-bit organization
(alternative 2 097 152 words by 16-bit)
• Fast access and cycle time
50 ns access time
90 ns cycle time (-50 version)
60 ns access time
110 ns cycle time (-60 version)
• Fast page mode capability with
35 ns cycle time (-50 version)
40 ns cycle time (-60 version)
HYM 321000S/GS-50/-60
• Single + 5 V (± 10 %) supply
• Low power dissipation
max 2200 mW acti ve (-50 version)
max. 1980 mW acti ve (-60 version)
CMOS – 11 mW standby
TTL – 22 mW standby
• CAS-before-RAS refresh, RAS-only -refresh, Hidden refresh
• 2 decoupling capacitors mounted on substrate
• All inputs, outputs and clock fully TTL compatible
• 72 pin Single in-Line Memory Module
• Utilizes two 1M × 16 -DRAMs in SOJ-42 packages
• 1024 refresh cycles/16 ms
• Optimized for use in byte-write non-parity applications
• Tin-Lead contact pads HYM 321000S
• Gold-Lead contact pads HYM 321000GS
• single sided module with 20.32 mm (800 mil) height
Semiconductor Group 1
1 12.95
HYM 321000S/GS-50/-60
1M × 32-Bit
The HYM 321000S/GS-50/-60 is a 4 MByte DRAM module organized as 1 048 576 words by 32bit in a 72-pin single-in-line package comprising two HYB 5118160BSJ 1M × 16 DRAMs in 400 mil
wide SOJ-packages mounted together with two 0.2 µF ceramic decoupling capaci tors on a PC
board.
The HYM 321000S/GS-60/-70 can also be use d as a 2 097 152 words by 16-bi ts dynamic RAM
module by means of connectin g DQ0 and DQ16, DQ 1 and DQ17, DQ2 and DQ18, … , DQ15 an d
DQ31, respectively.
Each HYB 5118160BSJ is described in the data sheet and is fully electrically tested and processed
according to Siemens standard quality procedure prior to modul e assembly. After assembl y onto
the board, a further set of electrical tests is performed.
The speed of the module can be detected by the use of four presence detect pins.
The common I/O feature on the HYM 321000S/GS-50/-60 dictates the use of ear ly write cyc les.
Ordering Infor mation
Type Ordering Code Package Descriptions
HYM 321000S-50 Q67100 - Q2051 L-SIM-72-10 DRAM module
(access time50 ns)
HYM 321000S-60 Q67100 - Q2056 L-SIM-72-10 DRAM module
(access time 60 ns)
HYM 321000GS-50 Q67100 - Q2053 L-SIM-72-10 DRAM module
(access time 50 ns)
HYM 321000GS-60 Q67100 - Q2058 L-SIM-72-10 DRAM module
(access time 60 ns)
Semiconductor Group 2
VSS 1 DQ0 2
DQ16 3 DQ1 4
DQ17 5 DQ2 6
DQ18 7 DQ3 8
DQ19 9 VCC 10
N.C. 11 A0 12
A1 13 A2 14
A3 15 A4 16
A5 17 A6 18
N.C. 19 DQ4 20
DQ20 21 DQ5 22
DQ21 23 DQ6 24
DQ22 25 DQ7 26
DQ23 27 A7 28
N.C. 29 VCC 30
A8 31 A9 32
N.C. 33 RAS2
N.C. 35 N.C. 36
34
HYM 321000S/GS-50/-60
1M × 32-Bit
Pin Names
A0-A9 Address Inputs
DQ0-DQ31 Data Input/Output
CAS0
- CAS3 Column Address Strobe
, RAS2 Row Address Strobe
RAS0
WE
V
CC
V
SS
PD Presence Detect Pin
N.C. No Connection
Read/Write Input
Power (+ 5 V)
Ground
N.C. 37 N.C. 38
VSS 39 CAS0
41 CAS342
CAS2
43 RAS044
CAS1
N.C. 45 N.C. 46
47 N.C. 48
WE
DQ8 49 DQ24 50
DQ9 51 DQ25 52
DQ10 53 DQ2654
DQ11 55 DQ2756
DQ12 57 DQ2858
VCC 59 DQ2960
DQ13 61 DQ3062
DQ14 63 DQ3164
DQ15 65 N.C. 66
PD0 67 PD1 68
PD2 69 PD3 70
N.C. 71 VSS 72
40
Pin Configu ration
Presence Detect Pins
-50 -60
PD0
PD1 V
PD2 V
PD3
V
SS
SS
SS
V
SS
V
SS
V
SS
N.C.
N.C.
Semiconductor Group 3
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