Siemens HYB514256BJL-50, HYB514256BJL-60, HYB514256BJL-70, HYB514256BL-50, HYB514256BL-60 Datasheet

Semiconductor Group 55 01.95

• 262 144 words by 4-bit organization

• Fast access and cycle time

50 ns access time
95 ns cycle time (-50 version)
60 ns access time
110 ns cycle time (-60 version)
70 ns access time
130 ns cycle time (-70 version)

• Fast page mode cycle time

35 ns (-50 version)
40 ns (-60 version)
45 ns (-70 version)

• Low power dissipation

max. 495 mW active (-50 version)
max. 440 mW active (-60 version)
max. 385 mW active (-70 version)
max. 5.5 mW standby
max. 1.1 mW standby for L-version

Ordering Information
Type Ordering Code Package Description

HYB 514256B-50 Q67100-Q1044 P-DIP-20-2 DRAM (access time 50ns)
HYB 514256B-60 Q67100-Q530 P-DIP-20-2 DRAM (access time 60 ns)
HYB 514256B-70 Q67100-Q433 P-DIP-20-2 DRAM (access time 70 ns)
HYB 514256BJ-50 Q67100-Q1054 P-SOJ-26/20-1 DRAM (access time 50 ns)
HYB 514256BJ-60 Q67100-Q536 P-SOJ-26/20-1 DRAM (access time 60 ns)
HYB 514256BJ-70 Q67100-Q537 P-SOJ-26/20-1 DRAM (access time 70 ns)
HYB 514256BL-50 on request P-DIP-20-2 DRAM (access time 50 ns)
HYB 514256BL-60 Q67100-Q542 P-DIP-20-2 DRAM (access time 60 ns)
HYB 514256BL-70 Q67100-Q543 P-DIP-20-2 DRAM (access time 70 ns)
HYB 514256BJL-50 on request P-SOJ-26/20-1 DRAM (access time 50 ns)
HYB 514256BJL-60 Q67100-Q608 P-SOJ-26/20-1 DRAM (access time 60 ns)
HYB 514256BJL-70 Q67100-Q607 P-SOJ-26/20-1 DRAM (access time 70 ns)

256 K × 4-Bit Dynamic RAM
Low Power 256 K × 4-Bit Dynamic RAM

Advanced Information

• Single + 5 V (± 10 %) supply with a built-inV

BB

generator

• Output unlatched at cycle end allows two-

dimensional chip selection

• Read-modify-write, CAS-before-RAS

refresh,

RAS-only refresh, hidden-refresh

and fast page mode capability

• All inputs, outputs and clocks

TTL-compatible

• 512 refresh cycles/8 ms

512 refresh cycles/64 ms
for L-version only

• Plastic Packages: P-DIP-20-2,

P-SOJ-26/20-1

HYB 514256B/BJ-50/-60/-70

HYB 514256BL/BJL-50/-60/-70

Semiconductor Group 56

HYB 514256B/BL/BJ/BJL-50/-60/-70

256 K × 4-DRAM

The HYB 514256B/BJ/BL/BJL is the new generation dynamic RAM organized as 262 144 words by
4-bit. The HYB 514256B/BJ/BL/BJL utilizes CMOS silicon gate process technology as well as
advanced circuit techniques to provide wide operating margins, both internally and for the system
user. Multiplexed address inputs permit the HYB 514256B/BJ/BL/BJL to be packaged in a standard
plastic P-DIP-20-2,or plastic P-SOJ-26/20-1. This package size provides high system bit densities
and is compatible with commonly used automatic testing and insertion equipment. System oriented
features include single + 5 V (± 10 %) power supply, direct interfacing with high-performance logic
device families such as Schottky TTL. These HYB 514256BL/BJL are specially selected for battery
backup applications.

Pin Definitions and Functions
Pin No. Function

A0-A8 Address Inputs
RAS Row Address Strobe
OE Output Enable
I/O1-I/O4 Data Input/Output
CAS Column Address Strobe
WE Read/Write Input

V

CC

Power Supply (+ 5 V)

V

SS

Ground (0 V)

N.C. No Connection

Semiconductor Group 57

HYB 514256B/BL/BJ/BJL-50/-60/-70

256 K × 4-DRAM

Pin Configuration

(top view)

P-SOJ-26/20-1 P-DIP-20-2

Semiconductor Group 58

HYB 514256B/BL/BJ/BJL-50/-60/-70

256 K × 4-DRAM

Block Diagram

Semiconductor Group 59

HYB 514256B/BL/BJ/BJL-50/-60/-70

256 K × 4-DRAM

Absolute Maximum Ratings

Operating temperature range .........................................................................................0 to + 70 ˚C

Storage temperature range......................................................................................– 55 to + 150 ˚C

Soldering temperature ............................................................................................................260 ˚C

Soldering time.............................................................................................................................10 s

Input/output voltage ........................................................................................................– 1 to + 7 V

Power supply voltage......................................................................................................– 1 to + 7 V

Power dissipation..................................................................................................................... 0.6 W

Data out current (short circuit) ................................................................................................ 50 mA

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.

DC Characteristics

T

A

= 0 to 70 ˚C; VSS = 0 V; VCC = 5 V ± 10 %

Parameter Symbol Limit Values Unit Test

Condition

min. max.

Input high voltage

V

IH

2.4 6.5 V

1)

Input low voltage V

IL

– 1.0 0.8 V

1)

Output high voltage (I

OUT

= – 5 mA) V

OH

2.4 – V

1)

Output low voltage (I

OUT

= 4.2 mA) V

OL

– 0.4 V

1)

Input leakage current, any input
(0 V ≤

V

IN

≤ 6.5 V, all other pins = 0 V)

I

I(L)

– 10 10 µA

1)

Output leakage current
(DO is disabled, 0 V ≤

V

OUT

≤ VCC)

I

O(L)

– 10 10 µA

1)

Average VCC supply current:

-50 version

-60 version

-70 version

(

RAS, CAS, address cycling: tRC = tRC min.)

I

CC1

–
–
–

90
80
70

mA
mA
mA

2) 3)

2) 3)

2) 3)

Standby VCC supply current (RAS = CAS = VIH) I

CC2

–2mA–

Average

V

CC

supply current, RAS only mode:

-50 version

-60 version

-70 version

(

RAS cycling: CAS = VIH: tRC = tRC min.)

I

CC3

–
–
–

90
80
70

mA
mA
mA

2)

2)

2)

Semiconductor Group 60

HYB 514256B/BL/BJ/BJL-50/-60/-70

256 K × 4-DRAM

Average VCC supply current, fast page mode:

-60 version

-70 version

-50 version

(RAS = VIL, CAS, address cycling:

t

PC

= tPC min.)

I

CC4

–
–
–

70
60
50

mA
mA
mA

2) 3

2) 3)

2) 3)

Standby VCC supply current

L-Version

(

RAS = CAS = VCC – 0.2 V)

I

CC5

–
–

1
200

mA
µA

1)

1)

Average VCC supply current, CAS-before-RAS
refresh mode:

-50 version

-60 version

-70 version

(

RAS, CAS cycling: tRC = tRC min.)

I

CC6

–
–
–

90
80
70

mA
mA
mA

2)

2)

2)

For L-version only:
Battery backup current:
average power supply current,
battery backup mode:
(CAS = CAS before RAS cycling or 0.2 V,
OE = VCC – 0.2 V
WE = VCC – 0.2 V or 0.2 V,
A0 to A8 =

V

CC

– 0.2 V or 0.2 V,

I/O1 to I/O4 =

V

CC

– 0.2 V or 0.2 V or open,

t

RC

= 125 µs, t

RAS

= t

RAS

min. ~ 1 µs)

I

CC7

– 300 µA

2)

DC Characteristics (cont’d)

T

A

= 0 to 70 ˚C; VSS = 0 V; VCC = 5 V ± 10 %

Parameter Symbol Limit Values Unit Test

Condition

min. max.

Semiconductor Group 61

HYB 514256B/BL/BJ/BJL-50/-60/-70

256 K × 4-DRAM

AC Characteristics

4) 13)

T

A

= 0 to 70 ˚C; VCC = 5 V ± 10 %; tT = 5 ns

Parameter Symbol Limit Values Unit

-50 -60 -70

min. max. min. max. min. max.

Random read or write cycle
time

t

RC

95 – 110 – 130 – ns

Read-modify-write cycle time

t

RWC

140 – 160 – 185 – ns

Fast page mode cycle time

t

PC

35 – 40 – 45 – ns

Fast page mode read-modify­write cycle time

t

PRWC

80 – 90 – 100 – ns

Access time from

RAS

6) 11)

t

RAC

–50 –60 –70 ns

Access time from

CAS

6) 11)

t

CAC

–15 –15 –20 ns

Access time from column
address

6) 12)

t

AA

–25 –30 –35 ns

Access time from

CAS

precharge

6) 12)

t

CPA

–30 –35 –40 ns

CAS to output in low-Z

4)

t

CLZ

0– 0– 0– ns

Output buffer
turn-off delay

7)

t

OFF

015 020 020 ns

Transition time
(rise and fall)

5)

t

T

350 350 350 ns

RAS precharge time t

RP

35 – 40 – 50 – ns

RAS pulse width t

RAS

50 10.000 60 10.000 70 10.000 ns

RAS pulse width
(fast page mode)

t

RASP

50 100.000 60 100.000 70 100.000 ns

RAS hold time t

RSH

15 – 15 – 20 – ns

CAS hold time t

CSH

50 – 60 – 70 – ns

CAS pulse width t

CAS

15 10.000 15 10.000 20 10.000 ns

RAS hold time from CAS
precharge (Fast Page Mode)

t

RHCP

30 – 35 – 45 – ns

CAS precharge to WE delay
time (FPM RMW)

t

CPWD

55 – 60 – 65 – ns

RAS to CAS delay time

11)

t

RCD

20 35 20 45 20 50

RAS to column address delay
time

12)

t

RAD

15 25 15 30 15 35 ns

CAS to RAS precharge time t

CRP

5– 5– 5– ns

CAS precharge time t

CP

10 – 10 – 10 – ns