Siemens HYB514175BJ-50, HYB514175BJ-55, HYB514175BJ-60 Datasheet

256k × 16-Bit EDO-DRAM

Advanced Information

HYB 514175BJ-50/-55/-60

• 262 144 words by 16-bit organization

• 0 to 70 °C operating temperature

• Fast access and cycle time

• RAS access time:
50 ns (-50 version)
55 ns (-55 version)
60 ns (-60 version)

• CAS access time:
13 ns (-50 & -55 version)
15 ns (-60 version)

• Cycle time:
89 ns (-50 version)
94 ns (-55 version)
104 ns (-60 version)

• Hyper page mode (EDO) cycle time
20 ns (-50 & -55 version)
25 ns (-60 version)

• High data rate
50 MHz (-50 & -55 version)
40 MHz (-60 version)

• Single + 5 V (± 10 %) supply with a built-in

V

generator

BB

• Low Power dissipation
max. 1100 mW active (-50 version)
max. 1045 mW active (-55 version)
max. 935 mW active (-60 version)

• Standby power dissipation
11 mW standby (TTL)

5.5 mW max. standby (CMOS)

• Output unlatched at cycle end allows
two-dimensional chip selection

• Read, write, read-modify write,
CAS-before-RAS refresh, RAS-only
refresh, hidden-refresh and hyper page
(EDO) mode capability

•2CAS/1 WE control

• All inputs and outputs TTL-compatible

• 512 refresh cycles/16 ms

• Plastic Packages:
P-SOJ-40-1 400 mil width

Semiconductor Group 1 1998-10-01

HYB 514175BJ/BJL-50/-55/-60

256k × 16 EDO-DRAM

The HYB 514175BJ is the new generation dynamic RAM organized as 262 144 words by 16-bit.
The HYB 514175BJ utilizes CMOS silicon gate process as well as advanced circuit techniques to
provide wide operation margins, both internally and for the system user. Multiplexed address inputs
permit the HYB 514175BJ to be packed in a standard plastic 400 mil wide P-SOJ-40-1 package.
This package size provides high system bit densities and is compatible with commonly used
automatic testing and insertion equipment. System oriented features include single + 5 V (± 10 %)
power supply, direct interfacing with high performance logic device families such as Schottky TTL.

Ordering Information
Type Ordering Code Package Description

HYB 514175BJ-50 Q67100-Q2072 P-SOJ-40-1 400 mil 50 ns 256k × 16 EDO-DRAM
HYB 514175BJ-55 Q67100-Q2100 P-SOJ-40-1 400 mil 55 ns 256k × 16 EDO-DRAM
HYB 514175BJ-60 Q67100-Q2073 P-SOJ-40-1 400 mil 60 ns 256k × 16 EDO-DRAM

Truth Table
RAS LCAS UCAS WE OE I/O1 - I/O8 I/O9 - I/O16 Operation

H
L
L
L
L
L
L
L
L

Pin Names

A0 - A8 Address Inputs
RAS Row Address Strobe
UCAS, LCAS Column Address Strobe

H
H
L
H
L
L
H
L
L

H
H
H
L
L
H
L
L
L

H
H
H
H
H
L
L
L
H

H
H
L
L
L
H
H
H
H

High-Z
High-Z
Dout
High-Z
Dout
Din
Don't care
Din
High-Z

High-Z
High-Z
High-Z
Dout
Dout
Don't care
Din
Din
High-Z

Standby
Refresh
Lower byte read
Upper byte read
Word read
Lower byte write
Upper byte write
Word write

−

WE Read/Write Input
OE Output Enable
I/O1 -I/O16 Data Input/Output

V

CC

V

SS

N.C. No Connection

Semiconductor Group 2 1998-10-01

Power Supply (+ 5 V)
Ground (0 V)

P-SOJ-40-1

HYB 514175BJ-50/-55/-60

256k × 16 EDO-DRAM

V

1

CC

2

I/O1

3

I/O2
I/O3

4

I/O4

5

V

6

CC

I/O5

7

I/O6

8

I/O7

9
10

I/O8

11

N.C.

12

N.C.

WE

13

RAS

14

N.C.

15

A0

16

A1

17

A2

18

A3 A4

19

V

20

CC

40
39
38
37
36
35
34
33
32

31
30
29
28
27
26
25
24
23
22

21

SPP02811

V

SS

I/O16
I/O15
I/O14
I/O13

V

SS

I/O12
I/O11
I/O10
I/O9
N.C.
LCAS
UCAS
OE
A8
A7
A6
A5

V

SS

Pin Configuration

(top view)

Semiconductor Group 3 1998-10-01

HYB 514175BJ/BJL-50/-55/-60

256k × 16 EDO-DRAM

WE
UCAS
LCAS

A0
A1
A2
A3
A4
A5
A6
A7
A8

I/O1 I/O2 I/O16

Data In

Buffer

&

16

...

..

.

.

Data Out

Buffer

OE

16

No.2 Clock

Generator

9

Column

Address

Buffers (9)

9

Column
Decoder

Refresh

Controller

Sense Amplifier

16

I/O Gating

Refresh

Counter (9)

512

...

...

16x

9

.

.

9

Row

Address

Buffers (9)

9

Row

Decoder

.

512

.

.

.

Memory Array

512 x 512 x

16

RAS

No.1 Clock

Generator

Substrate Bias

Generator

V

CC

V

SS

SPB02827

Block Diagram

Semiconductor Group 4 1998-10-01

HYB 514175BJ-50/-55/-60

256k × 16 EDO-DRAM

Absolute Maximum Ratings

Operating temperature range ....................................................................................... 0 to + 70 °C

Storage temperature range.................................................................................... – 55 to + 150 °C

Input/output voltage....................................................................................................... – 1 to + 6 V

Power supply voltage..................................................................................................... – 1 to + 6 V

Data out current (short circuit) ............................................................................................... 50 mA

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent

damage of the device. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

DC Characteristics

T

= 0 to 70 °C; VSS = 0 V; VCC = 5 V ± 10 %, tT = 2 ns

A

Parameter Symbol Limit Values Unit Test

Condition

1

1

1

1

1

1

2, 3, 4

Input high voltage V
Input low voltage V
Output high voltage (I
Output low voltage (I

= – 5.0 mA) V

OUT

= 4.2 mA) V

OUT

Input leakage current, any input
(0 V < VIN < 7 V, all other inputs = 0 V)

Output leakage current
(DO is disabled, 0 V < V

OUT

< VCC)

Average VCC supply current

-50 version

-55 version

-60 version

I

I

I

IH

IL

OH

OL

I(L)

O(L)

CC1

min. max.

2.4 VCC+ 0.5 V
– 1.0 0.8 V

2.4 – V
– 0.4 V
– 10 10 µA

– 10 10 µA

–

200

mA
190
170

Standby VCC supply current

I

CC2

–2mA

(RAS = LCAS = UCAS = WE = VIH)
Average VCC supply current during

I

CC3

–

RAS-only refresh cycles

2, 4

2, 3, 4

Average VCC supply current during

-50 version

-55 version

-60 version

I

CC4

200

mA
190
170

–

hyper page mode (EDO) operation

-50 version

-55 version

-60 version

190
180
170

mA

Semiconductor Group 5 1998-10-01

HYB 514175BJ/BJL-50/-55/-60

256k × 16 EDO-DRAM

DC Characteristics (cont’d)

T

= 0 to 70 °C; VSS = 0 V; VCC = 5 V ± 10 %, tT = 2 ns

A

Parameter Symbol Limit Values Unit Test

min. max.

Standby VCC supply current

I

CC5

–1mA

(RAS = LCAS = UCAS = WE = VCC – 0.2 V)
Average VCC supply current during

I

CC6

–

CAS-before-RAS refresh mode

-50 version

-55 version

-60 version

200
190
170

mA

Capacitance

T

= 0 to 70 °C; VCC = 5 V ± 10 %, f = 1 MHz

A

Parameter Symbol Limit Values Unit

Condition

1

2, 4

min. max.

Input capacitance (A0 to A8) C
Input capacitance (RAS, UCAS, LCAS, WE, OE) C
Output capacitance (l/O1 to l/O16) C

AC Characteristics

T

= 0 to 70 °C; VSS = 0 V; VCC = 5 V ± 10 %, tT= 2 ns

A

5, 6

I1

I2

IO

–5pF
–7pF
–7pF

Parameter Symbol Limit Values Unit Note

-50 -55 -60

min. max. min. max. min. max.

Common Parameters

Random read or write cycle time t
RAS precharge time t
RAS pulse width t
CAS pulse width t
Row address setup time t
Row address hold time t
Column address setup time t
Column address hold time t
RAS to CAS delay time t
RAS to column address delay time t

RC

RP

RAS

CAS

ASR

RAH

ASC

CAH

RCD

RAD

89 – 94 – 104 – ns
35 – 35 – 40 – ns
50 10k 55 10k 60 10k ns
8 10k 8 10k 10 10k ns
0–0–0–ns
8–8–10–ns
0–0–0–ns
8–8–10–ns
12 37 12 43 14 45 ns
10 25 10 30 12 30 ns

Semiconductor Group 6 1998-10-01

HYB 514175BJ-50/-55/-60

256k × 16 EDO-DRAM

AC Characteristics

T

= 0 to 70 °C; VSS = 0 V; VCC = 5 V ± 10 %, tT= 2 ns

A

(cont’d)5, 6

Parameter Symbol Limit Values Unit Note

-50 -55 -60

min. max. min. max. min. max.

RAS hold time t
CAS hold time t
CAS to RAS precharge time t
Transition time (rise and fall) t
Refresh period t

RSH

CSH

CRP

T

REF

13 – 13 – 15 – ns
40 – 45 – 50 – ns
5–5–5–ns
1 50 1 50 1 50 ns
– 16 – 16 – 16 ms

7

Read Cycle

Access time from RAS t
Access time from CAS t
Access time from column address t
OE access time t
Column address to RAS lead time t
Read command setup time t
Read command hold time t
Read command hold time ref. to RAS t
CAS to output in low-Z t
Output buffer turn-off delay from CAS t
Output buffer turn-off delay from OE t
Data to OE low delay t
CAS high to data delay t
OE high to data delay t

RAC

CAC

AA

OEA

RAL

RCS

RCH

RRH

CLZ

OFF

OEZ

DZO

CDD

ODD

– 50 – 55 – 60 ns
– 13 – 13 – 15 ns
– 25 – 25 – 30 ns
– 13 – 13 – 15 ns
25 – 25 – 30 – ns
0–0–0–ns
0–0–0–ns
0–0–0–ns
0–0–0–ns
0 13 0 13 0 15 ns
0 13 0 13 0 15 ns
0–0–0–ns
10 – 10 – 13 – ns
10 – 10 – 13 – ns

8, 9

8, 9

8, 10

11

11

8

12

12

13

14

14

Write Cycle

Write command hold time t
Write command pulse width t
Write command setup time t
Write command to RAS lead time t
Write command to CAS lead time t
Data setup time t
Data hold time t
Data to CAS low delay t

WCH

WP

WCS

RWL

CWL

DS

DH

DZC

8–8–10–ns
8–8–10–ns
0–0–0–ns
13 – 13 – 15 – ns
13 – 13 – 15 – ns
0–0–0–ns
8–8–10–ns
0–0–0–ns

15

16

16

13

Semiconductor Group 7 1998-10-01