Siemens HYB514171BJ-50, HYB514171BJ-60 Datasheet
256k × 16-Bit Dynamic RAM
Advanced Information
HYB 514171BJ-50/-60
• 262 144 words by 16-bit organization
• 0 to 70 °C operating temperature
• Fast access and cycle time
• RAS access time:
50 ns (-50 version)
60 ns (-60 version)
• CAS access time:
15ns (-50, -60 version)
• Cycle time:
95 ns (-50 version)
110 ns (-60 version)
• Fast page mode cycle time
35 ns (-50 version)
40 ns (-60 version)
• Single + 5.0 V (± 10 %) supply with a
built-in VBB generator
• Low Power dissipation
max. 1045 mW active (-50 version)
max. 935 mW active (-60 version)
• Standby power dissipation
11 mW standby (TTL)
5.5 mW max. standby (CMOS)
• Output unlatched at cycle end allows
two-dimensional chip selection
• Read, write, read-modify write,
CAS-before-RAS refresh, RAS-only
refresh, hidden-refresh and fast page
mode capability
•2CAS / 1 WE control
• All inputs and outputs TTL-compatible
• 512 refresh cycles / 16 ms
• Plastic Packages:
P-SOJ-40-1 400 mil width
The HYB 514171BJ is a 4 MBit dynamic RAM organized as 262 144 words by 16-bit. The
HYB 514171BJ utilizes CMOS silicon gate process as well as advanced circuit techniques to
provide wide operation margins, both internally and for the system user. Multiplexed address inputs
permit the HYB 514171BJ to be packed in a standard plastic 400 mil wide P-SOJ-40-1 package.
This package size provides high system bit densities and is compatible with commonly used
automatic testing and insertion equipment. System oriented features include single + 5 V (± 10 %)
power supply, direct interfacing with high performance logic device families such as Schottky TTL.
Semiconductor Group 1 1998-10-01
HYB 514171BJ-50/-60
256k × 16 DRAM
Ordering Information
Type Ordering Code Package Description
HYB 514171BJ-50 Q67100-Q2021 P-SOJ-40-1 400 mil 50 ns 256k × 16 DRAM
HYB 514171BJ-60 Q67100-Q727 P-SOJ-40-1 400 mil 60 ns 256k × 16 DRAM
Truth Table
RAS LCAS UCAS WE OE I/O1 - I/O8 I/O9 - I/O16 Operation
H
L
L
L
L
L
L
L
L
Pin Names
A0 - A8 Address Inputs
RAS Row Address Strobe
UCAS, LCAS Column Address Strobe
WE Read/Write Input
OE Output Enable
I/O1 - I/O16 Data Input/Output
H
H
L
H
L
L
H
L
L
H
H
H
L
L
H
L
L
L
H
H
H
H
H
L
L
L
H
H
H
L
L
L
H
H
H
H
High-Z
High-Z
Dout
High-Z
Dout
Din
Don't care
Din
High-Z
High-Z
High-Z
High-Z
Dout
Dout
Don't care
Din
Din
High-Z
Standby
Refresh
Lower byte read
Upper byte read
Word read
Lower byte write
Upper byte write
Word write
−
V
CC
V
SS
N.C. No Connection
Semiconductor Group 2 1998-10-01
Power Supply (+ 5 V)
Ground (0 V)
P-SOJ-40-1
HYB 514171BJ-50/-60
256k × 16 DRAM
V
1
CC
2
I/O1
3
I/O2
I/O3
4
I/O4
5
V
6
CC
I/O5
7
I/O6
8
I/O7
9
10
I/O8
11
N.C.
12
N.C.
WE
13
RAS
14
N.C.
15
A0
16
A1
17
A2
18
A3 A4
19
V
20
CC
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
SPP02811
V
SS
I/O16
I/O15
I/O14
I/O13
V
SS
I/O12
I/O11
I/O10
I/O9
N.C.
LCAS
UCAS
OE
A8
A7
A6
A5
V
SS
Pin Configuration
(top view)
Semiconductor Group 3 1998-10-01
HYB 514171BJ-50/-60
256k × 16 DRAM
WE
UCAS
LCAS
A0
A1
A2
A3
A4
A5
A6
A7
A8
I/O1 I/O2 I/O16
Data In
Buffer
&
16
...
..
.
.
Data Out
Buffer
OE
16
No.2 Clock
Generator
9
Column
Address
Buffers (9)
9
Column
Decoder
Refresh
Controller
Sense Amplifier
16
I/O Gating
Refresh
Counter (9)
512
...
...
16x
9
.
.
9
Row
Address
Buffers (9)
9
Row
Decoder
.
512
.
.
.
Memory Array
512 x512 x
16
RAS
No.1 Clock
Generator
Substrate Bias
Generator
V
CC
V
SS
SPB02827
Block Diagram
Semiconductor Group 4 1998-10-01
HYB 514171BJ-50/-60
256k × 16 DRAM
Absolute Maximum Ratings
Operating temperature range ....................................................................................... 0 to + 70 °C
Storage temperature range.................................................................................... – 55 to + 150 °C
Input/output voltage......................................................................................................... – 1 to 6 V
Power supply voltage........................................................................................................ – 1 to 6 V
Data out current (short circuit) ............................................................................................... 50 mA
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
DC Characteristics
T
= 0 to 70 °C; VSS = 0 V; VCC = 5 V ± 10 %, tT = 5 ns
A
Parameter Symbol Limit Values Unit Notes
Input high voltage V
Input low voltage V
TTL Output high voltage (I
TTL Output low voltage (I
= – 5.0 mA) V
OUT
= 4.2 mA) V
OUT
Input leakage current, any input
(0 V < VIN < VCC+ 0.3 V, all other inputs = 0 V)
Output leakage current
(DO is disabled, 0 V < V
OUT
< VCC)
Average VCC supply current -50 version
-60 version
Standby VCC supply current
(RAS = LCAS = UCAS = WE = VIH)
Average VCC supply current during
RAS-only refresh cycles -50 version
-60 version
Average VCC supply current during
fast page mode operation -50 version
-60 version
Standby VCC supply current
(RAS = LCAS = UCAS = WE = VCC– 0.2 V)
Average VCC supply current during
CAS-before-RAS refresh mode
-50 version
-60 version
I
I
I
I
I
I
I
I
IH
IL
OH
OL
I(L)
O(L)
CC1
CC2
CC3
CC4
CC5
CC6
min. max.
2.4 VCC+ 0.5 V
– 1.0 0.8 V
2.4 – V
– 0.4 V
– 10 10 µA
– 10 10 µA
– 190
mA
1
1
1
1
1
1
2, 3, 4
170
–2mA
–
190
mA
2, 4
170
–
160
mA
2, 3, 4
150
–1mA
–
190
mA
1
2, 4
170
Semiconductor Group 5 1998-10-01
HYB 514171BJ-50/-60
256k × 16 DRAM
Capacitance
T
= 0 to 70 °C; VCC = 5 V ± 10 %, f = 1 MHz
A
Parameter Symbol Limit Values Unit
min. max.
Input capacitance (A0 to A8) C
Input capacitance (RAS, UCAS, LCAS, WE, OE) C
Output capacitance (l/O1 to l/O16) C
AC Characteristics
T
= 0 to 70 °C; VSS = 0 V; VCC = 5 V ± 10 %, tT = 5 ns
A
5, 6
I1
I2
IO
–6pF
–7pF
–7pF
Parameter Symbol Limit Values Unit Note
-50 -60
min. max. min. max.
Common Parameters
Random read or write cycle time t
RAS precharge time t
RAS pulse width t
CAS pulse width t
Row address setup time t
Row address hold time t
Column address setup time t
Column address hold time t
RAS to CAS delay time t
RAS to column address delay time t
RAS hold time t
CAS hold time t
CAS to RAS precharge time t
Transition time (rise and fall) t
Refresh period t
RC
RP
RAS
CAS
ASR
RAH
ASC
CAH
RCD
RAD
RSH
CSH
CRP
T
REF
95 – 110 – ns
35 – 40 – ns
50 10k 60 10k ns
15 10k 15 10k ns
0–0–ns
10 – 10 – ns
0–0–ns
10 – 15 – ns
20 35 20 45 ns
15 25 15 30 ns
15 – 15 – ns
50 – 60 – ns
5–5–ns
3 50 3 50 ns
7
– 16 – 16 ms
Read Cycle
Access time from RAS t
Access time from CAS t
Access time from column address t
OE access time t
RAC
CAC
AA
OEA
– 50 – 60 ns
– 15 – 15 ns
– 25 – 30 ns
– 15 – 15 ns
8, 9
8, 9
8, 10
Semiconductor Group 6 1998-10-01
HYB 514171BJ-50/-60
256k × 16 DRAM
AC Characteristics (cont’d)
T
= 0 to 70 °C; VSS = 0 V; VCC = 5 V ± 10 %, tT = 5 ns
A
5, 6
Parameter Symbol Limit Values Unit Note
-50 -60
min. max. min. max.
Column address to RAS lead time t
Read command setup time t
Read command hold time t
Read command hold time ref. to RAS t
CAS to output in low-Z t
Output buffer turn-off delay from CAS t
Output buffer turn-off delay from OE t
Data to OE low delay t
CAS high to data delay t
OE high to data delay t
RAL
RCS
RCH
RRH
CLZ
OFF
OEZ
DZO
CDD
ODD
25 – 30 – ns
0–0–ns
0–0–ns
0–0–ns
0–0–ns
0 15 0 20 ns
0 15 0 20 ns
0–0–ns
15 – 20 – ns
15 - 20 – ns
11
11
8
12
12
13
14
14
Write Cycle
Write command hold time t
Write command pulse width t
Write command setup time t
Write command to RAS lead time t
Write command to CAS lead time t
Data setup time t
Data hold time t
Data to CAS low delay t
Read-Modify-Write Cycle
Read-write cycle time t
RAS to WE delay time t
CAS to WE delay time t
Column address to WE delay time t
OE command hold time t
WCH
WP
WCS
RWL
CWL
DS
DH
DZC
RWC
RWD
CWD
AWD
OEH
10 – 10 – ns
10 – 10 – ns
0–0–ns
15
15 – 15 – ns
15 – 15 – ns
0–0–ns
10 – 15 – ns
0–0–ns
16
16
13
140 – 160 – ns
75 – 90 – ns
40 – 45 – ns
50 – 60 – ns
15
15
15
15 – 20 – ns
Fast Page Mode Cycle
Fast page mode cycle time t
PC
35 – 40 – ns
Semiconductor Group 7 1998-10-01
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