Siemens HYB514100BJ-50, HYB514100BJ-60 Datasheet
4M × 1-Bit Dynamic RAM
Advanced Information
• 4 194 304 words by 1-bit organization
• 0 to 70 °C operating temperature
• Fast Page Mode Operation
• Performance:
HYB 514100BJ-50/-60
-50 -60
t
t
t
t
t
RAS access time 50 60 ns
RAC
CAS access time 13 15 ns
CAC
Access time from address 25 30 ns
AA
Read/Write cycle time 95 110 ns
RC
Fast page mode cycle time 35 40 ns
PC
• Single + 5 V (± 10 %) supply with a built-in VBB generator
• Low power dissipation
max. 660 mW active (-50 version)
max. 605 mW active (-60 version)
• Standby power dissipation:
11 mW max. standby (TTL)
5.5 mW max. standby (CMOS)
• Output unlatched at cycle end allows two-dimensional chip selection
• Read, write, read-modify write, CAS-before-RAS refresh, RAS-only refresh,
hidden refresh and test mode capability
• All inputs and outputs TTL-compatible
• 1024 refresh cycles/16 ms
• Plastic Packages: P-SOJ-26/20-2 with 300 mil width
Semiconductor Group 1 1998-10-01
HYB 514100BJ-50/-60
4M × 1 DRAM
The HYB 514100BJ is the new generation dynamic RAM organized as 4 194 304 words by 1-bit.
The HYB 514100BJ utilizes CMOS silicon gate process as well as advances circuit techniques to
provide wide operation margins, both internally and for the system user. Multiplexed address inputs
permit the HYB 514100BJ to be packed in a standard plastic P-SOJ-26/20 package. This package
size provides high system bit densities and is compatible with commonly used automatic testing and
insertion equipment. System oriented features include single + 5 V (± 10 %) power supply, direct
interfacing with high performance logic device families such as Schottky TTL.
Type Ordering Code Package Descriptions
HYB 514100BJ-50 Q67100-Q971 P-SOJ-26/20-2 300 mil DRAM (access time 50 ns)
HYB 514100BJ-60 Q67100-Q759 P-SOJ-26/20-2 300 mil DRAM (access time 60 ns)
P-SOJ-26/20-2
Pin Configuration
Pin Names
A0 – A10 Address Input
RAS Row Address Strobe
1
DI
2
WE
RAS
N.C.
3
4
5
A10
9
A1 A7
10
A2
11
A3
12
V
13 14
CC
26
25
24
23
22
18
17
16
15
SPP02808
V
SS
DO
CAS
N.C.
A9
A8A0
A6
A5
A4
CAS Column Address Strobe
WE Read/Write Input
DI Data In
DO Data Out
V
CC
V
SS
Power Supply (+ 5 V)
Ground (0 V)
N.C. No Connection
Semiconductor Group 2 1998-10-01
HYB 514100BJ-50/-60
4M × 1 DRAM
WE
CAS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
11
11
&
No.2 Clock
Generator
Column
Address
Buffers (11)
Refresh
Controller
Refresh
Counter (10)
10
Row
Address
Buffers (11)
10
Row
Decoder
11
.
.
.
1024
.
.
.
Data In
Buffer
Data Out
Buffer
Column
Decoder
Sense Amplifier
I/O Gating
...
4096
Memory Array
DI
DO
...
RAS
No.1 Clock
Generator
Substrate Bias
Generator
V
CC
V
SS
SPB02847
Block Diagram
Semiconductor Group 3 1998-10-01
HYB 514100BJ-50/-60
4M × 1 DRAM
Absolute Maximum Ratings
Operating temperature range ........................................................................................... 0 to 70 °C
Storage temperature range.................................................................................... – 55 to + 150 °C
Input/output voltage....................................................................................................... – 1 to + 7 V
Power Supply voltage.................................................................................................... – 1 to + 7 V
Data out current (short circuit) ............................................................................................... 50 mA
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
DC Characteristics
T
= 0 to 70 °C, VSS = 0 V, VCC= 5 10 %, tT = 5 ns
A
Parameter Symbol Limit Values Unit Test
Condition
1
1
1
1
1
1
2, 3
Input high voltage V
Input low voltage V
Output high voltage (I
Output low voltage (I
= – 5 mA) V
OUT
= 4.2 mA) V
OUT
Input leakage current, any input
(0 V < VIN < 7, all other input = 0 V)
Output leakage current
(DO is disabled, 0 < V
OUT
< VCC)
Average VCC supply current
-50 version
-60 version
I
I
I
IH
IL
OH
OL
I(L)
O(L)
CC1
min. max.
2.4 VCC+ 0.5 V
– 1.0 0.8 V
2.4 – V
– 0.4 V
– 10 10 µA
– 10 10 µA
–
–
120
110
mA
mA
Standby VCC supply current
I
CC2
–2mA
(RAS = CAS = WE = VIH)
Average VCC supply current during RAS-only
I
CC3
refresh cycles
-50 version
-60 version
Average VCC supply current during fast page
I
CC4
–
–
120
110
mA
mA
2
mode operation
-50 version
-60 version
–
–
80
70
mA
mA
2, 3
Semiconductor Group 4 1998-10-01
HYB 514100BJ-50/-60
4M × 1 DRAM
DC Characteristics (cont’d)
T
= 0 to 70 °C, VSS = 0 V, VCC= 5 10 %, tT = 5 ns
A
Parameter Symbol Limit Values Unit Test
min. max.
Standby VCC supply current I
Average VCC supply current during
I
CC5
CC6
–1mA
CAS-before-RAS refresh mode
-50 version
-60 version
–
–
120
110
mA
mA
Capacitance
T
= 0 to 70 °C, VCC= 5.0 V ±10%,f = 1 MHz
A
Parameter Symbol Limit Values Unit
Condition
1
2
min. max.
Input capacitance (A0 to A10, DI) C
Input capacitance (RAS, CAS, WE) C
Output capacitance (DO) C
AC Characteristics
T
= 0 to 70 °C, VCC=5V±10%,tT=5ns
A
5, 6
I1
I2
IO
–5pF
–7pF
–7pF
Parameter Symbol Limit Values Unit Note
-50 -60
min. max. min. max.
Common Parameters
Random read or write cycle time t
RAS precharge time t
RAS pulse width t
CAS pulse width t
Row address setup time t
Row address hold time t
Column address setup time t
Column address hold time t
RAS to CAS delay time t
RAS to column address delay time t
RAS hold time t
CAS hold time t
RC
RP
RAS
CAS
ASR
RAH
ASC
CAH
RCD
RAD
RSH
CSH
95 – 110 – ns
35 – 40 – ns
50 10k 60 10k ns
13 10k 15 10k ns
0– 0– ns
8 – 10 – ns
0– 0– ns
10 – 15 – ns
18 37 20 45 ns
13 25 15 30 ns
13 15 – ns
50 60 – ns
Semiconductor Group 5 1998-10-01
HYB 514100BJ-50/-60
4M × 1 DRAM
AC Characteristics (cont’d)
T
= 0 to 70 °C, VCC=5V±10%,tT=5ns
A
5, 6
Parameter Symbol Limit Values Unit Note
-50 -60
min. max. min. max.
CAS to RAS precharge time t
Transition time (rise and fall) t
Refresh period t
CRP
T
REF
5– 5– ns
3 50 3 50 ns
– 16 – 16 ms
7
Read Cycle
Access time from RAS t
Access time from CAS t
Access time from column address t
Column addr. to RAS lead time t
Read command setup time t
Read command hold time t
Read command hold time referenced to RAS t
CAS to output in low–Z t
Output buffer turn-off delay t
RAC
CAC
AA
RAL
RCS
RCH
RRH
CLZ
OFF
– 50 – 60 ns
– 13 – 15 ns
– 25 – 30 ns
25 – 30 – ns
0– 0– ns
0– 0– ns
0– 0– ns
0– 0– ns
0 13 0 15 ns
8, 9
8, 9
8, 10
11
11
8
12
Write Cycle
Write command hold time t
Write command pulse width t
Write command setup time t
Write command to RAS lead time t
Write command to CAS lead time t
Data setup time t
Data hold time t
Read-Modify-Write Cycle
Read-write cycle time t
RAS to WE delay time t
CAS to WE delay time t
Column address to WE delay time t
WCH
WP
WCS
RWL
CWL
DS
DH
RWC
RWD
CWD
AWD
8 – 10 – ns
8 – 10 – ns
0– 0– ns
13 – 15 – ns
13 – 15 – ns
0– 0– ns
10 – 10 – ns
115 – 130 – ns
50 – 60 – ns
13 – 15 – ns
25 – 30 – ns
13
14
14
13
13
13
Semiconductor Group 6 1998-10-01
HYB 514100BJ-50/-60
4M × 1 DRAM
AC Characteristics (cont’d)
T
= 0 to 70 °C, VCC=5V±10%,tT=5ns
A
5, 6
Parameter Symbol Limit Values Unit Note
-50 -60
min. max. min. max.
Fast Page Mode Cycle
Fast page mode cycle time t
CAS precharge time t
Access time from CAS precharge t
RAS pulse width t
CAS precharge to RAS Delay t
PC
CP
CPA
RAS
RHCP
35 – 40 – ns
10 – 10 – ns
– 30 – 35 ns
50 200k 60 200k ns
30 – 35 – ns
7
Fast Page Mode Read-Modify-Write Cycle
Fast page mode read-write cycle time t
CAS precharge to WE t
PRWC
CPWD
55 – 60 – ns
30 – 35 – ns
CAS-before-RAS Refresh Cycle
CAS setup time t
CAS hold time t
RAS to CAS precharge time t
Write to RAS precharge time t
Write hold time referenced to RAS t
CAS-before-RAS Counter Test Cycle
CAS precharge time t
Test Mode
Write command setup time t
Write command hold time t
CSR
CHR
RPC
WRP
WRH
CPT
WTS
WTH
10 – 10 – ns
10 – 10 – ns
5– 5– ns
10 – 10 – ns
10 – 10 – ns
35 – 40 – ns
10 – 10 – ns
10 – 10 – ns
Semiconductor Group 7 1998-10-01
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