Siemens HYB5117805BJ-50, HYB5117805BJ-60, HYB5117805BJ-70 Datasheet

2M x 8 - Bit Dynamic RAM
2k Refresh
(Hyper Page Mode- EDO)

Advanced Information

2 097 152 words by 8-bit organization

•

0 to 70 °C operating temperature

•

Performance:

•

HYB5117805BSJ -50/-60/-70

-50 -60 -70

t

RAC

t

CAC

t

AA

t

RC

t

HPC

RAS

access time 50 60 70 ns

CAS

access time 13 15 20 ns
Access time from address 25 30 35 ns
Read/Write cycle time 84 104 124 ns
Hyper page mode (EDO)

20 25 30 ns

cycle time

Single + 5 V (± 10 %) supply

•

Low power dissipation

•

max. 660 mW active (-50 version)
max. 605 mW active (-60 version)
max. 550 mW active (-70 version)
11 mW standby (TTL)

5.5. mW standby (MOS)

Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh,

•

self refresh and test mode

Hyper page mode (EDO) capability

•

All inputs, outputs and clocks fully TTL-compatible

•

2048 refresh cycles / 32 ms (2k-Refresh)

•

Plastic Package: P-SOJ-28-3 400 mil

•

Semiconductor Group 1 1.96

HYB5117805BSJ-50/-60/-70

2M x 8-EDO DRAM

The HYB 5117805BSJ is a 16 MBit dynamic RAM organized as 2 097 152 words by 8-bits. The HYB
5117805BSJ utilizes a submicron CMOS silicon gate process technology, as well as advanced
circuit techniques to provide wide operating margins, both internally and for the system user.
Multiplexed address inputs permit the HYB 5117805BSJ to be packaged in a standard SOJ 28
plastic package with 400 mil width. These packages provide high system bit densities and are
compatible with commonly used automatic testing and insertion equipment. System-oriented
features include single + 5 V (± 10 %) power supply, direct interfacing wit h hig h-performanc e l ogic
device families such as Schottky TTL.

Ordering Information
Type Ordering Code Package Descriptions

HYB 5117805BJ-50 Q67100-Q1104 P-SOJ-28-3 400 mil DRAM (access time 50 ns)
HYB 5117805BJ-60 Q67100-Q1105 P-SOJ-28-3 400 mil DRAM (access time 60 ns)
HYB 5117805BJ-70 Q67100-Q1106 P-SOJ-28-3 400 mil DRAM (access time 70 ns)

Pin Names

A0-A10 Row Address Inputs
A0-A9 Column Address Inputs
RAS
OE

Row Address Strobe

Output Enable
I/O1-I/O8 Data Input/Output
CAS
WE

V

CC

V

SS

Column Address Strobe

Read/Write Input

Power Supply (+ 5 V)

Ground (0 V)
N.C. not connected

Semiconductor Group 2

VCC

I/O1
I/O2

I/O3

I/O4

WE

RAS

N.C.
A10

A0

A1

A2
A3

VCC

P-SOJ-28-3 400 mil

O

1

2

3
4
5
6

7

28
27

26
25
24

23
22
218

9
10
11
12
13
14

20

19

18
17
16

15

HYB5117805BSJ-50/-60/-70

2M x 8-EDO DRAM

VSS
I/O8
I/O7
I/O6
I/O5
CAS

OE
A9

A8
A7
A6

A5
A4

VSS

Pin Configuration

Semiconductor Group 3

WE

HYB5117805BSJ-50/-60/-70

2M x 8-EDO DRAM

I

I/O1I/O2

/O8

A0

A1

A2
A3
A4
A5
A6
A7
A8
A9

A10

CAS

.

10

11 11

&

No. 2 Clock

Generator

Column

Address

Buffer(10)

Refresh

Controller

Refresh

Counter (1 1 )

11

Row

Address

Buffers(11)

Data in
Buffer

Row

Decoder

8

10

2048

Data out

Buffer

8

Column

Decoder

Sense Amplifier

I/O Gating

1024

x8

Memory Array

2048x1024x8

OE

8

No. 1 Clock

RAS

Block Diagram

Semiconductor Group 4

Generator

Voltage Down

Generator

VCC
VCC (internal)

HYB5117805BSJ-50/-60/-70

2M x 8-EDO DRAM

Absolute Maximum Ratings

Operating temperature range ............................................................................................0 to 70 °C

Storage temperature range.........................................................................................– 55 to 150 °C

Input/output voltage................................................................................-0.5 to min (Vcc+0.5,7.0) V

Power supply voltage...................................................................................................-1.0V to 7.0 V

Power dissipation.....................................................................................................................1.0 W

Data out current (short circuit)................................................................................................50 mA

Note:

Stresses above those listed under “Absolute Maximum Ratings” may cause perm anent dama ge of
the device. Exposure to absolute maximu m rating conditions for extended perio ds may affect device
reliability.

DC Characteristics

= 0 to 70 °C,

T

A

Parameter Symbol Limit Values Unit Test

Input high voltage
Input low voltage
Output high voltage (
Output low voltage (
Input leakage current

≤ Vcc + 0.3V, all other pins = 0 V)

(0 V ≤

V

IH

Output leakage current
(DO is disabled, 0 V ≤

Average

(RAS

, CAS, address cycling: tRC = tRC min.)

supply current:

V

CC

V

SS

= 0 V,

= – 5 mA)

I

OUT

= 4.2 mA)

I

OUT

V

OUT

= 5 V ± 10 %; tT = 2 ns

V

CC

≤ Vcc + 0.3V)

-50 ns version

-60 ns version

-70 ns version

V
V
V
V
I

I

I

IH

IL

OH

OL

I(L)

O(L)

CC1

mA
mA
mA

Condition

1)

1)

1)

1)

1)

1)

2) 3) 4)

2) 3) 4)

2) 3) 4)

min. max.

2.4 Vcc+0.5 V
– 0.5 0.8 V

2.4 – V
–0.4V
– 10 10 µA

– 10 10 µA

–
–
–

120
110
100

Standby

Average

supply current (RAS =CAS=

V

CC

supply current, during RAS-only

V

CC

)

V

IH

refresh cycles: -50 ns version

-60 ns version

-70 ns version

(RAS

cycling, CAS =

, tRC = tRC min.)

V

IH

Semiconductor Group 5

I
I

CC2

CC3

–2mA–

–
–
–

120
110
100

mA
mA
mA

2) 4)

2) 4)

2) 4)

HYB5117805BSJ-50/-60/-70

2M x 8-EDO DRAM

DC Characteristics

= 0 to 70 °C,

T

A

Parameter Symbol Limit Values Unit Test

V

SS

= 0 V,

= 5 V ± 10 %; tT = 2 ns

V

CC

min. max.

Condition

Average
during hyper page mode: -50 ns version

(RAS

=

Standby

= CAS =

(RAS
Average

before-RAS refresh mode: -50 ns version

(RAS

, CAS cycling: tRC = t

Average Self Refresh Current

(CBR cycle with tRAS>TRASSmin., CAS held low,
WE

=Vcc-0.2V, Address and Din= Vc c - 0.2 V or 0. 2V)

supply current,

V

CC

-60 ns version

-70 ns version

, CAS, address cycling:tPC = t

V

IL

supply current

V

CC

– 0.2 V)

V

CC

supply current, during CAS-

V

CC

-60 ns version

-70 ns version
min.)

RC

PC

min.)

I

I

I

I

CC4

CC5

CC6

CC7

–
–
–

70
55
45

–1mA

–
–
–

120
110
100

mA
mA
mA

mA
mA
mA

2) 3) 4)

2) 3) 4)

2) 3) 4)

1)

2) 4)

2) 4)

2) 4)

_1mA

Capacitance

= 0 to 70 °C,

T

A

= 5 V ± 10 %, f = 1 MHz

V

CC

Parameter Symbol Limit Values Unit

Input capacitance (A0 to A10)
Input capacitance (RAS

, CAS, WE, OE)

I/O capacitance (I/O1-I/O8)

Semiconductor Group 6

min. max.

C

I1

C

I2

C

IO

–5pF
–7pF
–7pF

HYB5117805BSJ-50/-60/-70

2M x 8-EDO DRAM

AC Characteristics

= 0 to 70 °C,

T

A

5 )6)

= 5 V ± 10 %, tT = 2 ns

V

CC

Parameter

common parameters

Random read or write cycle time t

precharge time t

RAS
RAS

pulse width t
pulse width t

CAS
Row address setup time t
Row address hold time t
Column address setup time t
Column address hold time t

to CAS delay time t

RAS
RAS

to column address delay t
hold time t

RAS
CAS

hold time t
to RAS precharge time t

CAS
Transition time (rise and fall) t
Refresh period t

Symbol

RC

RP

RAS

CAS

ASR

RAH

ASC

CAH

RCD

RAD

RSH

CSH

CRP

T

REF

16E

Limit Values

Unit Note

-50 -60 -70

min. max. min. max. min. max.

84 – 104 – 124 – ns
30 – 40 – 50 – ns
50 10k 60 10k 70 10k ns
8 10k 10 10k 12 10k ns
0–0–0–ns
8–10–10–ns
0–0–0–ns
8–10–12–ns
12 37 14 45 14 53 ns
10 25 12 30 12 35 ns
13 15 – 17 – ns
40 50 – 60 – ns
5–5–5–ns
150150150ns7
–32–32–32ms

Read Cycle

Access time from RAS
Access time from CAS
Access time from column address t

access time t

OE
Column address to RAS

lead time t
Read command setup time t
Read command hold time t
Read command hold time

t
t

t

RAC

CAC

AA

OEA

RAL

RCS

RCH

RRH

–50–60–70ns8, 9
–13–15–17ns8, 9
–25–30–35ns8,10
–13–15–17ns
25 – 30 – 35 – ns
0–0–0–ns
0–0–0–ns11
0–0–0–ns11

referenced to RAS
CAS

to output in low-Z t
Output buffer turn-off delay t
Output turn-off delay from OE

t

CLZ

OFF

OEZ

0–0–0–ns8
013015017ns12
013015017ns12

Semiconductor Group 7

HYB5117805BSJ-50/-60/-70

2M x 8-EDO DRAM

AC Charac teris tics

= 0 to 70 °C,

T

A

V

CC

(cont’d)

= 5 V ± 10 %, tT = 2 ns

5)6)

Parameter

Data to CAS low delay t
Data to OE

high to data delay t

CAS
OE

high to data delay t

low delay t

Write Cycle

Write command hold time t
Write command pulse width t
Write command setup time t
Write command to RAS
Write command to CAS

lead time t

lead time t
Data setup time t
Data hold time t

Symbol

DZC

DZO

CDD

ODD

WCH

WP

WCS

RWL

CWL

DS

DH

16E

Limit Values

Unit Note

-50 -60 -70

min. max. min. max. min. max.

0–0–0–ns13
0–0–0–ns13
10 – 13 – 15 – ns 14
10 – 13 – 15 – ns 14

8–10–10–ns
8–10–10–ns
0–0–0–ns15
13 – 15 – 17 – ns
13 – 15 – 17 – ns
0–0–0–ns16
8–10–12–ns16

Read-modify-Write Cycle

Read-write cycle time t
RAS

to WE delay time t
to WE delay time t

CAS
Column address to WE

command hold time t

OE

delay time t

Hyper Page Mode (EDO) Cycle

Hyper page mode (EDO) cycle
time

CAS

precharge time t

Access time from CAS

precharge t

Output data hold time t

pulse width in EDO mode t

RAS
CAS

precharge to RAS Delay t

RWC

RWD

CWD

AWD

OEH

t

HPC

CP

CPA

COH

RAS

RHPC

113 – 138 – 162 – ns
64 – 77 – 89 – ns 15
27 – 32 – 36 – ns 15
39 – 47 – 54 – ns 15
10 – 13 – 15 – ns

20 – 25 – 30 – ns

8–10–10–ns
–27–32–37ns7
5–5–5–ns
50 200k 60 200k 70 200k ns
27 – 32 – 37 – ns

Semiconductor Group 8