Siemens HYB5117800BSJ-50, HYB5117800BSJ-60, HYB5117800BSJ-70 Datasheet

2M x 8-Bit Dynamic RAM

Advanced Information

• 2 097 152 words by 8-bit organization

• 0 to 70 °C operating temperature

• Performance::

t

RAC

t

CAC

t

AA

t

RC

t

PC

RAS access time 50 60 70 ns
CAS access time 13 15 20 ns
Access time from address 25 30 35 ns
Read/Write cycle time 90 110 130 ns
Fast page mode cycle time 35 40 45 ns

HYB5117800BSJ-50/-60/-70

-50 -60 -70

• Single + 5 V (± 10 %) supply

• Low power dissipation

max. 660 active mW (-50 version)
max. 605 active mW (-60 version)
max. 550 active mW (-70 version)
11 mW standby (TTL)

5.5. mW standby (CMOS)

• Output unlatched at cycle end allows two-dimensional chip selection

• Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh,

self refresh and test mode

• Fast page mode capability

• All inputs, outputs and clocks fully TTL-compatible

• 2048 refresh cycles / 32 ms

• Plastic Package: P-SOJ-28-3 400 mil

Semiconductor Group 1 1.96

HYB 5117800BSJ-50/-60/-70

2M x 8-DRAM

The HYB 5117800BSJ is a 16 MBit dynamic RAM organized as 2097152 words by 8-bits. The HYB
5117800BSJ utilizes a submicron CMOS silicon gate process technology, as well as advanced
circuit techniques to provide wide operating margins, both internally and for the system user.
Multiplexed address inputs permit the HYB 5117800BSJ to be packaged in a standard SOJ 28
400 mil plastic package. Thes e packages provide high s ystem bit densities and are compat ible with
commonly used automatic testing and insertion equipment . System-oriented features i nclude single
+ 5 V (± 10 %) power supply, direct interfac ing with high-performance logic device fam ilies such as
Schottk y TTL.

Ordering Information
Type Ordering Code Package Descriptions

HYB 5117800BSJ-50 Q67100-Q1092 P-SOJ-28-3 400 mil DRAM (access time 50 ns)
HYB 5117800BSJ-60 Q67100-Q1093 P-SOJ-28-3 400 mil DRAM (access time 60 ns)
HYB 5117800BSJ-70 Q67100-Q1094 P-SOJ-28-3 400 mil DRAM (access time 70 ns)

Pin Names

A0 to A10 Row Address Inputs
A0 to A9 Column Address Inputs
RAS
OE

Row Address Strobe

Output Enable
I/O1-I/O8 Data Input/Output
CAS
WE

V

CC

V

SS

Column Address Strobe

Read/Write Input

Power Supply (+ 5 V)

Ground (0 V)
N.C. not connected

Semiconductor Group 2

VCC

I/O1
I/O2

I/O3

I/O4

WE

RAS

N.C.
A10

A0

A1

A2
A3

VCC

P-SOJ-28-3 (400mil)

O

1

2
3

4
5
6

7

28
27

26
25
24

23
22
218

9
10
11
12
13
14

20

19

18
17
16

15

HYB 5117800BSJ-50/-60/-70

2M x 8-DRAM

VSS
I/O8
I/O7
I/O6
I/O5
CAS

OE
A9

A8
A7
A6

A5
A4

VSS

Pin Configuration

Semiconductor Group 3

HYB 5117800BSJ-50/-60/-70

2M x 8-DRAM

A0

A1

A2
A3
A4
A5
A6
A7
A8
A9

A10

WE

CAS

.

10

11 11

&

No. 2 Clock

Generator

Column

Address

Buffer(10)

Refresh

Controller

Refresh

Counter (11)

11

Row

Address

Buffers(11)

I/O1 I/O2

Data in
Buffer

Row

Decoder

8

10

2048

I/O8

Data out

Buffer

8

Column

Decoder

Sense Amplifier

I/O Gating

1024

x8

Memory Array

2048x1024x8

OE

8

RAS

Block Diagram

Semiconductor Group 4

No. 1 Clock

Generator

Voltage Down

Generator

VCC
VCC (internal)

HYB 5117800BSJ-50/-60/-70

2M x 8-DRAM

Absolute Maximum Ratings

Operating temperature range .......................... ............ ............ ............ ................... ...........0 to 70 °C

Storage temperature range.................................... ........ ........ ........ ........ ........... ........ ..– 55 to 150 °C

Input/output volt age............. .... .. .... .... .... .... .. .... .... .... .... .... .. .... .... .... .... .. ...-0.5 to min (Vcc+0.5,7.0) V

Power supply voltage...................................................................................................-1.0V to 7.0 V

Power dissipation..................... ...... ...... .... ...... ...... ...... ...... ...... ...... .... ...... ......... ...... ...... ...... .... ...1.0 W

Data out current (short circuit)................................................................................................50 mA

Note:

Stresses above those list ed under “Absolute M aximum Ratings ” ma y cause permanent damage of
the device. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

DC Characteristics

T

= 0 to 70 °C, VSS = 0 V, VCC = 5 V ± 10 %, tT = 5 ns

A

Parameter Symbol Limit Values Unit Test

mA
mA
mA

Condition

1)

1)

1)

1)

1)

1)

2) 3) 4)

2) 3) 4)

2) 3) 4)

Input high voltage
Input low voltage V
Output high voltage (I
Output low voltage (I

= – 5 mA) V

OUT

= 4.2 mA) V

OUT

Input leakage current,any input
(0 V ≤

V

≤ Vcc + 0.3V, all other pins = 0 V)

IH

Output leakage current
(DO is disabled, 0 V ≤

V

≤ Vcc + 0.3V)

OUT

Average VCC supply current:

-50 ns version

-60 ns version

-70 ns version

(RAS

, CAS, address cycling, tRC = tRC min.)

V

I

I

I

IH

IL

OH

OL

I(L)

O(L)

CC1

min. max.

2.4 Vcc+0.5 V
– 0.5 0.8 V

2.4 – V
– 0.4 V
– 10 10 µA

– 10 10 µA

–
–
–

120
110
100

Standby VCC supply current (RAS =CAS= VIH) I

V

Average

supply current, during RAS-only

CC

refresh cycles: -50 ns version

-60 ns version

-70 ns version

(RAS

cyc ling: CAS = VIH, tRC = tRC min.)

Semiconductor Group 5

I

CC2

CC3

–2mA–

–
–
–

120
110
100

mA
mA
mA

2) 4)

2) 4)

2) 4)

HYB 5117800BSJ-50/-60/-70

2M x 8-DRAM

DC Characteristics

T

= 0 to 70 °C, VSS = 0 V, VCC = 5 V ± 10 %, tT = 5 ns

A

(cont’d)

Parameter Symbol Limit Values Unit Test

mA
mA
mA

mA
mA
mA

Condition

2) 3) 4)

2) 3) 4)

2) 3) 4)

1)

2) 4)

2) 4)

2) 4)

Average

V

supply current,

CC

during fast page mode: -50 ns vers ion

-60 ns version

-70 ns version

(RAS

= VIL, CAS, address cycling,tPC = t

PC

min.)

Standby VCC supply current
(RAS

= CAS = VCC – 0.2 V)

Average VCC supply current, during CAS­before-RAS refresh mode: -50 ns version

-60 ns version

-70 ns version

(RAS

, CAS cycling, tRC = t

RC

min.)

Average Self Refresh Current

(CBR cycle with tRAS>TRASSmin., CAS held low,

=Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V)

WE

I

I

I

I

CC4

CC5

CC6

CC7

min. max.

–
–
–

40
35
30

–1mA

–
–
–

120
110
100

_1mA

Capacitance

T

= 0 to 70 °C,VCC = 5 V ± 10 %, f = 1 MHz

A

Parameter Symbol Limit Values Unit

min. max.

Input capacitance (A0 to A10)
Input capacitance (RAS

, CAS, WE, OE) C

I/O capacitance (I/O1-I/O8)

C

I1

I2

C

IO

–5pF
–7pF
–7pF

Semiconductor Group 6

HYB 5117800BSJ-50/-60/-70

2M x 8-DRAM

AC Characteristics

T

= 0 to 70 °C,VCC = 5 V ± 10 %, tT = 5 ns

A

Parameter

5)6)

Symbol

common parameters

Random read or write cycle time t

precharge time t

RAS

pulse width t

RAS

pulse width t

CAS
Row address setup time t
Row address hold time t
Column address setup time t
Column address hold time t

to CAS delay time t

RAS

to column address delay

RAS

t

RC

RP

RAS

CAS

ASR

RAH

ASC

CAH

RCD

RAD

time

Limit Values

Unit Note

-50 -60 -70

min. max. min. max. min. max.

90 – 110 – 130 – ns
30 – 40 – 50 – ns
50 10k 60 10k 70 10k ns
13 10k 15 10k 20 10k ns
0–0–0–ns
8 – 10 – 10 – ns
0–0–0–ns
10 – 15 – 15 – ns
18 37 20 45 20 50
13 25 15 30 15 35 ns

16F

hold time t

RAS

hold time t

CAS

to RAS precharge time t

CAS
Transition time (rise and fall) t
Refresh period t

Read Cycle

Access time from RAS t
Access time from CAS
Access time from colum n address t

access time t

OE
Column address to RAS

lead time t
Read command setup time t
Read command hold time t
Read command hold time

referenced to RAS
CAS

to output in low-Z t

Output buffer turn-off delay t

t

t

RSH

CSH

CRP

T

REF

RAC

CAC

AA

OEA

RAL

RCS

RCH

RRH

CLZ

OFF

13 15 – 20 – ns
50 60 – 70 – ns
5–5–5–ns
350350350ns7
– 32 – 32 – 32 ms

– 50 – 60 – 70 ns 8, 9
– 13 – 15 – 20 ns 8, 9
– 25 – 30 – 35 ns 8,10
– 13 – 15 – 20 ns
25 – 30 – 35 – ns
0–0–0–ns
0–0–0–ns11
0–0–0–ns11

0–0–0–ns8
0 13 0 15 0 20 ns 12

Semiconductor Group 7

HYB 5117800BSJ-50/-60/-70

2M x 8-DRAM

AC Characteristics

T

= 0 to 70 °C,VCC = 5 V ± 10 %, tT = 5 ns

A

(cont’d)

Parameter

Output buffer turn-off delay from OEt

Data to O E
CAS

high to data delay t

OE

low delay t

high to data delay t

5)6)

Symbol

OEZ

DZO

CDD

ODD

Write Cycle

Write command hold time t
Write command pulse width t
Write command setup time t
Write command to RAS
Write command to CAS

lead time t

lead time t
Data setup time t
Data hold time t
Data to CAS

low delay t

WCH

WP

WCS

RWL

CWL

DS

DH

DZC

16F

Limit Values

Unit Note

-50 -60 -70

min. max. min. max. min. max.

0 13 0 15 0 20 ns 12

0–0–0–ns13
13 – 15 – 20 – ns 14
13 – 15 – 20 – ns 14

8 – 10 – 10 – ns
8 – 10 – 10 – ns
0–0–0–ns15
13 – 15 – 20 – ns
13 – 15 – 20 – ns
0–0–0–ns16
10 – 10 – 15 – ns 16
0–0–0–ns13

Read-Modify-Write Cycle

Read-write cycle time t

to WE delay time t

RAS

to WE delay time t

CAS
Column address to WE

command hold t ime t

OE

delay time t

RWC

RWD

CWD

AWD

OEH

126 – 150 – 180 – ns
68 – 80 – 95 – ns 15
31 – 35 – 45 – ns 15
43 – 50 – 60 – ns 15
13 – 15 – 20 – ns

Fast Page Mo de Cycle

Fast page mode cycle time t

precharge time t

CAS
Access t ime from C AS

pulse width t

RAS

precharge to RAS Delay t

CAS

precharge t

PC

CP

CPA

RAS

RHPC

35 – 40 – 45 – ns
10 – 10 – 10 – ns
–30–35–40ns7
50 200k 60 200k 70 200k ns
30 – 35 – 40 – ns

Semiconductor Group 8