Siemens HYB5116400BJ-50, HYB5116400BJ-60, HYB5116400BJ-70, HYB5116400BT-50, HYB5116400BT-60 Datasheet

4M x 4-Bit Dynamic RAM

Advanced Information

4 194 304 words by 4-bit organization

•

0 to 70 °C operating temperature

•

Performance:

•

HYB5116400BJ -50/-60/-70

HYB5116400BT -50/-60/-70

-50 -60 -70

t

RAC

t

CAC

t

AA

t

RC

t

PC

Single + 5 V (± 10 %) supply

•

Low power dissipation

•

RAS

access time 50 60 70 ns

CAS

access time 13 15 20 ns
Access time from address 25 30 35 ns
Read/Write cycle time 90 110 130 ns
Fast page mode cycle time 35 40 45 ns

max. 550 active mW (-50 version)
max. 495 active mW (-60 version)
max. 440 active mW (-70 version)
11 mW standby (TTL)

5.5. mW standby (MOS)

Output unlatched at cycle end allows two-dimensional chip selection

•

Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh,

•

self refresh and test mode

Fast page mode capability

•

All inputs, outputs and clocks fully TTL-compatible

•

4096 refresh cycles / 64 ms

•

Plastic Package: P-SOJ-26/24 300 mil

•

P TSOPII-26/24 300 mil

Semiconductor Group 1 1.96

HYB 5116400BJ/BT-50/-60/-70

4M x 4-DRAM

The HYB 5116400BJ/BT is a 16MBit dynamic RAM organized as 4194304 words by 4-bits. The
HYB 5116400BJ/BT utilizes a submicron CMOS silicon gate process technology, as well as
advanced circuit techniques to provide wide operating margins, both internally and for the system
user. Multiplexed address input s permit the HYB 5116400BJ/ BT to be packaged in a standard SOJ
26/24 or TSOPII-26/24 plastic package, both with 300 mil width. These packages provide high
system bit densities and are compatible with commonly used automatic testing and insertion
equipment. System-oriented features include sin gle + 5 V (± 10 %) power s upply, direct interfacing
with high-performance logic device families such as Schottky TTL.

Ordering Information
Type Ordering Code Package Descriptions

HYB 5116400BJ-50 Q67100-Q1049 P-SOJ-26/24 300 mil DRAM (access time 50 ns)
HYB 5116400BJ-60 Q67100-Q1050 P-SOJ-26/24 300 mil DRAM (access time 60 ns)
HYB 5116400BJ-70 Q67100-Q1051 P-SOJ-26/24 300 mil DRAM (access time 70 ns)
HYB 5116400BT-50 on request P-TSOPII-26/24 300mil DRAM (access time 50 ns)
HYB 5116400BT-60 on request P-TSOPII-26/24 300mil DRAM (access time 60 ns)
HYB 5116400BT-70 on request P-TSOPII-26/24 300mil DRAM (access time 70 ns)

Pin Names

A0-A11 Row Address Inputs
A0-A9 Column Address Inputs
RAS
OE

Row Address Strobe

Output Enable
I/O1-I/O4 Data Input/Output
CAS
WE

V

CC

V

SS

Column Address Strobe

Read/Write Input

Power Supply (+ 5 V)

Ground (0 V)
N.C. not connected

Semiconductor Group 2

HYB 5116400BJ/BT-50/-60/-70

4M x 4-DRAM

Vcc
I/O1
I/O2
WE
RAS
A11

A10
A0
A1
A2
A3
VCC

1
2
3
4
5
6

8
9
10
11
12
13

P-SOJ-26/24 300 mil
P-TSOPII-26/24 300 mil

26
25
24
23
22
21

19
18
17
16
15
14

Vss
I/O4
I/O3
CAS
OE
A9

A8
A7
A6
A5
A4
Vss

Pin Configuration

Semiconductor Group 3

WE

HYB 5116400BJ/BT-50/-60/-70

4M x 4-DRAM

I/O1 I/O2 I/O3 I/O4

A0

A1
A2
A3
A4
A5
A6
A7
A8
A9

A10
A11

CAS

.

10

12 12

&

No. 2 Clock

Generator

Column

Address

Buffer(10)

Refresh

Controller

Refresh

Counter (12)

12

Row

Address

Buffers(12)

Data in
Buffer

Row

Decoder

4

10

4096

Data out

Buffer

4

Column

Decoder

Sense Amplifier

I/O Gating

1024

x4

Memory Array

4096x1024x4

OE

4

No. 1 Clock

RAS

Block Diagram

Semiconductor Group 4

Generator

Voltage Down

Generator

VCC
VCC (internal)

HYB 5116400BJ/BT-50/-60/-70

4M x 4-DRAM

Absolute Maximum Ratings

Operating temperature range ............................................................................................0 to 70 °C

Storage temperature range.........................................................................................– 55 to 150 °C

Input/output voltage................................................................................-0.5 to min (Vcc+0.5,7.0) V

Power supply voltage...................................................................................................-1.0V to 7.0 V

Power dissipation.....................................................................................................................1.0 W

Data out current (short circuit)................................................................................................50 mA

Note:

Stresses above those listed under “Absolute Maximum Ratings” may cause perm anent dama ge of
the device. Exposure to absolute maximu m rating conditions for extended perio ds may affect device
reliability.

DC Characteristics

= 0 to 70 °C,

T

A

Parameter Symbol Limit Values Unit Test

Input high voltage
Input low voltage
Output high voltage (
Output low voltage (
Input leakage current

(0 V ≤

≤ Vcc + 0.3V, all other pins = 0 V)

V

IH

Output leakage current
(DO is disabled, 0 V ≤

supply current:

Average

(RAS

V

CC

, CAS, address cycling: tRC = tRC min.)

V

SS

= 0 V,

= – 5 mA)

I

OUT

= 4.2 mA)

I

OUT

V

OUT

= 5 V ± 10 %; tT = 5 ns

V

CC

≤ Vcc + 0.3V)

-50 ns version

-60 ns version

-70 ns version

V
V
V
V
I

I

I

IH

IL

OH

OL

I(L)

O(L)

CC1

mA
mA
mA

Condition

1)

1)

1)

1)

1)

1)

2) 3) 4)

2) 3) 4)

2) 3) 4)

min. max.

2.4 Vcc+0.5 V
– 0.5 0.8 V

2.4 – V
–0.4V
– 10 10 µA

– 10 10 µA

–
–
–

100
90
80

Standby

Average

supply current (RAS =CAS=

V

CC

supply current, during RAS-only

V

CC

)

V

IH

refresh cycles: -50 ns version

-60 ns version

-70 ns version

(RAS

cycling, CAS =

, tRC = tRC min.)

V

IH

Semiconductor Group 5

I
I

CC2

CC3

–2mA–

–
–
–

100
90
80

mA
mA
mA

2) 4)

2) 4)

2) 4)

HYB 5116400BJ/BT-50/-60/-70

4M x 4-DRAM

DC Characteristics

= 0 to 70 °C,

T

A

V

SS

(cont’d)

= 0 V,

= 5 V ± 10 %; tT = 5 ns

V

CC

Parameter Symbol Limit Values Unit Test

mA
mA
mA

mA
mA
mA

Condition

2) 3) 4)

2) 3) 4)

2) 3) 4)

1)

2) 4)

2) 4)

2) 4)

Average

supply current,

V

CC

during fast page mode: -50 ns version

-60 ns version

-70 ns version

(RAS

=

Standby

= CAS =

(RAS
Average

, CAS, address cycling:tPC = t

V

IL

supply current

V

CC

– 0.2 V)

V

CC

supply current, during CAS-

V

CC

PC

min.)

before-RAS refresh mode: -50 ns version

-60 ns version

-70 ns version

(RAS

, CAS cycling: tRC = t

RC

min.)

Average Self Refresh Current

(CBR cycle with tRAS>TRASSmin., CAS held low,
WE

=Vcc-0.2V, Address and Din=Vcc--0.2V or 0.2V)

I

I

I

I

CC4

CC5

CC6

CC7

min. max.

–
–
–

40
35
30

–1mA

–
–
–

100
90
80

_1mA

Capacitance

= 0 to 70 °C,

T

A

= 5 V ± 10 %, f = 1 MHz

V

CC

Parameter Symbol Limit Values Unit

min. max.

Input capacitance (A0 to A11)
Input capacitance (RAS

, CAS, WE, OE)

I/O capacitance (I/O1-I/O4)

C

I1

C

I2

C

IO

–5pF
–7pF
–7pF

Semiconductor Group 6

HYB 5116400BJ/BT-50/-60/-70

4M x 4-DRAM

AC Characteristics

= 0 to 70 °C,

T

A

5)6)

= 5 V ± 10 %, tT = 5 ns

V

CC

Parameter

common parameters

Random read or write cycle time t
RAS

precharge time t
pulse width t

RAS
CAS

pulse width t
Row address setup time t
Row address hold time t
Column address setup time t
Column address hold time t

to CAS delay time t

RAS
RAS

to column address delay
time

Symbol

RC

RP

RAS

CAS

ASR

RAH

ASC

CAH

RCD

t

RAD

Limit Values

Unit Note

-50 -60 -70

min. max. min. max. min. max.

90 – 110 – 130 – ns
30 – 40 – 50 – ns
50 10k 60 10k 70 10k ns
13 10k 15 10k 20 10k ns
0–0–0–ns
8–10–10–ns
0–0–0–ns
10 – 15 – 15 – ns
18 37 20 45 20 50
13 25 15 30 15 35 ns

16F

hold time t

RAS
CAS

hold time t

to RAS precharge time t

CAS
Transition time (rise and fall) t
Refresh period t

Read Cycle

Access time from RAS
Access time from CAS
Access time from column address t

access time t

OE
Column address to RAS

lead time t
Read command setup time t
Read command hold time t
Read command hold time

referenced to RAS
CAS

to output in low-Z t

Output buffer turn-off delay t

t
t

t

RSH

CSH

CRP

T

REF

RAC

CAC

AA

OEA

RAL

RCS

RCH

RRH

CLZ

OFF

13 15 – 20 – ns
50 60 – 70 – ns
5–5–5–ns
350350350ns7
–64–64–64ms

–50–60–70ns8, 9
–13–15–20ns8, 9
–25–30–35ns8,10
–13–15–20ns
25 – 30 – 35 – ns
0–0–0–ns
0–0–0–ns11
0–0–0–ns11

0–0–0–ns8
013015020ns12

Semiconductor Group 7

HYB 5116400BJ/BT-50/-60/-70

4M x 4-DRAM

AC Characteristics

= 0 to 70 °C,

T

A

V

CC

(cont’d)

= 5 V ± 10 %, tT = 5 ns

5)6)

Parameter

Output buffer turn-off delay from
OE

Data to OE

high to data delay t

CAS
OE

high to data delay t

low delay t

Write Cycle

Write command hold time t
Write command pulse width t
Write command setup time t
Write command to RAS
Write command to CAS

lead time t

lead time t
Data setup time t
Data hold time t
Data to CAS

low delay t

Symbol

t

OEZ

DZO

CDD

ODD

WCH

WP

WCS

RWL

CWL

DS

DH

DZC

16F

Limit Values

Unit Note

-50 -60 -70

min. max. min. max. min. max.

013015020ns12

0–0–0–ns13
13 – 15 – 20 – ns 14
13 – 15 – 20 – ns 14

8–10–10–ns
8–10–10–ns
0–0–0–ns15
13 – 15 – 20 – ns
13 – 15 – 20 – ns
0–0–0–ns16
10 – 10 – 15 – ns 16
0–0–0–ns13

Read-Modify-Write Cycle

Read-write cycle time t

to WE delay time t

RAS
CAS

to WE delay time t
Column address to WE
OE

command hold time t

delay time t

RWC

RWD

CWD

AWD

OEH

126 – 150 – 180 – ns
68 – 80 – 95 – ns 15
31 – 35 – 45 – ns 15
43 – 50 – 60 – ns 15
13 – 15 – 20 – ns

Fast Page Mode Cycle

Fast page mode cycle time t
CAS

precharge time t
Access time from CAS
RAS

pulse width t

precharge to RAS Delay t

CAS

precharge t

PC

CP

CPA

RAS

RHPC

35 – 40 – 45 – ns
10 – 10 – 10 – ns
–30–35–40ns7
50 200k 60 200k 70 200k ns
30 – 35 – 40 – ns

Semiconductor Group 8