Siemens E61 Service Manual
Release 1.0
Service Repair Documentation
Level 3 - E61
Release Date Department Notes to change
R 1.0
Technical Documentation
TTD_Repair_L3 _Theory of Operation_E61_R1.0.pdf Page 1 of 33
12.05.2006 BenQ S CC CES New document
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Release 1.0
Table of Content
1 Introduction ...............................................................................................................................3
1.1 PURPOSE...............................................................................................................................3
1.2 SCOPE ...................................................................................................................................3
1.3 TERMS AND ABBREVIATIONS ...................................................................................................3
2 List of available level 3 parts....................................................................................................4
3 Required Equipment for Level 3 ..............................................................................................6
4 Required Software for Level 3..................................................................................................6
5 Radio Part ..................................................................................................................................7
5.1 RECEIVER OPERATION............................................................................................................7
5.2 TRANSMITTER OPERATION......................................................................................................8
5.3 VCXO OPERATION.................................................................................................................9
6 Logic (Base-Band)...................................................................................................................10
6.1 CALYPSO..............................................................................................................................12
6.2 IOTA....................................................................................................................................15
6.3 POWER SUPPLY ...................................................................................................................19
6.3.1 System power on/off Sequence ...................................................................................20
6.4 MEMORY CIRCUIT .................................................................................................................21
6.5 LCD MODULE (LCDM)..........................................................................................................23
6.6 CAMERA MODULE.................................................................................................................24
7 Interfaces .................................................................................................................................25
7.1 AUDIO CODEC AND AUDIO AMPLIFIER....................................................................................25
7.1.1 Audio codec function block...........................................................................................25
7.1.2 Multimedia Application Input Circuit Design.................................................................26
7.1.3 Multimedia Application Output Circuit Design..............................................................27
7.1.4 Loudspeaker output path and D-amplifier design.........................................................27
7.2 10 PINS I/O CONNECTOR ......................................................................................................28
7.3 MINI-SD CARD .....................................................................................................................29
7.4 KEYPAD LED CIRCUIT...........................................................................................................30
7.5 VIBRATOR ............................................................................................................................30
7.6 KEYPAD................................................................................................................................31
8 Charging circuit.......................................................................................................................33
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1 Introduction
1.1 Purpose
This Service Repair Documentation is intended to carry out repairs on BenQ repair level 3-4.
1.2 Scope
This document is the reference document for all BenQ authorised Service Partners which are
released to repair Siemens mobile phones up to level 3.
1.3 Terms and Abbreviations
Technical Documentation
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2 List of available level 3 parts
Product ID Order Number Description CM
E61
E61
E61
E61
E61
E61
E61
E61
E61
E61
E61
E61
E61
E61
E61
E61 RT1 L50622-f4103-k NTC10K0402NTH5GBQ6J.60009.001
E61 T9 L50640-D110-D670 DISDIODETVM0A090MIRYBQ6J.80009.011
E61 T2 L50640-D128-D670 DISDIODESFI0402ML120CBQ6J.80018.011
E61 T3 L50640-D128-D670 DISDIODESFI0402ML120CBQ6J.80018.011
E61 T4 L50640-D128-D670 DISDIODESFI0402ML120CBQ6J.80018.011
E61 T1 L50640-D129-D670 DISDIODE0402-050E560NPBQ6J.80018.031
E61 T5 L50640-D129-D670 DISDIODE0402-050E560NPBQ6J.80018.031
E61 T7 L50640-D129-D670 DISDIODE0402-050E560NPBQ6J.80018.031
E61 T8 L50640-D129-D670 DISDIODE0402-050E560NPBQ6J.80018.031
E61 CB57 L50640-D130-D670 DISDIODESFI0402-050E47BQ6J.80018.041
E61 CB58 L50640-D130-D670 DISDIODESFI0402-050E47BQ6J.80018.041
E61 TVS4C1 L50640-D119-D670 DISDIODETVSSFI0508-050RBQ6J.80022.011
E61 TVS4C2 L50640-D119-D670 DISDIODETVSSFI0508-050RBQ6J.80022.011
E61 CN1 L50664-F6220-K CAPARRAY22P50VJ0805SBQ7G.62203.0C1
E61 CN2 L50664-F6220-K CAPARRAY22P50VJ0805SBQ7G.62203.0C1
E61 CN3 L50664-F6220-K CAPARRAY22P50VJ0805SBQ7G.62203.0C1
E61 DN1 L50640-D5121-D670 DISDIODEARRDAN222BQ8C.00222.0A0
E61 D601 L50640-D124-D670 DISDIODEVARHVD358BKRF-EBQ8C.00358.090
E61 D1 L50640-D5110-D670 DISDIODERB520S-30BQ8C.00520.080
E61 LED3 L50640-L2179-D670 DISOPT19-213AUWD/S365-2BQ8C.19213.071
E61 LED4 L50640-L2179-D670 DISOPT19-213AUWD/S365-2BQ8C.19213.071
E61 LED5 L50640-L2179-D670 DISOPT19-213AUWD/S365-2BQ8C.19213.071
E61 LED6 L50640-L2179-D670 DISOPT19-213AUWD/S365-2BQ8C.19213.071
DCJ
SPCON
LCDM
DSC
BATC1
BATC2
IOJ
ANT1
KPCON
SIM
MINISD
TKCON1
TKCON2
F1
F2
L50634-Z97-C553 CONNDCPWRPA05302-QNJBQ2B.13120.021
L50634-Z97-C557 CONN24PD.4H1.5AXK824145YBQ2K.L1142.024
L50634-Z97-C562 CONN30PD5H185AXK5F30545YBQ2K.L1143.030
L50634-Z97-C668 CONNSKT24PD.4AXK724245BQ2K.L1165.024
L50634-Z97-C664 CONNBATTCBE-3111-2769HBQ2K.N0079.011
L50634-Z97-C665 CONNBATT2PJ-3111H-2-25BQ2K.N0079.071
L50634-Z97-C558 CONNI/O10PP0.5BQ2K.N0081.001
L50634-Z97-C666 CONNSPRING2PN027M4-2I3BQ2K.N0082.031
L50634-Z97-C667 CONNBTB14PFBF05314BQNBQ2K.N1003.021
L50634-Z97-C659 CONNSIMCARDBM05106-L5BQ2K.N5030.021
L50634-Z97-C669 CONNSDMINI11P48050-3BQ2K.N5037.011
L50634-Z97-C670 CONNVOLUMAV4040-A0G12BQ2K.P0003.004
L50634-Z97-C670 CONNVOLUMAV4040-A0G12BQ2K.P0003.004
L50645-A820-Y48 FUSE1.25A32VF04671BQ6J.41251.001
L50645-A820-Y48 FUSE1.25A32VF04671BQ6J.41251.001
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E61 LED7 L50640-L2179-D670 DISOPT19-213AUWD/S365-2BQ8C.19213.071
E61 LED8 L50640-L2179-D670 DISOPT19-213AUWD/S365-2BQ8C.19213.071
E61 LED9 L50640-L2179-D670 DISOPT19-213AUWD/S365-2BQ8C.19213.071
E61 LED10 L50640-L2179-D670 DISOPT19-213AUWD/S365-2BQ8C.19213.071
E61 D4 L50640-D5123-D670 DISDIODERB161M-20BQ8C.1R002.08Q
E61 D5 L50640-D5124-D670 DISDIODEPMEG2020EJBQ8C.2R002.A8F
E61 D601 L50640-D5124-D670 DISDIODEPMEG2020EJBQ8C.2R002.A8F
E61 DZB1 L50640-D3142-D670 DISDIODEZEN6.06-6.33VBQ8C.6R205.03F
E61 D2 L50640-D5125-D670 DISDIODE1PS79SB30BQ8C.R2004.A84
E61 D3 L50640-D5125-D670 DISDIODE1PS79SB30BQ8C.R2004.A84
E61 B1 L50640-C2149-D670 DISTRANSPEMH9NPNBQ8D.00009.010
E61 B3 L50640-C2167-D670 DISTRANSUMH10NNPNBQ8D.00010.01F
E61 B2 L50640-C2143-D670 DISTRANSBC807-40WPNPBQ8D.00807.A1K
E61 FN1 L50630-C1198-D670 DISTRANSFDG6303NBQ8D.06303.03K
E61 FP1 L50630-C1186-D670 DISTRANSFETFDC6306PBQ8D.06306.030
E61 FP3 L50630-C1186-D670 DISTRANSFETFDC6306PBQ8D.06306.030
E61 FP2 L50630-C1187-D670 DISTRANSFETFDC6506PBQ8D.06506.030
E61 U67 L50645-K280-Y420 FILSAW1842.5MHZSAFEH1GBQ6J.10151.001
E61 U68 L50645-K280-Y421 FILSAW942.5MHZSAFEH942MBQ6J.10152.001
E61 U66 L50645-K280-Y437 FILSAW1960MHSAFEH1G96FBBQ6J.10154.001
E61 EMI2 L50645-K280-Y453 FILLFA24-2A1A144MTBQ6J.10189.001
E61 EMI3 L50645-K280-Y453 FILLFA24-2A1A144MTBQ6J.10189.001
E61 EMI4 L50645-K280-Y453 FILLFA24-2A1A144MTBQ6J.10189.001
E61 EMI5 L50645-K280-Y453 FILLFA24-2A1A144MTBQ6J.10189.001
E61 EMI6 L50645-K280-Y467 FILLFB20-3D1E471MBQ6J.10189.011
E61 EMI7 L50645-K280-Y467 FILLFB20-3D1E471MBQ6J.10189.011
E61 IOTA L50610-U6243-D670 ICINTFTWL3025BZGMRBQ7A.03025.B0U
E61 SHJ2SL L50610-G6322-D670 ICCPUSH7327-DH6417327BQ7A.07327.00U
E61 G2 L50645-J4683-Y34 ICASICD751992AZHHRBQ7A.75199.A0U
E61 AND1 L50610-B6250-D670 ICLOGINL17SZ08XV5T2BQ7C.17085.090
E61 AND2 L50610-B6250-D670 ICLOGINL17SZ08XV5T2BQ7C.17085.090
E61 OR1 L50610-B6251-D670 ICLOGINL17SZ32XV5T2BQ7C.17325.09H
E61 BR13M L50610-B6252-D670 ICLOGISN74AVC1T45DCKRBQ7C.74145.09H
E61 BR32K L50610-B6252-D670 ICLOGISN74AVC1T45DCKRBQ7C.74145.09H
E61 BRRSTO L50610-B6252-D670 ICLOGISN74AVC1T45DCKRBQ7C.74145.09H
E61 AMP L50610-C6390-D670 ICANATPA2010D1YZFRBQ7D.02010.0K0
E61 U1 L50610-C6392-D670 ICANANUF2221W1T2GBQ7D.02221.07Y
E61 BLDRV L50610-C6288-D670 ICDCCONLM3501TLXBQ7D.03501.040
E61 LDO2CH L50610-C6423-D670 ICVRR5325K005B-TRBQ7D.05325.030
E61 U64 L50610-U6248-D670 ICSWITCHPLELMSP54CA-272BQ7D.054CA.D30
E61 PMIC L50610-C6394-D670 ICANABH6053GUBQ7D.06053.04U
E61 CHRIC L50610-C6395-D670 ICANAISL6292CCR3ZBQ7D.06292.070
E61 CODEC L50610-U6276-D670 ICAUDIOWM8955LSEFL/RBQ7D.08955.075
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E61 U70 L50610-C6289-D670 ICANAVRMAS9124A2GC06BQ7D.09124.03B
E61 VD1 L50610-C6424-D670 ICDETECTORXC61GN2302HRNBQ7D.12302.0B0
E61 U65 L50610-U6244-D670 ICIRXCVRHD155165BPEBBQ7D.15516.0FU
E61 U69 L50610-C6425-D670 ICPWRAMPSKY77328BQ7D.77328.0K0
E61 U62 L50610-B6218-D670 ICLOGIBUFFERNC7WZ16BQ7D.7WZ16.0MY
E61 O48M L50645-G200-Y28 OSC48MHZ30PF50PPMBQ8B.24800.301
E61 U61 L50645-F102-Y48 OSCCRYST26MHZU-860-1-1BQ8B.30026.D02
E61 C30M L50645-F102-Y64 OSCCRYST30MHZ30MHZ8PFBQ8B.33000.B02
E61 C32K L50645-F102-Y49 OSCCRYST32.768DST520BQ8B.33276.705
3 Required Equipment for Level 3
GSM-Tester
PC-incl. Monitor, Keyboard and Mouse
USB boot cable with USB foxlink driver (F30032-P601-A1)
Troubleshooting Frame E61
Power Supply
Spectrum Analyser
Active RF-Probe incl. Power Supply
Oscilloscope incl. Probe
RF-Connector (N<>SMA(f))
Power Supply Cables
Dongle
BGA Soldering equipment
4 Required Software for Level 3
Windows XP
XCSD Tools Level 3
GRT Version 4 or higher
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5 Radio Part
5.1 Receiver Operation
IRxP
IRxN
QRxP
QRxN
RX GSM: 925~960 MHz
T/R
Switch
1805~1880 MHz
1930~1990 MHz
DCS:
PCS:
GSM LNA
0
90
DCS LNA
0
90
PCS LNA
RFVCO
PCS:3860~3980 MHz
DCS:3610~3760 MHz
GSM:3700~3840 MHz
0
90
Shift(1/2)
0
90
Shift(1/2)
2
GSM:
1850~1920 MHz
DCS:
1805~1880 MHz
PCS:
1930~1990 MHz
RF
Synth
ADC/DAC & Control Logic for DC Offset Cancellation
HD155165BP (B6E)
The Receiver structure in HD155165BP is a zero-IF solution. That means RF signal is directly downconverted to the baseband signal. And by the way, all of the DC-offset canceling processes
are done within chip. We do not have to care about that.
The LNA amplifies the RF signal after passing the T/R switch and RF SAW filter and before it enters
the down-converter section. The RF signal is mixed with a local oscillator (LO) signal to generate the
baseband signal.
Three LPFs are used in the baseband signal processing for reducing blocking signals. The first LPF
employs two external capacitors, and we can check whether the front-end (LNA + Mixer) is
functionally well or not by probing these two capacitors to see if there is any baseband
signal(<200kHz).
After three stages of DC-offset cancelling, the signal (I+/I-/Q+/Q-) then output to the baseband IC for
further processing.
The HD155165BP receiver is based upon the HD155155NP direct conversion design. As
HD155165BP supports quad band, the front end incorporates four LNAs and mixers. The incoming
RF signals are mixed directly down to I/Q base-band by the front-end block. This incorporates four
LNAs / four buffers and Gilbert Cell mixer blocks optimized for operation at 850MHz, 900MHz,
1800MHz, and 1900MHz respectively.
The front-end block is followed by two closely matched base-band amplifier chains. These include
distributed low pass filter, three switched gain stages and one fixed gain stage.
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In addition, the base-band section integrates A/D and D/A converters which provide automatic onchip correction of DC offsets. The three switched gain stages in each channel are DC coupled and
provide 90dB gain control range with 2dB step size. The first PGA has a voltage gain range (x8-x1)
with 6dB steps. The second PGA has a gain range (x8-x0.125) with 2dB steps. The third PGA has a
gain range (x8-x0.125) with 2dB steps. The final fixed gain amplifier provides a gain of x3 or x6. The
gain is set to match the on-chip levels to the input dynamic range of the base-band. The base-band
filtering in each channel comprises a single RC low pass filter at the input of the first switched gain
stage and three 2nd order Butterworth filters, one at the input of each of the other switched gain
stages. The R/C filter requires an off-chip capacitor for each channel. The Butterworth filters are fully
integrated on-chip.
The base-band PGA includes a DC offset cancellation system. The auto calibration system uses a
successive approximation technique and requires around 20us to perform a three stages calibration.
The system calibrates out the offsets arising in both I and Q receives channels.
5.2 Transmitter Operation
PCS:3860~3980 MHz
DCS:3580~3730 MHz
RFVCO
GSM:3840~3980 MHz
2
2
GSM
GSM: 960~995 MHz
RF
DCS/
PCS
PCS:1930~1990 MHz
DCS:1790~1865 MHz
Synth
IF
Synth
IFVCO
640/656 MHz
2
2
0
T/R
Switch
Quad-Band PA
TX GSM: 880~ 915 MHz
DCS:1710~1785 MHz
PCS:1850~1910 MHz
Loop Filter
Charge
Pump
Shift(1/2)
PFD
80/82 MHz
90
I&Q Mod
ITxP
ITxN
QTxP
QTxN
HD155165BP (B6E)
The B6E generates a modulated signal at IF with a quadrature modulator and converts it to final
frequency with an Offset Phase Locked Loop (OPLL).
The Offset Phase Locked Loop is simply a PLL with a down conversion mixer in the feedback path.
Using a down converter in the feedback path acts as an up-converter in the forward path. This
allows the output frequency to be different from the comparison frequency without affecting the
normal operation of the loop. Phase/frequency changes in the reference signal are not scaled, as
they would be if a divider were used in the feedback path, hence the modulation is faithfully
reproduced at the final frequency.
The main advantage of the OPLL in this application is that it forms a tracking band pass filter around
the modulated signal. This is because the loop cannot respond to phase variations at the reference
that are outside its closed loop bandwidth. Thus the broad band phase noise from the quadrature
modulator is shaped by the frequency response of the closed loop allowing the TX noise
specification to be met without further filtering.
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A secondary advantage of the OPLL is that the output signal, coming from a VCO, is truly constant
envelope. This removes the problem of spectral spreading caused by AM to AM and AM to PM
conversion in the power amplifier.
The OPLL is formed from an on chip Gilbert cell down converter, limiter and phase detector with on
chip passive loop filter. The phase detector is implemented as a Gilvert cell with current source
output stage. The current output allows an integrator to be included in the passive loop filter. This is
similar to the technique commonly used in PLL synthesizers. A digital phase detector is used to
speed OPLL locking. After locking, the digital phase detector is switched off and the analogue phase
detector becomes active.
5.3 VCXO Operation
+R
HD155165BP provides a DCXO function. With that function, we can build a reference clock
generation circuits as shown in the above graph. This means that the VCTCXO module is not
necessary for clock application, and only one crystal with 8ppm tolerance and one varactor are
enough.
The transistor in HD155165BP and two internal capacitors (C1, C2) provide a negative resistance,
and the crystal (X1) combined with some other passive components to provide a positive resistance.
When these two resistance values equal to each other at some frequency, the oscillation will happen
at that frequency. In our design target, the oscillation frequency should be within 26MHz +/-15 ppm
at least.
-R
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6 Logic (Base-Band)
Introduction:
E61 utilizes TI’s chipsets (CALYPSO and IOTA) and RENESAS’s chipset (SHJ2SLSL) as baseband solution. Base-band is composed with three potions: Logic, Analog/Codec and MMP.
CALYPSO is a GSM/GPRS digital base-band logic solution included microprocessor, DSP, and
peripherals. IOTA is a combination of analog/codec solution and power management which contain
base-band codec, voice-band codec, several voltage regulators and SIM level shifter etc.
SHJ2SLSL is a multimedia solution included microprocessor, DSP, internal memory, and interrupt
controller. In addition, HerB1A integrates with other features such as LED backlight, TFT-LCD
display, CMOS DSC module, Mini-SD card, vibration, SW-midi, MP3 and charging etc. The following
sections will present the operation theory with circuitry and descriptions respectively.
Block Diagram CPU CALYPSO (HERCROM400)
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