Siemens CPU 412-2, CPU 414-2, CPU 412, CPU 414-3, CPU 414 Instruction Manual

S7-400 Instruction List CPU 412, 414, 416, 417

This Instruction List has the order number:

6ES7498-8AA04-8BN0

Edition 04/2004

A5E00267845-01

The reproduction, transmission or use of this document or its contents is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created b y patent grant or registration of a utility model or design, are reserved.

Siemens AG Bereich Automation and Drives Geschaeftsgebiet Industrial Automation Systems Postfach 4848, D- 90327 Nuernberg

Siemens Aktiengesellschaft 6ES7498-8AA04-8BN0

We have checked the contents of this manual for agreement with the hardware and software described. Since deviations cannot be precluded entirely, we cannot guarantee full agreement. However, the data in this manual are reviewed regularly and any necessary corrections included in subsequent editions. Suggestions for improvement are welcomed.

 Siemens AG 2004 Subject to change without prior notice

Applicability

CPU 412

CPU 414

CPU 416 CPU 417

This list of instructions applies to the CPUs listed below.

Name Order number subsequently described as*

CPU 412-1 6ES7412-1XF04-0AB0 CPU 412-2 6ES7412-2XG04-0AB0 CPU 414-2 6ES7414-2XG04-0AB0 CPU 414-3 6ES7414-3XJ04-0AB0 CPU 414-4H 6ES7414-4HJ04-0AB0 CPU 416-2 6ES7416-2XK04-0AB0 CPU 416F-2 6ES7416-2FK04-0AB0 CPU 416-3 6ES7416-3XL04-0AB0 CPU 417-4 6ES7417-4XL04-0AB0 CPU 417-4 H 6ES7417-4HL04-0AB0

* except in the tables, where a detailled differentiation is necessary

Applicability

CPU 414

CPU 416

S7-400 Instruction List A5E00267845-01

5

Address Identifier and Parameter Ranges

Description

Address Identifier and Parameter Ranges

Addr. Parameter Range Description

ID CPU 412 CPU 414 CPU 416 CPU 417

**

Q

**

QB

**

QW

**

QD DBX 0.0 to 65533.7* 0.0 to 65533.7 0.0 to 65533.7 0.0 to 65533.7 Data bit in data block DB 1 to 511 1 to 4095 1 to 4095 1 to 8191 Data block DBB 0 to 65533* 0 to 65533 0 to 65533 0 to 65533 Data byte in DB DBW 0 to 65532* 0 to 65532 0 to 65532 0 to 65532 Data word in DB DBD 0 to 65530* 0 to 65530 0 to 65530 0 to 65530 Data double word in DB DIX 0.0 to 65533.7* 0.0 to 65533.7 0.0 to 65533.7 0.0 to 65533.7 Data bit in instance DB DI 1 to 511 1 to 4095 1 to 4095 1 to 8191 Instance data block DIB 0 to 65533* 0 to 65533 0 to 65533 0 to 65533 Data byte in instance DB

DIW DID 0 to 65530* 0 to 65530 0 to 65530 0 to 65530 Data double word instance DB

* Also restricted by the size of the working memory. ** Default setting can be changed, see Technical Specifications

0.0 to 127.7 0.0 to 255.7 0.0 to 511.7 0.0 to 1023.7 Output (in PIQ) 0 to 127 0 to 255 0 to 511 0 to 1023 Output byte (in PIQ) 0 to 126 0 to 254 0 to 510 0 to 1022 Output word (in PIQ) 0 to 124 0 to 252 0 to 508 0 to 1020 Output double word (in PIQ)

0 to 65532* 0 to 65532 0 to 65532 0 to 65532 Data word in instance DB

S7-400 Instruction List A5E00267845-01

6

Address Identifier and Parameter Ranges

Description

Address Identifier and Parameter Ranges, continued

Addr. Parameter Range Description

ID CPU 412 CPU 414 CPU 416 CPU 417

I** 0.0 to 127.7 0.0 to 255.7 0.0 to 511.7 0.0 to 1023.7 Input bit (in PII) IB** 0 to 127 0 to 255 0 to 511 0 to 1023 Input byte (in PII) IW** 0 to 126 0 to 254 0 to 510 0 to 1022 Input word (in PII) ID** 0 to 124 0 to 252 0 to 508 0 to 1020 Input double word (in PII) L** 0.0 to 4095.7 0.0 to 8191.7 0.0 to 16383.7 0.0 to 32767.7 Local data LB** 0 to 4095 0 to 8191 0 to 16383 0 to 32767 Local data byte LW** 0 to 4094 0 to

8190 LD** 0 to 4092 0 to 8188 0 to 16380 0 to 32764 Local data double word M 0.0 to 4095.7 0.0 to 8191.7 0.0 to 16383.7 0.0 to 16383.7 Bit memory MB 0 to 4095 0 to 8191 0 to 16383 0 to 16383 memory byte MW 0 to 4094 0 to 8190 0 to 16382 0 to 16382 memory word MD 0 to 4092 0 to 8188 0 to 16380 0 to 16380 memory double word

** Default setting can be changed, see Technical Specifications

0 to 16382 0 to 32766 Local data word

S7-400 Instruction List A5E00267845-01

7

Address Identifier and Parameter Ranges

Description

Address Identifier and Parameter Ranges, continued

Addr. Parameter Range Description

ID CPU 412 CPU 414 CPU 416 CPU 417

PQB 0 to 4095 0 to 8191 0 to 16383 0 to 16383 Peripheral output byte

PQW 0 to 4094 0 to 8190 0 to 16382 0 to 16382 Peripheral output word

PQD 0 to 4092 0 to 8188 0 to 16380 0 to 16380 Peripheral output double word

PIB 0 to 4095 0 to 8191 0 to 16383 0 to 16383 Peripheral input byte

PIW 0 to 4094 0 to 8190 0 to 16382 0 to 16382 Peripheral input word

PID 0 to 4092 0 to 8188 0 to 16380 0 to 16380 Peripheral output double word

T 0 to 2047 0 to 2047 0 to 2047 0 to 2047 Timer C 0 to 2047 0 to 2047 0 to 2047 0 to 2047 Counter

(direct I/O access)

S7-400 Instruction List A5E00267845-01

8

Constants and Ranges

Constant Range Description

B(b1,b2) B(b1,b2,b3,b4)

D# Date – IEC date constant L# Integer – 32-bit integer constant P# Bit pointer – Pointer constant S5T# Time value – S7 time constant T# TIme value TOD# Time value – IEC time constant C# Count value – Counter constant (BCD code) 2#n – Binary constant W#16#

DW#16#

1)

For loading of S7 timers.

– Constant, 2 or 4 bytes

1)

–

– Hexadecimal constant

Time constant

Constants and Ranges

S7-400 Instruction List A5E00267845-01

9

Abbreviations and Mnemonics

The following abbreviations and mnemonics are used in the Instruction List:

Abbrev. Description Example

k8 8-bit constant

0 to 255

Abbreviations and Mnemonics

32

k16 16-bit constant

k32 32-bit constant

i8 8-bit integer

i16 16-bit integer

i32 32-bit integer

m Pointer constant P#240.3 n Binary constant 1001 1100 p Hexadecimal constant EA12 Label Symbolic jump address (max. 4 characters) DESTINATION a Byte address

S7-400 Instruction List A5E00267845-01

256 to 32 767

28 131

127 624

32 768 to 999 999 999

-113

-128 to +127 +6523

-32768 to +32767

-2 222 222

-2 147 483 648 to +2 147 483 647

10

Abbreviations and Mnemonics, continued

Abbrev. Description Example

b Bit address c Address area I, Q, M, L, DBX, DIX d Address in: MD, DBD, DID or LD e Number in: MW, DBW, DIW or L W f Timer/counter No.

Abbreviations and Mnemonics

g Address area IB, QB, PIB, PQB, MB, LB,

h Address area IW, QW, PIW, PQW, MW,

i Address area ID, QD, PID, PQD, MD, LD,

q Block No.

S7-400 Instruction List A5E00267845-01

DBB, DIB

LW, DBW, DIW

DBD, DID

11

Registers

ACCU1 to ACCU4 (32 Bits)

The accumulators are registers for processing bytes, words or double words. The address identifiers are loaded into the accumulators, where they are logically gated. The result of the logic operation (RLO) is in ACCU1 and can be transferred from there to a memory cell.

The accumulators are 32 bits long.

Accumulator designations :

ACCU Bits

ACCUx (x = 1 to 4) Bit 0 to 31 ACCUx-L Bit 0 to 15 ACCUx-H Bit 16 to 31 ACCUx-LL Bit 0 to 7 ACCUx-LH Bit 8 to 15 ACCUx-HL Bit 16 to 23 ACCUx-HH Bit 24 to 31

S7-400 Instruction List A5E00267845-01

12

Registers

Address Registers AR1 and AR2 (32 Bits)

The address registers contain the area-internal or area-crossing pointers for instructions using indirect addressing. The address registers are 32 bits long.

The area-internal and/or area-crossing pointers have the following syntax:

• Area-internal pointer 00000000 00000bbb bbbbbbbb bbbbbxxx

• Area-crossing pointer yyyyyyyy 00000bbb bbbbbbbb bbbbbxxx

Legend: b Byte address

x Bit number

y Area identifier

(see “Examples of Addressing”)

S7-400 Instruction List A5E00267845-01

13

Status Word (16 Bits)

The status word bits are evaluated or set by the instructions. The status word is 16 bits long.

Bit Assignment Description

0 FC First check bit 1 RLO Result of logic operation 2 STA Status 3 OR Or (AND before OR) 4 OS Stored overflow 5 OV Overflow 6 CC 0 Condition code 0 7 CC 1 Condition code 1 8 BR Binary result

9 to 15 Unassigned –

Registers

S7-400 Instruction List A5E00267845-01

14

Examples of Addressing

Addressing Examples Description

Immediate Addressing L +27 Load 16-bit integer constant “27” into ACCU1 L L#-1 Load 32-bit integer constant “-1” into ACCU1 L 2#1010101010101010 Load binary constant into ACCU1 L DW#16#A0F0BCFD Load hexadecimal constant into ACCU1 L ’ENDE’ Load ASCII character into ACCU1 L T#500 ms Load time value into ACCU1 L C#100 Load count value into ACCU1 L B#(100,12) Load 2-byte constant L B#(100,12,50,8) Load 4-byte constant L P#10.0 Load area-internal pointer into ACCU1 L P#E20.6 Load area-crossing pointer into ACCU1 L -2.5 Load real number into ACCU1 L D# 1995-01-20 Load date L TOD 13:20:33.125 Load time of day

Examples of Addressing

S7-400 Instruction List A5E00267845-01

15

Examples of Addressing

Addressing Examples Description

Direct Addressing A I 0.0 ANDing of input bit 0.0 L IB 1 Load input byte 1 into ACCU1 L IW 0 Load input word 0 into ACCU1 L ID 0 Load input double word 0 into ACCU1 Indirect Addressing of Timers/Counters SP T [LW 8] Start timer; the timer number is in local data word 8 CU C [LW 10 ] Count upwards; the counter number is in local data word 10 Area-Internal Memory-Indirect Addressing A I [LD 12]

Example: L P#22.2

T LD 12

A I [LD 12] A I [DBD 1] AND operation: The address of the input is in data double word 1 of the open DB as pointer A I [DID 12] AND operation: The address of the output is in data double word 12 of the open instance DB as pointer A I [MD 12] AND operation: The address of the output is in memory double word 12 as pointer

AND operation: The address of the input is in local data double word 12 as pointer

S7-400 Instruction List A5E00267845-01

16

Examples of Addressing

Examples of Addressing, continued

Addressing Examples

Area-Internal Register-Indirect Addressing A I [AR1,P#12.2] Area-Crossing Register-Indirect Addressing For area-crossing register-indirect addressing, the address must also contain an area identifier. The address is in the address register.

The area identifiers are as follows:

Area Coding Area identifier (binary) hex.

P 1000 0000 80 I/O area I 1000 0001 81 Input area Q 1000 0010 82 Output area M 1000 0011 83 Bit memory area DB 1000 0100 84 Data area DI 1000 0101 85 Instance data area L 1000 0110 86 Local data area VL 1000 0111 87 Predecessor local data area (access to local data of invoking block)

L B [AR1,P#8.0] A [AR1,P#32.3] Addressing Via Parameters A Parameter

S7-400 Instruction List A5E00267845-01

17

Examples of how to calculate the pointer

• Example for sum of bit addresses x7: LAR1 P#8.2

A I [AR1,P#10.2]

Result: Input 18.4 is addressed (by adding the byte and bit addresses)

• Example for sum of bit addressesu7:

L P#10.5 LAR1 A I [AR1,P#10.7]

Result: Input 21.4 is addressed (by adding the byte and bit addresses with carry over)

S7-400 Instruction List A5E00267845-01

18

Execution Times with Indirect Addressing1

When using indirect addresses statement consists of two parts:

Part 1: Load the address of the instruction Part 2: Execute the instruction

In other words, when working with indirect addresses, you must calculate the execution time of an instruction from these two parts.

Calculating the Execution Time

The total execution time is calculated as follows: + execution time of the instruction

= Total execution time of the instruction

The execution times listed in the chapter entitled “List of Instructions” apply to the execution times of the second part of an instruction, i.e. for the actual execution of an instruction.

Y ou must then add the time required for loading the address of the instruction to this execution time (see following Table).

S7-400 Instruction List A5E00267845-01

Time required for loading the address

19

Execution Times with Indirect Addressing1

The execution time for loading the address of the instruction from the various areas is shown in the following table.

Address is in ... Execution Time in s

CPU 412 CPU 414 CPU 416 CPU 417

Bit memory area M

Data block DB/DX

Local data area L

AR1/AR2 (area-internal) 0.0 * 0.0 * 0.0 * 0.0 * AR1/AR2 (area-crossing) 0.0 * 0.0 * 0.0 * 0.0 * Parameter (word) ... for:

S Timers S Counters

Word Double word

0.2

0.3

0.2

0.4

0.12

0.18

0.12

0.24

0.08

0.12

0.08

0.16

S Block calls

Parameter (double word) ... for

Bits, bytes, words and double words

0.4 0.24 0.16 0.15

0.06

0.12

0.06

0.15

* Address registers AR1/AR2 do not need to be loaded in separate cycles for addressing.

The pages that follow contain examples for calculating the instruction run time for the various indirectly addressed instructions.

S7-400 Instruction List A5E00267845-01

20

Examples of Calculations

Y ou will find a few examples here for calculating the execution times for the various methods of indirect addressing.

Calculating the Execution Times for Area-Internal Memory-Indirect Addressing

Example: A I [DBD 12] with CPU 414 Step 1: Load the contents of DBD 12 (time required is listed in the table on page 20)

Address is in ... Execution Time in s

Bit memory area M

Data block DB/DX

Step 2: AND the input addressed in this way (you will find the execution time in the tables in the chapter entitled “List of Instruc-

tions” on page 25)

Total execution time:

+ 0.06 s

0.18 s

0.24 s

Word Double word

Direct Addressing Indirect Addressing

0.06/0.075 :

Typical Execution T ime in s

Time for A I

0.2

0.3

0.2

0.3

0.06+ :

S7-400 Instruction List A5E00267845-01

21

Examples of Calculations

Execution Time for Area-Crossing Register-Indirect Addressing

Example: A [AR1, P#23.1] ... with I 1.0 in AR1 with CPU 416 Step 1: Load the contents of AR1, and increment them by the offset 23.1 (the time required is in the table on page 20)

Address is in ... Execution Time in s

: :

AR1/AR2 (area-crossing) 0.00

: :

Step 2: AND link of the input addressed this way (see page 25 for the execution time)

Typical Execution T ime in s

Direct Addressing Indirect Addressing

Total execution time:

0.00 s

+ 0.05 s

0.05 s

0.04/0.05 :

Time for A I

0.05+ :

S7-400 Instruction List A5E00267845-01

22

Execution Time for Addressing Via Parameters

Example A Parameter ... with I 0.5 in the block parameter list with CPU 414 Step 1: Load input I 0.5 addressed via the parameter (the time required is in the table on page 20)

Address is in ... Execution Time in s

: : :

Parameter (double word) 0.24

Step 2: AND link of the input addressed this way (see page 25 for the execution time)

Direct Addressing Indirect Addressing

:

Typical Execution T ime in s

Examples of Calculations

Total execution time

0.24 s

+ 0.05 s

0.315 s

S7-400 Instruction List A5E00267845-01

0.06/0.075 :

Time for A I

0.075+ :

23

List of Instructions

This chapter contains the complete list of instructions for the S7-400 CPUs. The descriptions have been kept as concise as possible. You will find a detailed functional description in the various STEP 7 reference manuals. Please note that, in the case of indirect addressing (examples see page LEERER MERKER), you must add the time required for loading the address of the particular instruction to the execution times listed (see page 20).

S7-400 Instruction List A5E00267845-01

24

Bit Logic Instructions

Instr.

Length

Execution Time in s

Instr.

Address

Length

Bit Logic Instructions

All logic instructions generate a result (new RLO). The first instruction in a logic string generates the new RLO from the signal state scanned. The subsequent logic instructions generate the new RLO from the signal state scanned and the old RLO. The logic string ends with an instruction which limits the RLO (e.g. a memory instruction); that is, the /FC bit is set to zero.

ID

U/UN

Statusword for: U/UN BIE A1 A0 OV OS OR STA RLO /FC Instruction depends on: – – – – – Yes – Yes Yes Instruction affects: – – – – – Yes Yes Yes 1

+ Plus time required for loading the address of the instruction (see page 20)

*)

**)With direct instruction addressing;Address area 0 to 255 ***)I,Q,M,L / DB, DI

S7-400 Instruction List A5E00267845-01

I/Q a.b M a.b L a.b DBX a.b DIX a.b c [d] c [AR1,m] c [AR2,m] [AR1,m] [AR2,m] Parameter

With direct instruction addressing;Address area 0 to 127

Input/output Bit memory Local data bit Data bit Instance data bit Memory-indirect, area-internal*** Register-ind., area-internal (AR1)*** Register-ind., area-internal (AR2)*** Area-crossing (AR1)*** Area-crossing (AR2)*** Via parameter ***

Description

in

Words

1*/2

1**/2

2 2 2 2 2 2 2 2 2

CPU 412 CPU 414 CPU 416 CPU 417

0.1/0.125

0.125

0.2

0.1+/0.2+

0.125+/0.2+

0.06/0.075

0.075

0.12

0.06+/0.12+

0.075+/0.12+

0.04/0.05

0.05

0.08

0.04+/0.08+

0.05+/0.08+

0.03/0.042

0.042

0.09

0.03+/0.09+

0.042+/0.09+

25

Bit Logic Instructions, continued

Bit Logic Instructions

Instr.

O/ON

Statusword for: O, ON BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – Yes Yes Instruction affects: – – – – – 0 Yes Yes 1

+ Plus time required for loading the address of the instruction (see page 20)

*)

**)With direct instruction addressing; Address area 0 to 255 ***)I,Q,M,L / DB, DI

S7-400 Instruction List A5E00267845-01

Address

ID

I/Q a.b M a.b L a.b DBX a.b DIX a.b c [d] c [AR1,m] c [AR2,m] [AR1,m] [AR2,m] Parameter

With direct instruction addressing; Address area 0 to 127

OR/OR-NOT Input/output Bit memory Local da Data bit Instance data bit Memory-indirect, area-internal *** Register-ind., area-internal (AR1) *** Register-ind., area-internal (AR2) *** Area-crossing (AR1) *** Area-crossing (AR2) *** Via parameter ***

Description

Length

in

Words

1*/2

1**/2

2 2 2 2 2 2 2 2 2

CPU 412 CPU 414 CPU 416 CPU 417

0.1/0.125

0.125

0.2

0.1+/0.2+

0.125+/0.2+

0.06/0.075

0.075

0.12

0.06+/0.12+

0.075+/0.12+

0.04/0.05

0.05

0.08

0.04+/0.08+

0.05+/0.08+

0.03/0.042

0.042

0.09

0.03+/0.09+

0.042+/0.09+

26

Bit Logic Instructions, continued

Address-

Instr.

Address-

Description

Lengt

Execution Time in s

h in

Words

Bit Logic Instructions

Instr.

ID

Lengt

h in

CPU 412 CPU 414 CPU 416 CPU 417

X/XN

EXKLUSIV-OR/

EXKLUSIV-OR-NOT E/A a.b M a.b L a.b DBX a.b DIX a.b c [d] c [AR1,m] c [AR2,m] [AR1,m] [AR2,m] Parameter

Input/output

Bit memory

Local data bit

Data bit

Instance data bit

Memory-indirect, area-internal.

*)

Register-ind., area-internal (AR1)

Register-ind., area-internal (AR2)

Area-crossing (AR1)

Area-crossing (AR2)

Via parameter

*) *)

*)

2 2 2 2 2 2

*)

2

*)

2 2 2 2

0.125

0.2

0.1+/0.2+

0.125+/0.2+

0.075

0.12

0.06+/0.12+

0.075+/0.12+

0.05

0.08

0.04+/0.08+

0.05+/0.08+

0.03+/0.09+

0.042+/0.09+

Status word for: X, XN BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – Yes Yes Instruction affects: – – – – – 0 Yes Yes 1

+Plus time required for loading the address of the instruction (see page 20)

*)

I,Q,M,L / DB, DI

S7-400 Instruction List A5E00267845-01

0.042

0.09

27

Bit Logic Instructions with Parenthetical Expressions

struc-

in

Bit Logic Instructions with Parenthetical Expressions

Saving the RLO and OR bits and the relevant function identifier (A, AN, ...) to the nesting stack. Seven nesting levels are possible per block. After the right parenthesis, the logic operation indicated by the function identifier is performed on the saved RLO and the current RLO; the current OR is overwritten with the saved OR.

In-

tion

U( AND left parenthesis 1 0.1 0.06 0.04 0.03 UN( AND NOT left parenthesis 1 0.1 0.06 0.04 0.03 O( OR left parenthesis 1 0.1 0.06 0.04 0.03 ON( OR NOT left parenthesis 1 0.1 0.06 0.04 0.03 X( Exclusive OR left parenthesis 1 0.1 0.06 0.04 0.03 XN( EXKLUSIV-ODER-NICHT-Klam-

Statusword for: U(, UN(, O(, ON(, X(,

Instruction evaluates: – – – – – Yes – Yes Yes Instruction affects: – – – – – 0 1 – 0

S7-400 Instruction List A5E00267845-01

Address

ID

parenthesis

XN(

Description

Length

Words

1 0.1 0.06 0.04 0.03

BR CC1 CC0 OV OS OR STA RLO /FC

CPU 412 CPU 414 CPU 416 CPU 417

Execution Time in s

28

Bit Logic Instructions with Parenthetical Expressions

struc-

in

Bit Logic Instructions with Parenthetical Expressions, continued

In-

tion

) Right parenthesis, removing an

Statusword for: ) BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – Yes – Instruction affects: – – – – – Yes 1 Yes 1

Address

ID

Description

entry from the nesting stack.

Length

Words

1 0.1 0.06 0.04 0.03

CPU 412 CPU 414 CPU 416 CPU 417

Execution Time in s

S7-400 Instruction List A5E00267845-01

29

ORing of AND Instructions

in

The ORing of AND instructions is implemented according to the rule: AND before OR.

ORing of AND Instructions

In-

struc-

tion

O ORing of AND operations

Status word for: O BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – Yes Yes Instruction affects: – – – – – Yes 1 – Yes

S7-400 Instruction List A5E00267845-01

Address

ID

Description

according to the rule: AND before

OR

Length

Words

1 0.1 0.06 0.04 0.03

CPU 412 CPU 414 CPU 416 CPU 417

Execution Time in s

30

Logic Instructions with Timers and Counters

Execution Time in s

In-

in

Execution Time in s

Logic Instructions with Timers and Counters

Examining the status of the addressed timer/counter and gating the result with the RLO according to the appropriate logic function.

In-

struc-

tion

A/AN

Status word for: A, AN BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – Yes – Yes Yes Instruction affects: – – – – – Yes Yes Yes 1

+ Plus time required for loading the address of the instruction (see page 20) *)With direct instruction addressing ;Address area 0 to 255

Address ID Description

Tf T [e] Cf C [e]

Timerpara. Counter para.

AND/AND NOT Timer Timer, memory-indirect addressing Counter Counter, memory-indirect addressing

Timer/counter (addressing via parameter)

Length

in

Words

1*/2

2

1*/2

2 2 0.1+

CPU 412 CPU 414 CPU 416 CPU 417

0.1/0.125

0.1+

0.1/0.125

0.1+

0.06/0.075

0.06+

0.06/0.075

0.06+

0.04/0.05

0.04+

0.04/0.05

0.04+

0.03/0.042

0.03+

0.03/0.042

0.03+

S7-400 Instruction List A5E00267845-01

31

Logic Instructions with Timers and Counters

Execution Time in s

In-

in

Execution Time in s

Logic Instructions with Timers and Counters, continued

In-

struc-

tion

O/ON

X/XN

Status word for: O, ON, X, XN BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – Yes Yes Instruction affects: – – – – – 0 Yes Yes 1

+ Plus time required for loading the address of the instruction (see page 20) *)With direct instruction addressing; address area 0 to 255

S7-400 Instruction List A5E00267845-01

Address ID Description

Tf T [e] Cf C [e]

Timerpara. Counterpara.

Tf T [e] Cf C [e]

Timerpara. Counterpara.

Timer Timer, memory-indirect addr. Counter Counter, memory-indirect addressing

Timer/counter (addressing via parameter)

EXCLUSIVE OR/EXCLUSIVE OR NOT Timer Timer, memory-indirect addr. Counter Counter, mem.-indirect addr .

EXCLUSIVE OR timer/counter (addressing via parameter)

Length

in

Words

1*/2

2

1*/2

2 2 0.1+

2 2 2 2

2 0.1+

CPU 412 CPU 414 CPU 416 CPU 417

0.1/0.125

0.1+

0.1/0.125

0.1+

0.125

0.1+

0.125

0.1+

0.06/0.075

0.06+

0.06/0.075

0.06+

0.075

0.06+

0.075

0.06+

0.04/0.05

0.04+

0.04/0.05

0.04+

0.05

0.04+

0.05

0.04+

0.03/0.042

0.03+

0.03/0.042

0.03+

0.042

0.03+

0.042

0.03+

32

Word Logic Instructions with the Contents of Accumulator 1

Address

struc-

Address

Description

Length

in

Words

Word Logic Instructions with the Contents of Accumulator 1

Gating the contents of ACCU1 and/or ACCU1-L with a word or double word according to the appropriate function. The word or double word is either specified in the instruction as an address or is in ACCU2. The result is in ACCU1 and/or ACCU1-L.

In-

tion

AW AND ACCU2-L 1 0.1 0.06 0.04 0.03 AW W#16#p AND 16-bit constant 2 0.125 0.075 0.05 0.042 OW OR ACCU2-L 1 0.1 0.06 0.04 0.03 OW W#16#p OR 16-bit constant 2 0.125 0.075 0.05 0.042 XOW EXCLUSIVE OR ACCU2-L 1 0.1 0.06 0.04 0.03 XOW W#16#p EXKLUSIV-ODER EXCLUSIVE

Status word for: UW, OW, XOW BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – – – Instruction affects: – ja 0 0 – – – – –

S7-400 Instruction List A5E00267845-01

ID

OR 16-bit constant

Length

CPU 412 CPU 414 CPU 416 CPU 417

2 0.125 0.075 0.05 0.042

Execution Time in s

33

Word Logic Instructions with the Contents of Accumulator 1

Instruc-

Address

Instruc-

Address

Description

Length

in

Words

Word Logic Instructions with the Contents of Accumulator 1, continued

Length

tion

AD AND ACCU2 1 0.1 0.6 0.04 0.3 AD DW#16#p AND 32-bit constant 3 0.185 0.112 0.075 0.062 OD OR ACCU2 1 0.1 0.06 0.04 0.3 OD DW#16#p OR 32-bit constant 3 0.185 0.112 0.075 0.062 XOD EXCLUSIVE OR ACCU2 1 0.1 0.06 0.04 0.03 XOD DW#16#p EXCLUSIVE OR 32-bit constant 3 0.185 0.112 0.075 0.062 Status word for: UD, OD, XOD BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – – – Instruction affects: – Yes 0 0 – – – – –

ID

CPU 412 CPU 414 CPU 416 CPU 417

Execution Time in s

S7-400 Instruction List A5E00267845-01

34

Evaluating Conditions Using AND, OR and EXCLUSIVE OR

Instruc-

Address

Instruc-

Address

Description

Length

in

Words

Evaluating Conditions Using AND, OR and EXCLUSIVE OR

All logic instructions generate a result (new RLO). The first instruction in a logic string generates the new RLO from the signal state scanned. The subsequent logic instructions generate the new RL from the signal state scanned and the old RLO. The logic string ends with an instruction which limits the RLO (e.g. a memory instruction); that is, the FC bit is set to zero.

Length

tion

A/AN O/ON X/XN

Status word for: A/AN/O/ON/X/XN BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – Yes Yes – – Yes – Yes Yes Instruction affects: – – – – – Yes Yes Yes 1

S7-400 Instruction List A5E00267845-01

ID

AND/AND NOT OR/OR-NOT EXCLUSIVE OR/ EXCLUSIVE-OR-NOT

==0 >0 Result>0

<0 Result<0

<>0

Result=0 (A1=0 and A0=0) 1 0.1 0.06 0.04 0.03

(CC1=1 and CC0=0)

(CC1=0 and CC0=1) Result00

((CC1=0 and CC0=1) or (CC1=1 and CC0=0))

CPU 412 CPU 414 CPU 416 CPU 417

1 0.1 0.06 0.04 0.03

Execution Time in s

35

Evaluating Conditions Using AND, OR and EXCLUSIVE OR

Instruc-

Address

Instruc-

Address

Description

Length

in

Words

Evaluating Conditions Using AND, OR and EXCLUSIVE OR, continued

Length

tion

A/AN O/ON X/XN

Status word for: A/AN/O/ON/X/XN BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – Yes Yes – – Yes – Yes Yes Instruction affects: – – – – – Yes Yes Yes 1

ID

>=0 Result>=0

((CC1=1 and CC0=0) or (CC1=0 and CC0=0))

<=0 Result<=0

((CC1=0 and CC0=1) or (CC1=0 and CC0=0))

CPU 412 CPU 414 CPU 416 CPU 417

1 0.1 0.06 0.04 0.03

Execution Time in s

S7-400 Instruction List A5E00267845-01

36

Evaluating Conditions Using AND, OR and EXCLUSIVE OR

Evaluating Conditions Using AND, OR and EXCLUSIVE OR, continued

Instruc-

tion

A/AN O/ON X/XN

Status word for: A/AN/O/ON/X/XN BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: Yes Yes Yes Yes Yes Yes – Yes Yes Instruction affects: – – – – – Yes Yes Yes 1

S7-400 Instruction List A5E00267845-01

Address

ID

AND/AND-NOT

OR/OR-NOT

EXCLUSIVE-OR/

UO

OS AND OS=1 1 0.1 0.06 0.04 0.03 BR AND BR=1 1 0.1 0.06 0.04 0.03 OV AND OV=1 1 0.1 0.06 0.04 0.03

EXCLUSIVE-OR-NOT

Unordered math instruction

(CC1=1 and CC0=1)

Description

Length

in

Words

1 0.1 0.06 0.04 0.03

Execution Time in s

CPU 412 CPU 414 CPU 416 CPU 417

37

Edge-Triggered Instructions

Execution Time in s

Length

Execution Time in s

Instruc-

tion

Address ID

Description

in

Words

.

c [d]

2

0.2+/0.3+

0.12+/0.18+

0.08+/0.12+

0.06+/0.12+

Edge-Triggered Instructions

The current RLO is compared with the status of the instruction or “edge bit memory”. FP detects a change from “0” to “1”; FN detects a change from “1” to “0”.

Instruc-

FP/FN I/Q a.b

Status word for: FP, FN BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – Yes – Instruction affects: – – – – – 0 Yes Yes 1

+ Plus time required for loading the address of the instruction (see page 20)

*)

Unnecessary if the bit being monitored is in the process image (local data of a block are only valid while the block is running).

**)

I, Q, M, L /DB, DI

S7-400 Instruction List A5E00267845-01

M a.b L a.b* DBX a.b DIX a.b

c [AR1,m] ** c [AR2,m] ** [AR1,m]** [AR2,m]** Parameter**

The positive/negative edge is indicated by RLO = 1. The bit

)

addressed in the instruction is the auxiliary edge bit memory

Length

in

2 2 2 2 2

CPU 412 CPU 414 CPU 416 CPU 417

0.2

0.3

0.2+/0.3+

0.12

0.18

0.12+/0.18+

0.08

0.12

0.08+/0.12+

0.06

0.12

0.06+/0.12+

38

Setting/Resetting Bit Addresses

Instruc-

Lengt

Execution Time in s

Instruc-

Address

Lengt

Setting/Resetting Bit Addresses

Assigning the value “1” or “0” to the addressed instruction when RLO = 1. The instructions can be dependent on the MCR (see page 97).

tion

S R

ID

I/Q a.b M a.b L a.b DBX a.b DIX a.b c [d] c [AR1,m] c [AR2,m] [AR1,m] [AR2,m] Parameter

Set addressed bit to “1” Set addressed bit to “0” Input/output Bit memory Local data bit Data bit Instance data bit Memory-indirect, area-internal Register-indirect, area-internal (AR1) Register-indirect, area-internal (AR2) Area-crossing (AR1) Area-crossing (AR2) Via parameter

Description

***

*** ***

h in

Words

1*/2

1**/2

*** ***

CPU 412 CPU 414 CPU 416 CPU 417

0.2

0.2 2 2 2 2 2 2 2 2 2

0.2

0.3

0.2+/0.3+

0.12

0.18

0.12+/0.18+

0.08

0.12

0.08+/0.12+

0.08+/0.12+ Status word for: S, R BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – Yes – Instruction affects: – – – – – 0 Yes – 0

+ Plus time required for loading the address of the instruction (see page 20)

*)

With direct instruction addressing; Address area 0 to 127

**)

With direct instruction addressing; Address area 0 to 255

***)

I, Q, M, L / DB, DI

S7-400 Instruction List A5E00267845-01

0.06

0.12

0.06+/0.12+

39

Setting/Resetting Bit Addresses

Instru

Length

Execution Time in s

Instru

Address

Length

Setting/Resetting Bit Addresses, continued

The RLO is written to the address of the instruction. The instructions can be dependent on the MCR (see page 97).

Ction

=

Status word for: = BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – Yes – Instruction affects: – – – – – 0 Yes – 0

+ Plus time required for loading the address of the instruction (see page 20)

*)

With direct instruction addressing; Address area 0 to 127 **)With direct instruction addressing; Address area 0 to 255 ***)I, Q, M, L / DB, DI

S7-400 Instruction List A5E00267845-01

ID

I/Q a.b M a.b L a.b DBX a.b DIX a.b c [d] c [AR1,m] c [AR2,m] [AR1,m] [AR2,m] Parameter

Assign RLO To input/output To bit memory To local data bit To data bit To instance data bit Memory-indirect, area-internal *** Register-indirect, area-internal (AR1) *** Register-indirect, area-internal (AR2) *** Area-crossing (AR1) *** Area-crossing (AR2) *** Via parameter ***

Description

in

Words

1*/2

1**/2

2 2 2 2 2 2 2 2 2

CPU 412 CPU 414 CPU 416 CPU 417

0.2

0.3

0.2+/0.3+

0.12

0.18

0.12+/0.18+

0.08

0.12

0.08+/0.12+

0.06

0.12

0.06+/0.12+

40

Instructions Directly Affecting the RLO

Instruc-

Address

Instruc-

Address

Description

Length

in

Words

Instructions Directly Affecting the RLO

The following instructions have a direct effect on the RLO.

Length

tion

CLR Set RLO to “0” 1 0.1 0.06 0.04 0.03 Status word for: CLR BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – – – Instruction affects: – – – – – 0 0 0 0

SET Set RLO to “1” 1 0.1 0.06 0.04 0.03 Status word for: SET BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – – – Instruction affects: – – – – – 0 1 1 0

NOT Negate RLO 1 0.1 0.06 0.04 0.03 Status word for: NOT BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – Yes – Yes – Instruction affects: – – – – – – 1 Yes –

SAVE Save RLO to the BR bit 1 0.1 0.06 0.04 0.03 Status word for: SAVE BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – Yes – Instruction affects: Yes – – – – – – – –

ID

CPU 412 CPU 414 CPU 416 CPU 417

Execution Time in s

S7-400 Instruction List A5E00267845-01

41

Timer Instructions

In-

Length

Execution Time in s

struc-

Address

in

Timer Instructions

Starting o r resetting a timer. The time value must be in ACCU1-L. The instructions are triggered by an edge transition in the RLO; that is, when the status of the RLO has changed between two calls.

tion

SP Tf

SE Tf

SD Tf

Status word for SP, SE, SD BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – Yes – Instruction affects: – – – – – 0 – – 0

+ Plus time required for loading the address of the instruction (see page 20)

1)

With direct instruction addressing Timer No.: 0 to 255 S7-400 Instruction List

A5E00267845-01

ID

T [e] Timer para. 2 0.2+ 0.12+ 0.08+ 0.06+

T [e] Timer para. 2 024+ 0.12+ 0.08+ 0.06+

T [e] Timer para. 2 0.2+ 01.2+ 0.08+ 0.06+

Start timer as pulse on edge change from “0” to “1”

Start timer as extended pulse on edge change from “0” to “1”

Start timer as ON delay on edge change from “0” to “1”

Description

Words

11)/2 0.2

CPU 412 CPU 414 CPU 416 CPU 417

0.2+

0.12

0.12+

0.12

0.2+

0.12

0.12+

0.08

0.08+

0.08

0.08+

0.08

0.08+

0.06

0.06+

0.06

0.06+

0.06

0.06+

42

Timer Instructions, continued

In-

Length

Execution Time in s

struc-

Address

in

Timer Instructions

tion

SS Tf

SF Tf

Status word for SS, SF BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – Yes – Instruction affects: – – – – – 0 – – 0

S7-400 Instruction List A5E00267845-01

ID

T [e] Timer para. 2 0.2+ 0.12+ 0.08+ 0.06+

Start timer as retentive ON delay on edge change from “0” to “1”

Start timer as OFF delay on edge change from “0” to “1”

Description

Words

11)/2 0.2

CPU 412 CPU 414 CPU 416 CPU 417

0.2+

0.12

0.12+

0.12

0.12+

0.08

0.08+

0.08

0.08+

0.06

0.06+

0.06

0.06+

43

Timer Instructions, continued

In-

Length

Execution Time in s

struc-

Address

in

(reset edge bit memory for

Timer Instructions

tion

FR Tf

R Tf

Status word for: FR, R BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – Yes – Instruction affects: – – – – – 0 – – 0

+ Plus time required for loading the address of the instruction (see page 20)

1)

With direct instruction addressing Timer No.: 0 to 255 S7-400 Instruction List

A5E00267845-01

ID

T [e] Timer para.

T [e] Timer para. 2 0.2+ 0.12+ 0.08+ 0.06+

Enable timer for restarting on edge change from “0” to “1”

starting timer) Reset timer 11)/2 0.2

Description

Words

11)/2 0.2

2 0.2+ 01.2+ 0.08+ 0.06+

CPU 412 CPU 414 CPU 416 CPU 417

0.2+

0.12

0.12+

0.12

0.12+

0.08

0.08+

0.08

0.08+

0.06

0.06+

0.06

0.06+

44

Counter Instructions

In-

Length

Execution Time in s

struc-

in

The count value must be in ACCU1-L in the form of a BCD number (0 - 999).

Counter Instructions

tion

S Cf

R Cf

CU Cf

Status word for: S, R, CU BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – Yes – Instruction affects: – – – – – 0 – – 0

+ Plus time required for loading the address of the instruction (see page 20)

1)

S7-400 Instruction List A5E00267845-01

Address ID Description

C [e] Counter para. 2 0.2+ 0.12+ 0.08+ 0.06+

With direct instruction addressing Counter No.: 0 to 255

Presetting of counter on edge change from “0” to “1”

Reset counter to “0” when RLO = “1”

Increment counter by 1 on edge change from “0” to “1”

Words

11)/2 0.2

CPU 412 CPU 414 CPU 416 CPU 417

0.4+

0.2+

0.12

0.12+

0.12

0.12+

0.12

0.12+

0.08

0.08+

0.08

0.08+

0.08

0.08+

0.06

0.06+

0.06

0.06+

0.06

0.06+

45

Counter Instructions, continued

In-

Length

Execution Time in s

struc-

in

memory for up and down

Counter Instructions

tion

CD Cf

FR Cf

Status word for: CD, FR BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – Yes – Instruction affects: – – – – – 0 – – 0

+ Plus time required for loading the address of the instruction (see page 20)

1)

S7-400 Instruction List A5E00267845-01

Address ID Description

C [e]

C [e] Counter para.

With direct instruction addressing Counter No.: 0 to 255

Decrement counter by 1 on edge change from “0” to “1”

Enable counter on edge change from “0” to “1” (reset edge bit

counting and setting the counter)

Words

11)/2 0.2

2 0.2+ 0.12+ 0.08+ 0.06+

CPU 412 CPU 414 CPU 416 CPU 417

0..2+

0.2+

0.12

0.2+

0.12

0.12+

0.08

0.08+

0.08

0.08+

0.06

0.06+

0.06

0.06+

46

Load Instructions

In-

Length

Execution Time in s

struc-

Address

in

Load Instructions

Loading address identifiers into ACCU1. The contents of ACCU1 are first saved to ACCU2. The status word is not affected.

Description

2)

Words

11)/2

CPU 412 CPU 414 CPU 416 CPU 417

0.1/0.125

2

0.125

13)/220.1/0.125

0.125

2 2

0.2

0.06/0.075

0.075

0.06/0.075

0.075

0.12

0.04/0.05

0.05

0.04/0.05

0.05

0.08

L

tion

ID

IB a QB a PIB a

MB a LB a

DBB a DIB a

Load ... Input byte Output byte Peripheral input byte

Bit memory byte Local data byte

Data byte Instance data byte ... into ACCU1

g [d] g [AR1,m] g [AR2,m] B[AR1,m] B[AR2,m] Parameter

+ Plus time required for loading the address of the instruction (see page 20)

1)

With indirect instruction addressing; Address area 0 to 127

2)

The following peripheral acknowledgement time must be observed with CPU 414-4H and CPU 417-4H: solo xx s, redundant xx s

3)

With direct instruction addressing; Address area 0 to 255

4)

I, Q, P, M, L / DB, DI S7-400 Instruction List

A5E00267845-01

Memory-indirect, area-internal Register-indirect, area-internal (AR1) Register-indirect, area-internal (AR2) Area-crossing (AR1) Area-crossing (AR2) Via parameter

4)

2 2 2 2 2 2

0.1+/0.2+

0.125+/0.2+

4)

0.06+/0.12+

0.075+/0.12+

0.04+/0.08+

0.05+/0.08+

0.03+/0.09+

0.42+/0.09+

0.03/0.042

0.042

0.03/0.042

0.042

0.09

47

Load Instructions

In-

Length

Execution Time in s

struc-

Address

in

Load Instructions, continued

If there is a remainder of 3 following an integral division of the used addresses by 4, the execution times for instructions specified on this page are doubled.

Description

2)

Words

11)/2

CPU 412 CPU 414 CPU 416 CPU 417

0.1/0.125

13)/220.1/0.125

0.125

2 2

0.2

0.06/0.075

0.075

0.12

0.04/0.05

0.05

0.08

L

tion

ID

IW a QW PIW a

MW a LW a

DBW a DIW a

Load ... Input word Output word Peripheral input word

Bit memory word Local data word

Data word Instance data word ... into ACCU1-L

h [d] h [AR1,m] h [AR2,m] W[AR1,m] W[AR2,m] Parameter

+ Plus time required for loading the address of the instruction (see page 20)

1)

With indirect instruction addressing; Address area 0 to 127

2)

The following peripheral acknowledgement time must be observed with CPU 414-4H and CPU 417-4H: solo xx s, redundant xx s

3)

With direct instruction addressing; Address area 0 to 255

4)

I, Q, P, M, L / DB, DI S7-400 Instruction List

A5E00267845-01

Memory-indirect, area-internal Register-indirect, area-internal (AR1) Register-indirect, area-internal (AR2) Area-crossing (AR1) Area-crossing (AR2) Via parameter

4)

2 2 2 2 2 2

0.1+/0.2+

0.125+/0.2+

0.06+/0.12+

0.075+/0.12+

0.04+/0.08+

0.05+/0.08+

0.042+/0.09+

0.03/0.042

0.042

0.09

0.03+/0.09+

48

Load Instructions

In-

Length

Execution Time in s

struc-

Address

in

Load Instructions, continued

If the used address is divisible by 4without a remainder, the execution times for instructions specified on this page is doubled.

Description

Words

11)/2

2)

11)/2

13)/2 2

2 2

CPU 412 CPU 414 CPU 416 CPU 417

0.1/0.125

0.125

0.2

0.06/0.075

0.075

0.12

0.04/0.05

0.05

0.08

L

tion

ID

IDa QD a PID a

MD a LD a

DBD a DID a

Load ... Input double word Output double word Peripheral input double word

Bit memory double word Local data double word

Data double word Instance data double word ... in ACCU1

i [d] i [AR1,m] i [AR2,m] D[AR1,m] D[AR2,m] Parameter

+ Plus time required for loading the address of the instruction (see page 20)

1)

With indirect instruction addressing; Address area 0 to 127

2)

The following peripheral acknowledgement time must be observed with CPU 414-4H and CPU 417-4H: solo xx s, redundant xx s

3)

With direct instruction addressing; Address area 0 to 255

4)

I, Q, P, M, L / DB, DI

S7-400 Instruction List A5E00267845-01

Memory-indirect, area internal Register-ind., area internal (AR1) Register-ind., area internal (AR2) Area-crossing (AR1) Area-crossing (AR2) Via parameter

4)

2 2 2 2 2 2

0.1+/0.2+

0.125+/0.2+

0.06+/0.12+

0.075+/0.12+

0.04+/0.08+

0.05+/0.08+

0.03+/0.09+

0.042+/0.09+

0.03/0.042

0.042

0.09

49

Load Instructions, continued

In-

Length

Execution Time in s

struc-

Address

in

Load Instructions

tion

L

L 2#n Load 16-bit binary constant into

L W#16#p Load 16-bit hexadecimal

S7-400 Instruction List A5E00267845-01

ID

k8 k16 k32

Parameter Load constant into ACCU1

B#16#p Load 8-bit-hexadecimal constant

DW#16#p Load 32-bit hexadecimal

Load ... 8-bit constant into ACCU1-LL 16-bit constant into ACCU1-L 32-bit constant into ACCU1

(addressed via parameter)

ACCU1-L Load 32-bit binary constant into

ACCU1

into ACCU1-L

constant into ACCU1-L

constant into ACCU1

Description

Words

2 2 3

2 0.3+ 0.18+ 0.12+ 0.12+

2 0.125 0.075 0.05 0.042

3 0.185 0.112 0.075 0.062

1 0.1 0.06 0.04 0.03

2 0.125 0.075 0.05 0.042

3 0.185 0.112 0.075 0.065

CPU 412 CPU 414 CPU 416 CPU 417

0.125

0.185

0.075

0.112

0.05

0.075

0.042

0.062

50

Load Instructions, continued

In-

Length

Execution Time in s

struc-

in

Load Instructions

tion

L ’x’ Load 1 character 2 0.125 0.075 0.05 0.042

L D# time value Load IEC date 3 0.185 0.112 0.075 0.062 L S5T# time value Load S7 time constant (16 bits) 2 0.125 0.075 0.05 0.042 L TOD# time va-

L T# time value Load 16-bit time constant 2 0.125 0.075 0.05 0.042

L C# count value Load counter constant (BCD code) 2 0.125 0.075 0.05 0.042 L B# (b1, b2) Load constant as byte (b1, b2) 2 0.125 0.075 0.05 0.042

S7-400 Instruction List A5E00267845-01

Address ID Description

’xx’ Load 2 characters 2 0.125 0.075 0.05 0.042 ’xxx’ Load 3 characters 3 0.185 0.112 0.075 0.062 ’xxxx’ Load 4 characters 3 0.185 0.112 0.075 0.062

lue

B# (b1, b2, b3, b4)

Load IEC time constant 3 0.185 0.112 0.075 0.062

Load 32-bit time constant 3 0.185 0.112 0.075 0.062

Load constant as 4 bytes (b1, b2, b3, b4)

Words

3 0.185 0.112 0.075 0.062

CPU 412 CPU 414 CPU 416 CPU 417

51

Load Instructions, continued

In-

Length

Execution Time in s

struc-

in

Load Instructions

tion

L P# bit pointer Load bit pointer 3 0.185 0.112 0.075 0.062 L L# integer Load 32-bit integer constant 3 0.185 0.112 0.075 0.062 L Real number Load floating-point number 3 0.185 0.112 0.075 0.062

S7-400 Instruction List A5E00267845-01

Address ID Description

Words

CPU 412 CPU 414 CPU 416 CPU 417

52

Load Instructions for Timers and Counters

In-

Length

Execution Time in s

In-

Length

Load Instructions for Timers and Counters

Loading a time value or count value into ACCU1. The contents of ACCU1 are first saved to ACCU2. The bits of the status word are not affected.

struc-

tion

L T f

L C f

LC T f

LC C f

+ Plus time required for loading the address of the instruction (see page 20)

1)

S7-400 Instruction List A5E00267845-01

Address ID Description

Load time value 11)/220.1/0.12

T (e)

Timer para. Load time value (addressed via parameter) 2 0.1+ 0.06+ 0.04+ 0.03+

Load count value 11)/220.1/0.12

C (e)

Counter para. Load count value (addressed via parameter) 2 0.1+ 0.06+ 0.04+ 0.03+

Load time value in BCD 11)/2

T (e) Timer para. Load time value in BCD (addressed via parameter) 2 0.3+ 0.18+ 0.12+ 0.09+

Load count value in BCD 11)/2

C (e) Counter para. Load count value in BCD (addressed via parameter) 2 0.3+ 0.18+ 0.12+ 0.09+

With direct instruction addressing; Timer/counter No.: 0 to 255

in

Words

2

CPU

412

5

0.1+

5

xx+

0.3

0.3+

0.3

0.3+

CPU

414

0.06/0.0 75

0.06+

0.06/0.0 75

0.06+

0.18

0.18+

0.18

0.18+

CPU

416

0.04/0.0 5

0.04+

0.04/0.0 5

0.04+

0.12

0.12+

0.12

0.12+

CPU

417

0.03/0.0 42

0.03+

0.03/0.0 42

0.03+

0.09

0.09+

0.09

0.09+

53

Transfer Instructions

In-

Length

Execution Time in s

struc-

Address

in

Transfer Instructions

Transferring the contents of ACCU1 to the addressed operand. Note that some instructions are affected by the MCR (see page LEERER MERKER). The status word is not affected.

tion

T

+ Plus time required for loading the address of the instruction (see page 20)

1)

With direct instruction addressing; Address area 0 to 127

2)

The following peripheral acknowledgement time must be observed with CPU 414-4H and CPU 417-4H: solo xx s, redundant xx s

3)

With direct instruction addressing; Address area 0 to 255

S7-400 Instruction List A5E00267845-01

ID

IB a QB a PQB a

MB a LB a

DBB a DIB a

g [d] g [AR1,m] g [AR2,m] B[AR1,m] B[AR2,m] Parameter

Transfer contents of ACCU1-LL to ... input byte output byte peripheral output byte

bit memory byte local data byte

data byte instance data byte

Memory-indirect, area internal Register-ind., area internal (AR1) Register-ind., area internal (AR2) Area-crossing (AR1) Area-crossing (AR2) Via parameter

Description

Words

11)/2

2)

11)/2 2

13)/2 2

2 2

2 2 2 2 2 2

CPU 412 CPU 414 CPU 416 CPU 417

0.1/0.125

0.125

0.1/0.125

0.125

0.335

0.1+

0.125+

0.06/0.075

0.075

0.06/0.075

0.075

0.06+

0.075+

0.04/0.05

0.05

0.04/0.05

0.05

0.04+

0.05+

0.03/0.042

0.042

0.03/0.042

0.042

0.03+

0.042+

54

Transfer Instructions

Instruc-

Length

Execution Time in s

tion

Address

in

Transfer Instructions, continued

If there is a remainder of 3 following an integral division of the used addresses by 4, the execution times for instructions specified on this page are doubled.

ID

T

IW a QW a PQW a

MW a LW a

DBW a DIW a

h [d] h [AR1,m] h [AR2,m] W[AR1,m] W[AR2,m] Parameter

+ Plus time required for loading the address of the instruction (see page 20)

1)

With direct instruction addressing; Address area 0 to 127

2)

The following peripheral acknowledgement time must be observed with CPU 414-4H and CPU 417-4H: solo xx s, redundant xx s

3)

With direct instruction addressing; Address area 0 to 255

S7-400 Instruction List A5E00267845-01

Transfer contents of ACCU1-L to ... input word output word peripheral output word

bit memory word local data word

data word instance data word

Memory-indirect, area internal Register-ind., area internal (AR1) Register-ind., area internal (AR2) Area-crossing (AR1) Area-crossing (AR2) Via parameter

Description

2)

Words

11)/2

13)/2 2

2 2

2 2 2 2 2 2

CPU 412 CPU 414 CPU 416 CPU 417

0.1/0.125

0.125

0.335

0.1+

0.125+

0.06/0.075

0.075

0.06+

0.075+

0.04/0.05

0.05

0.04+

0.05+

0.03/0.042

0.042

0.03+

0.042+

55

Transfer Instructions

Instruc-

Length

Execution Time in s

tion

Address

in

Transfer Instructions, continued

If the used address is divisible by 4without a remainder, the execution times for instructions specified on this page is doubled.

ID

T

ED a AD a PAD a

MD a LD a

DBD a DID a

T i [d]

+ Plus time required for loading the address of the instruction (see page 20)

1)

With direct instruction addressing; Address area 0 to 127

2)

The following peripheral acknowledgement time must be observed with CPU 414-4H and CPU 417-4H: solo xx s, redundant xx s

3)

With direct instruction addressing; Address area 0 to 255

S7-400 Instruction List A5E00267845-01

i [AR1,m] i [AR2,m] D[AR1,m] D[AR2,m] Parameter

Transfer contents of ACCU1 to ... Input double word Output double word periph. output double word

Bit memory double word Local data double word

Data double word Instance data double word

Memory-indirect, area internal Register-ind., area internal (AR1) Register-ind., area internal (AR2) Area-crossing (AR1) Area-crossing (AR2) Via parameter

Description

Words

11)/2

2)

11)/2 2

13)/2 2

2 2

2 2 2 2 2 2

CPU 412 CPU 414 CPU 416 CPU 417

0.1/0.125

0.125

0.1/0.125

0.125

0.11

0.1+

0.125+

0.06/0.075

0.075

0.06/0.075

0.075

0.06+

0.075+

0.04/0.05

0.05

0.04/0.05

0.05

0.04+

0.05+

0.03/0.042

0.042

0.03/0.042

0.042

0.03+

0.042+

56

Load and Transfer Instructions for Address Registers

Instruc-

Address

Instruc-

Address

Description

Length

in

Load and Transfer Instructions for Address Registers

Loading a double word from a memory area or register into address register 1 (AR1) or address register 2 (AR2). The status word is not affected.

Execution Time in s

0.12

0.18

0.12

0.18

0.12

0.08

0.12

0.08

0.12

0.08

0.06

0.12

0.062 006 006

0.06

0.12

0.062

0.06

tion

LAR1

LAR2

ID

– AR2 DBD a DID a m LD a MD a

– DBD a DID a m LD a MD a

Load contents from ... ACCU1 Address register 2 Data double word Instance data double word 32-bit constant as pointer Local data double word Bit memory double word ... into AR1

Load contents from ... ACCU1 Data double word Instance data double word 32-bit constant as pointer Local data double word Bit memory double word ... into AR2

Length

Words

1 1 2 2 3 2 2

1 2 2 3 2 2

CPU 412 CPU 414 CPU 416 CPU 417

0.2

0.3

0.2

0.3

0.2

S7-400 Instruction List A5E00267845-01

57

Load and Transfer Instructions for Address Registers

Instruc-

Address

Instruc-

Address

Description

Length

in

Load and Transfer Instructions forAddress Registers, continued

Transferring a double word from address register 1 (AR1) or address register 2 (AR2) to a memory area or register. The contents of ACCU1 are first saved to ACCU2. The status word is not affected.

tion

TAR1

TAR2

CAR Exchange the contents of AR1

S7-400 Instruction List A5E00267845-01

ID

– AR2 DBD a DID a LD a MD a

– DBD a DID a LD a MD a

Transfer contents from AR1 in ... ACCU1 Address register 2 Data double word Instance data double word Local data double word Bit memory double word

Transfer contents from AR2 in ... ACCU1 Data double word Instance data double word Local data double word Bit memory double word

and AR2

Length

Words

1 1 2 2 2 2

1 2 2 2 2

1 0.2 0.12 0.08 0.06

CPU 412 CPU 414 CPU 416 CPU 417

0.1

0.2

0.125

0.1

0.125

Execution Time in s

0.06

0.12

0.075

0.06

0.075

0.04

0.08

0.05

0.04

0.05

0.03

0.06

0.042

0.03

0.042

58

Load and Transfer Instructions for the Status Word

Instruc-

Address

Instruc-

Address

Description

Length

in

Instruc-

Address

Instruc-

Address

Description

Length

in

Load and Transfer Instructions for the Status Word

Length

tion

L STW Load status word into ACCU1 0.1 0.06 0.04 0.3 Status word for: L STW BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: Yes Yes Yes Yes Yes Yes Yes Yes Yes Instruction affects: – – – – – – – – –

tion

T STW Transfer ACCU1 (bits 0 to 8) to

Status word for: T STW BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – – – Instruction affects: Yes Yes Yes Yes Yes Yes Yes Yes Yes

S7-400 Instruction List A5E00267845-01

ID

the status word

Words

Length

Words

CPU 412 CPU 414 CPU 416 CPU 417

0.1 0.06 0.04 0.03

Execution Time in s

59

Load Instructions for DB Number and DB Length

Instruc-

Address

Instruc-

Address

Description

Length

in

Load Instructions for DB Number and DB Length

Loading the number/length of a data block into ACCU1. The old contents of ACCU1 are saved to ACCU2. The status word is not affected.

Length

tion

L DBNO Load number of data block 1 0.1 0.06 0.04 0.03 L DINO Load number of instance data

L DBLG Load length of data block into

L DILG Load length of instance data

S7-400 Instruction List A5E00267845-01

ID

block

byte

block into byte

Words

1 0.1 0.06 0.04 0.03

CPU 412 CPU 414 CPU 416 CPU 417

Execution Time in s

60

Integer Math (16 Bits)

Instruc-

Address

Instruc-

Address

Description

Length

in

Integer Math (16 Bits)

Math instructions on two 16-bit words. The result is written to ACCU1 and/or ACCU1-L. ACCU3 and ACCU4 are then transferred to ACCU2 and ACCU3.

Length

tion

+I Add 2 integers (16 bits)

–I Subtract 1 integer from another (16 bits)

Status word for: +I, –I, BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – – – Instruction affects: – Yes Yes Yes Yes – – – –

S7-400 Instruction List A5E00267845-01

ID

(ACCU1-L)=(ACCU1-L)+(ACCU2-L)

(ACCU1-L)=(ACCU2-L)-(ACCU1-L)

Words

1 0.1 0.06 0.04 0.03

CPU 412 CPU 414 CPU 416 CPU 417

Execution Time in s

61

Integer Math (16 Bits)

Instruc-

Address

Instruc-

Address

Description

Length

in

Length

tion

I Multiply 1 integer by another (16 bits)

*

/I Divide 1 integer by another (16 bits)

Status word for: Instruction evaluates: – – – – – – – – – Instruction affects: – Yes Yes Yes Yes – – – –

ID

(ACCU1)=(ACCU2-L)*(ACCU1-L)

(ACCU1-L)=(ACCU2-L):(ACCU1-L) The remainder is in ACCU1-H

I, /I BR CC1 CC0 OV OS OR STA RLO /FC

*

Words

1 0.1 0.06 0.04 0.03

1 0.1 0.24 0.16 0.12

CPU 412 CPU 414 CPU 416 CPU 417

Execution Time in s

S7-400 Instruction List A5E00267845-01

62

Integer Math (32 Bits)

Instruc-

Address

Instruc-

Address

Description

Length

in

Integer Math (32 Bits)

Math instructions on two 32-bit words. The result is written to ACCU1. ACCU3 and ACCU4 are then transferred to ACCU2 and ACCU3.

Length

tion

+D Add 2 integers (32-bit)

–D Subtract 2 integer from another (32 bits)

D Multiply 2 integer by another (32 bits)

*

Status word for: +D, –D,*D, /D BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – – – Instruction affects: – Yes Yes Yes Yes – – – –

S7-400 Instruction List A5E00267845-01

ID

(ACCU1)=(ACCU2)+(ACCU1)

(ACCU1)=(ACCU2)-(ACCU1)

(ACCU1)=(ACCU2)*(ACCU1)

Words

1 0.1 0.06 0.04 0.03

CPU 412 CPU 414 CPU 416 CPU 417

Execution Time in s

63

Integer Math (32 Bits)

Instruc-

Address

Instruc-

Address

Description

Length

in

Length

tion

/D Divide 2 integer by another (32 bits)

MOD Divide 2 integer by another (32 bits) and

Status word for: /D, MOD BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – – – Instruction affects: – Yes Yes Yes Yes – – – –

ID

(ACCU1)=(ACCU2):(ACCU1)

load the remainder into ACCU1: (ACCU1)=remainder of [(ACCU2):(ACCU1)]

Words

1 0.6 0.36 0.24 0.18

CPU 412 CPU 414 CPU 416 CPU 417

Execution Time in s

S7-400 Instruction List A5E00267845-01

64

Floating-Point Math (32 Bits)

Instruc-

Address

Instruc-

Address

Description

Length

in

Floating-Point Math (32 Bits)

The result of the math instruction is in ACCU1. ACCU3 and ACCU4 are then transferred to ACCU2 and ACCU3.

Length

tion

+R Add 2 real numbers (32 bits)

–R Subtract 1 real number from another (32 bits)

R Multiply 1 real number by another (32 bits)

*

/R Divide 1 real number by another (32 bits)

Status word for: +R, –R, *R, /R BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – – – Instruction affects: – Yes Yes Yes Yes – – – –

S7-400 Instruction List A5E00267845-01

ID

(ACCU1)=(ACCU2)+(ACCU1)

(ACCU1)=(ACCU2)-(ACCU1)

(ACCU1)=(ACCU2)*(ACCU1)

(ACCU1)=(ACCU2):(ACCU1)

Words

CPU 412 CPU 414 CPU 416 CPU 417

1 0.4 0.24 0.16 0.12

1 0.2 0.12 0.08 0.06

1 0.7 0.42 0.28 0.21

Execution Time in s

65

Floating-Point Math (32 Bits), continued

Instruc-

Address

Instruc-

Address

Description

in

Floating-Point Math (32 Bits)

Length

tion

NEGR Negate the real number in

ABS Form the absolute value of the real

Status word for: NEGR, ABS BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – – – Instruction affects: – – – – – – – – –

S7-400 Instruction List A5E00267845-01

ID

ACCU1

number in ACCU1

Words

1 0.1 0.06 0.04 0.03

CPU 412 CPU 414 CPU 416 CPU 417

Execution Time in s

66

Square Root and Square Instructions (32 Bits)

Instruc-

Address

Instruc-

Address

Description

Length

in

Square Root and Square Instructions (32 Bits)

The result of the instruction is in ACCU1. The SQRT instruction can be interrupted.

Length

tion

SQRT Calculate the square root of a

SQR Form the square of the real

Status word for: SQRT, SQR BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – – – Instruction affects: – Yes Yes Yes Yes – – – –

S7-400 Instruction List A5E00267845-01

ID

real number in ACCU1

number in ACCU1

Words

1 1.7 1.02 0.68 0.51

1 0.2 0.12 0.08 0.06

CPU 412 CPU 414 CPU 416 CPU 417

Execution Time in s

67

Logarithmic Function (32 Bits)

Instruc-

Address

Instruc-

Address

Description

Length

in

The result of the logarithmic function is in ACCU1. The instructions can be interrupted.

Logarithmic Function (32 Bits)

Length

tion

LN Form the natural logarithm of a

EXP Calculate the exponential value

Status word for: LN, EXP BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – – – Instruction affects: – Yes Yes Yes Yes – – – –

S7-400 Instruction List A5E00267845-01

ID

real number in ACCU1

of a real number in ACCU1 to the base e (= 2.71828)

Words

1 20 13 9 7

1 21 15 10 8

CPU 412 CPU 414 CPU 416 CPU 417

Execution Time in s

68

Trigonometrical Functions (32 Bits)

Instruc-

Address

Instruc-

Address

Description

Length

in

The result of the instruction is in ACCU1. The instructions can be interrupted.

Trigonometrical Functions (32 Bits)

Length

tion

SIN Calculate the sine of a real

ASIN Calculate the arcsine of a real

COS Calculate the cosine of a real

ACOS Calculate the arccosine of a real

TAN Calculate the tangent of a real

ATAN Calculate the arctangent of a real

Status word for: SIN, ASIN, COS,

Instruction evaluates: – – – – – – – – – Instruction affects: – Yes Yes Yes Yes – – – –

S7-400 Instruction List A5E00267845-01

ID

number

ACOS, TAN, ATAN

Words

1 6,6 3,96 2,64 1,98

1 33 – 38 22 – 24 15 – 17 13

1 6,6 3,96 2,64 1,98

1 36 – 40 25 – 27 16 – 18 12 – 14

1 20 14 10 7

1 14 – 18 10 – 13 6 – 9 5 – 7

BR CC1 CC0 OV OS OR STA RLO /FC

CPU 412 CPU 414 CPU 416 CPU 417

Execution Time in s

69

Adding Constants

Instruc-

Address

Instruc-

Address

Description

Length

in

Adding integer constants and storing the result in ACCU1. The status word is not affected.

Adding Constants

Length

tion

+ i8 Add an 8-bit integer constant 1 0.1 0.06 0.04 0.03 + i16 Add a 16-bit integer constant 2 0.125 0.075 0.05 0.042 + i32 Add a 32-bit integer constant 3 0.185 0.11 0.075 0.062

S7-400 Instruction List A5E00267845-01

ID

Words

CPU 412 CPU 414 CPU 416 CPU 417

Execution Time in s

70

Adding Using Address Registers

Instruc-

Address

Instruc-

Address

Description

Length

in

Adding Using Address Registers

Adding a 16-bit integer to the contents of the address register. The value is either specified as an address in the instruction or is in ACCU1-L. The status word is not affected.

tion

+AR1 Add the contents of ACCU1-L to

+AR1 m (0 to

+AR2 Add the contents of ACCU1-L to

+AR2 m (0 to

S7-400 Instruction List A5E00267845-01

ID

4095)

those of AR1 Add a pointer constant to the

contents of AR1

those of AR2 Add pointer constant to the

contents of AR2

Length

Words

1 0.2 0.12 0.08 0.06

2 0.2 0.12 0.08 0.06

1 0.2 0.12 0.08 0.06

2 0.2 0.12 0.08 0.06

CPU 412 CPU 414 CPU 416 CPU 417

Execution Time in s

71

Comparison Instructions (16-Bit Integers)

Instruc-

Address

Instruc-

Address

Description

Length

in

Comparison Instructions (16-Bit Integers)

Comparing the 16-bit integers in ACCU1-L and ACCU2-L. RLO = 1 if the condition is satisfied.

Length

tion

==I ACCU2-L=ACCU1-L 1 0.1 0.06 0.04 0.03 <>I <I ACCU2-L<ACCU1-L 1 0.1 0.06 0.04 0.03 <=I ACCU2-L<=ACCU1-L 1 0.1 0.06 0.04 0.03 >I ACCU2-L>ACCU1-L 1 0.1 0.06 0.04 0.03 >=I ACCU2-L>=ACCU1-L 1 0.1 0.06 0.04 0.03 Status word for: ==I, <>I, <I, <=I, >I,

Instruction evaluates: – – – – – – – – – Instruction affects: – Yes Yes 0 – 0 Yes Yes 1

S7-400 Instruction List A5E00267845-01

ID

ACCU2-L0ACCU1-L

>=I

Words

1 0.1 0.06 0.04 0.03

BR CC1 CC0 OV OS OR STA RLO /FC

CPU 412 CPU 414 CPU 416 CPU 417

Execution Time in s

72

Comparison Instructions (32-Bit Integers)

Instruc-

Address

Instruc-

Address

Description

Length

in

Comparison Instructions (32-Bit Integers)

Comparing the 32-bit integers in ACCU1 and ACCU2. RLO = 1 if the condition is satisfied.

Length

tion

==D ACCU2=ACCU1 1 0.1 0.06 0.04 0.03 <>D <D ACCU2<ACCU1 1 0.1 0.06 0.04 0.03 <=D ACCU2<=ACCU1 1 0.1 0.06 0.04 0.03 >D ACCU2>ACCU1 1 0.1 0.06 0.04 0.03 >=D ACCU2>=ACCU1 1 0.1 0.06 0.04 0.03 Status word for: ==D,< >D, <D, <=D, >D,

Instruction evaluates: – – – – – – – – – Instruction affects: – Yes Yes 0 – 0 Yes Yes 1

S7-400 Instruction List A5E00267845-01

ID

>=D

ACCU20ACCU1

Words

1 0.1 0.06 0.04 0.03

BR CC1 CC0 OV OS OR STA RLO /FC

CPU 412 CPU 414 CPU 416 CPU 417

Execution Time in s

73

Comparison Instructions (32-Bit Real Numbers)

Instruc-

Address

Instruc-

Address

Description

Length

in

Comparison Instructions (32-Bit Real Numbers)

Comparing the 32-bit real numbers in ACCU1 and ACCU2. RLO = 1 if the condition is satisfied.

Length

tion

==R ACCU2=ACCU1 1 0.1 0.06 0.04 0.03 <>R <R ACCU2<ACCU1 1 0.1 0.06 0.04 0.03 <=R ACCU2<=ACCU1 1 0.1 0.06 0.04 0.03 >R ACCU2>ACCU1 1 0.1 0.06 0.04 0.03 >=R ACCU2>=ACCU1 1 0.1 0.06 0.04 0.03 Status word for: ==R, <>R, <R, <=R,

Instruction evaluates: – – – – – – – – – Instruction affects: – Yes Yes Yes Yes 0 Yes Yes 1

S7-400 Instruction List A5E00267845-01

ID

>R, >=R

ACCU20ACCU1

Words

1 0.1 0.06 0.04 0.03

BR CC1 CC0 OV OS OR STA RLO /FC

CPU 412 CPU 414 CPU 416 CPU 417

Execution Time in s

74

Shift Instructions

Instruc-

Address

Instruc-

Address

Description

Length

in

Shift the contents of ACCU1-L to the left. Positions that become free are provided with zeros.

1

0.1

0.06

0.04

0.03 t

Shift the contents of ACCU1 to the left. Positions that become free are provided with zeros.

1

0.1

0.06

0.04

0.03

Shift the contents of ACCU1-L to the right. Positions that become free are provided with zeros.

1

0.1

0.06

0.04

0.03

Shift Instructions

Shifting the contents of ACCU1 and ACCU1-L to the left or right by the specified number of places. If no address identifier is specified, the contents of ACCU2-LL are used as the number of places. The last bit shifted is loaded into condition code bit CC 1.

tion

1)

SLW SLW 0 ... 15 SLD Shift the contents of ACCU1 to the left. Positions tha SLD 0 ... 32

1)

SRW SRW 0 ... 15 Status word for: SLW, SLD, SRW BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – – –

Instruction affects: – Yes 0 0 – – – – –

1)

No. of places shifted: 0 to 16

S7-400 Instruction List A5E00267845-01

ID

Shift the contents of ACCU1-L to the left. Positions

Shift the contents of ACCU1-L to the right. Positions

Length

Words

CPU 412 CPU 414 CPU 416 CPU 417

1 0.1 0.06 0.04 0.03

Execution Time in s

75

Shift Instructions, continued

Instruc-

Address

Instruc-

Address

Description

Length

in

Shift the contents of ACCU1 to the right. Positions that become free are provided with zeros.

1

0.1

0.06

0.04

0.03

Positions that become free are provided with with the

Shift Instructions

Length

tion

SRD Shift the contents of ACCU1 to the right. Positions SRD 0 ... 32

1)

SSI SSI 0 ... 15 SSD Shift the contents of ACCU1 with sign to the right. SSD 0 ... 32 Status word for: SRD,SSI, SSD BR CC1 CC0 OV OS OR STA RLO /FC

Instruction evaluates: – – – – – – – – – Instruction affects: – Yes 0 0 – – – – –

1)

No. of places shifted: 0 to 16

ID

Shift the contents of ACCU1-L with sign to the right. sign (bit 15).

sign (bit 31).

Words

CPU 412 CPU 414 CPU 416 CPU 417

1 0.1 0.06 0.04 0.03

Execution Time in s

S7-400 Instruction List A5E00267845-01

76

Rotate Instructions

Instruc-

Address

Instruc-

Address

Description

Length

in

the left

the right

Rotate Instructions

Rotate the contents of ACCU1 to the left or right by the specified number of places. If no address identifier is specified, the contents of ACCU2-LL are used as the number of places. The last bit shifted is loaded into condition code bit CC1.

Length

tion

RLD Rotate the contents of ACCU1 to RLD 0 ... 32 RRD Rotate the contents of ACCU1 to RRD 0 ... 32 Status word for: RLD, RRD BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – – – Instruction affects: – Yes 0 0 – – – – –

S7-400 Instruction List A5E00267845-01

ID

Words

1 0.1 0.06 0.04 0.03

CPU 412 CPU 414 CPU 416 CPU 417

Execution Time in s

77

Rotate Instructions, continued

Instruc-

Address

Instruc-

Address

Description

Length

in

Rotate Instructions

Length

tion

RLDA Rotate the contents of ACCU1 one

RRDA Rotate the contents of ACCU1 one

Status word for: RLDA, RRDA BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – – – Instruction affects: – Yes 0 0 – – – – –

S7-400 Instruction List A5E00267845-01

ID

bit position to the left through condition code bit CC 1

bit position to the right through condition code bit CC 1

Words

CPU 412 CPU 414 CPU 416 CPU 417

0.1 0.06 0.04 0.03

Execution Time in s

78

Accumulator Transfer Instructions, Incrementing and Decrementing

Instruc-

Address

Instruc-

Address

Description

Length

in

Accumulator Transfer Instructions, Incrementing and Decrementing

The status word is not affected.

Length

tion

CAW Reverse the order of the bytes in ACCU1-L. 1 0.1 0.06 0.04 0.03 CAD Reverse the order of the bytes in ACCU1. 1 0.1 0.06 0.04 0.03 TAK Swap the contents of ACCU1 and ACCU2 1 0.1 0.06 0.04 0.03 ENT The contents of ACCU2 and ACCU3 are

LEAVE The contents of ACCU3 and ACCU4 are

PUSH The contents of ACCU1, ACCU2 and ACCU3

POP The contents of ACCU2, ACCU3 and ACCU4

S7-400 Instruction List A5E00267845-01

ID

transferred to ACCU3 and ACCU4.

transferred to ACCU2 and ACCU3.

are transferred to ACCU2, ACCU3 and ACCU4

are transferred to ACCU1, ACCU2 and ACCU3

Words

CPU 412 CPU 414 CPU 416 CPU 417

1 0.1 0.06 0.04 0.03

Execution Time in s

79

Accumulator Transfer Instructions, Incrementing and Decrementing, continued

Instruc-

Address

Instruc-

Address

Description

Length

in

Accumulator Transfer Instructions, Incrementing and Decrementing, continued

Length

tion

INC k8 Increment ACCU1-LL 1 0.1 0.06 0.04 0.03 DEC k8 Decrement ACCU1-LL 1 0.1 0.06 0.04 0.03

ID

Words

CPU 412 CPU 414 CPU 416 CPU 417

Execution Time in s

S7-400 Instruction List A5E00267845-01

80

Program Display and Null Operation Instructions

Instruc-

Address

Instruc-

Address

Description

Length

in

Program Display and Null Operation Instructions

The status word is not affected.

tion

BLD k8 Program display instruction:

NOP 0

S7-400 Instruction List A5E00267845-01

ID

Is treated by the CPU as a null operation instruction.

Null operation instruction 1 0.1 0.06 0.04 0.03

1

Length

Words

1 0.1 0.06 0.04 0.03

CPU 412 CPU 414 CPU 416 CPU 417

Execution Time in s

81

Data Type Conversion Instructions

Instruc-

Addr. ID

Description

Length

in

The results of the conversion are in ACCU1.

Data Type Conversion Instructions

Length

tion

BTI Convert contents of ACCU1-L

BTD Convert contents of ACCU1 from

DTR Convert contents of ACCU1 from

ITD Convert contents of ACCU1 from

Status word for: BTI, BTD, DTR, ITD BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – – – Instruction affects: – – – – – – – – –

S7-400 Instruction List A5E00267845-01

from BCD (0 to +/- 999) to integer (16 bits) (BCD To Int)

BCD (0 to +/-9 999 999) to double integer (32 bits) (BCD To Doubleint)

double integer (32 bits) to real number (32 bits) (Doubleint To Real)

integer (16 bits) to double integer (32 bits) (Int To Doubleint)

Words

1 0.1 0.06 0.04 0.03

1 0.3 0.18 0.12 0.09

1 0.3 0.06 0.04 0.03

CPU 412 CPU 414 CPU 416 CPU 417

Execution Time in s

82

Data Type Conversion Instructions, continued

Instruc-

Addr.

Instruc-

Addr.

Description

Length

in

Data Type Conversion Instructions

Length

tion

ITB Convert contents of ACCU1-L from

DTB Convert contents of ACCU1 from

Status word for: ITB, DTB BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – – – Instruction affects: – – – Yes Yes – – – –

S7-400 Instruction List A5E00267845-01

ID

integer (16 bits) to BCD from 0 to +/- 999 (Int To BCD)

double integer (32 bits) to BCD from 0 to +/- 9 999 999 (Doubleint To BCD)

Words

1 0.1 0.06 0.04 0.03

1 0.2 0.12 0.08 0.06

CPU 412 CPU 414 CPU 416 CPU 417

Execution Time in s

83

Data Type Conversion Instructions

Instruc-

Address

Instruc-

Address

Description

Length

in

Data Type Conversion Instructions, continued

The real number to be converted is in ACCU1.

Length

tion

RND+ Convert a real number into a

RND Convert a real number into a

RND- Convert a real number into a

TRUNC Convert a real number into a

Status word for: RND, RND-, RND+,

Instruction evaluates: – – – – – – – – – Instruction affects: – – – Yes Yes – – – –

ID

32-bit integer. The number is rounded up to the next whole number.

32-bit integer.

32-bit integer. The number is rounded down to the next whole number.

32-bit integer. The places after the decimal point are truncated.

TRUNC

Words

1 0.4 0.24 0.16 0.12

BR CC1 CC0 OV OS OR STA RLO /FC

CPU 412 CPU 414 CPU 416 CPU 417

Execution Time in s

S7-400 Instruction List A5E00267845-01

84

Forming the Ones and Twos Complements

Instruc-

Address

Instruc-

Address

Description

Length

in

Forming the Ones and Twos Complements

Length

tion

INVI Form the ones complement of

INVD Form the ones complement of

Status word for: INVI, INVD BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – – – Instruction affects: – – – – – – – – –

NEGI Form the twos complement of

NEGD Form the twos complement of

Status word for: NEGI, NEGD BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – – – Instruction affects: – Yes Yes Yes Yes – – – –

S7-400 Instruction List A5E00267845-01

ID

ACCU1-L

ACCU1

ACCU1-L (integer)

ACCU1 (double integer)

Words

1 0.1 0.06 0.04 0.03

CPU 412 CPU 414 CPU 416 CPU 417

Execution Time in s

85

Block Call Instructions

Address

struc-

Address

Description

Length

in

Block Call Instructions

The runtimes of the System Functions are specified in the chapter entitled “System Functions” as of page 106. The information on the status word only relates to the block call itself and not to the commands called in this block.

In-

tion

ID

CALL FB q, DB q Unconditional call of an FB, with

Length

Words

15/17

CPU 412 CPU 414 CPU 416 CPU 417

1)

4.0

3)

Execution Time in s

3)

2.4

1.6

3)

parameter transfer

CALL SFB q,

DB q

Unconditional call of an SFB, with parameter transfer

CALL FC q Unconditional call of a function,

16/17

7/8

1)

4.0

3.2

3)

2.4

1.92

3)

1.6

1.28

3)

with parameter transfer

CALL SFC q Unconditional call of an SFC,

8 3.2

3)

1.92

3)

1.28

3)

with parameter transfer Status word for: CALL BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – – – Instruction affects: – – – – 0 0 1 – 0

1)

The instruction length depends on the block number from (0...255 or more)

3)

Plus time required for supplying parameters

S7-400 Instruction List A5E00267845-01

1.26

1.02

3)

86

Block Call Instructions, continued

Address

struc-

Address

Description

Length

in

Block Call Instructions

In-

tion

UC FB q

CC FB q

ID

FC q FB [e] FC [e] Parameter

Unconditional call of blocks,

without parameter transfer

Memory-indirect FB call

Memory-indirect FC call

FB/FC call via parameter

Conditional call of blocks, without

parameter transfer

Memory-indirect FB call

Memory-indirect FC call

FB/FC call via parameter Status word for: UC, CC

Length

Words

11)/2

CPU 412 CPU 414 CPU 416 CPU 417

2.2

2.2 2 2 2

11)/2 2

2 2

2)

BR CC1 CC0 OV OS OR STA RLO /FC

2.2+

2.2/0.5

2.2+/0.5

4)

4) 4 4

Execution Time in s

1.32

1.32+

1.32/0.3

1.32+/0.3

4)

0.88

0.88+

0.88/0.2

0.88+/0.2

4)

0.72

0.72+

0.72/0.18

0.72+/0.18

Instruction evaluates: – – – – – – – – – Instruction affects: – – – – 0 0 1 – 0

+ Plus time required for loading the address of the instruction (see page 20)

1)

With direct instruction (DB) addressing; Block No. 0 to 255

2)

Depending on RLO, sets RLO = 1

4)

If call is not executed

4)

S7-400 Instruction List A5E00267845-01

87

Block Call Instructions, continued

Execution Time in s

Instruc-

Length

Execution Time in s

tion

Address

Description

in-

Words

Block Call Instructions

Instruc-

tion

OPN

Address

ID

DB q DI q DB [e] DI [e] Parameter

Open: Data block Instance data block Data block, memory-indirect Instance DB, memory-indirect Data block using parameters

Length

in-

11)/2

Direct Addressing

CPU 412 CPU 414 CPU 416 CPU 417

1)2);

0.1

0.1252); 0.5

0.5 /

1)2);

0.1

0.5 /

0.1252); 0.5

1)2);

0.1+

0.5+ /

0.125+2); 0.5+

1)2);

0.1+

0.5+ /

0.125+2); 0.5+

1)2);

0.1+

0.5+ /

0.125+2); 0.5+

1)2)

0.06

; 0.3 /

0.0752); 0.3

1)2)

0.06

; 0.3 /

0.0752); 0.3

1)2)

0.06+

0.075+2); 0.3+

0.06+

0.075+2); 0.3+

0.06+

1)2)

;0.3+/ ;0.3+/ ;0.3+/

0.075+2); 0.3+

1)2)

0.04

; 0.2 /

0.052); 0.2

1)2)

0.04

; 0.2 /

0.052); 0.2

1)2)

0.04+

,0.2+/

0.05+2); 0.2+

1)2)

,0.2+/

0.05+2); 0.2+

1)2)

,0.2+/

0.05+2); 0.2+ Status word for: OPN BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – – – Instruction affects: – – – – – – – – –

+ Plus time required for loading the address of the instruction (see page 20)

1)

With direct instruction (DB) addressing; Block No. 0 to 255

2)

If the same DB or DI is already selected

S7-400 Instruction List A5E00267845-01

1)2);

0.03

0.0422); 0.21

1)2);

0.03

0.0422); 0.21

1)2)

0.03+

2);

0.042+

1)2)

0.03+

2);

0.042+

1)2)

0.03+

2);

0.042+

0.21 /

0.21 / , 0.21+

0.21+

, 0.21+

0.21+

, 0.21+

0.21+

88

Block End Instructions

Instruc-

Address

Instruc-

Address

Description

Length

in

Block End Instructions

Length

tion

BE End block 1 4.0 2.4 1.6 1.62 BEU End block unconditionally 1 4.0 2.4 1.6 1.62 Status word for: BE, BEU BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – – – Instruction affects: – – – – 0 0 1 – 0

BEC End block conditionally if

Status word for: BEC BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – Yes – Instruction affects: – – – – Yes 0 1 1 0

1)

If jump is not executed

S7-400 Instruction List A5E00267845-01

ID

RLO = “1”

Words

CPU 412 CPU 414 CPU 416 CPU 417

4.2

1)

0.5

Execution Time in s

2.52

0.3

1)

1.78

0.2

1)

1.68

0.18

1)

89

Exchanging Shared Data Block and Instance Data Block

Instruc-

Address

Instruc-

Address

Description

Length

in

Exchanging Shared Data Block and Instance Data Block

Exchanging the two current data blocks. The current shared data block becomes the current instance data block, and vice versa. The status word is not affected.

tion

CDB Exchange shared data block and

S7-400 Instruction List A5E00267845-01

ID

instance data block

Length

Words

1 0.2 0.12 0.08 0.06

CPU 412 CPU 414 CPU 416 CPU 417

Execution Time in s

90

Jump Instructions

Instruc-

Address

Instruc-

Address

Description

Length

in

Jumping as a function of conditions.

Jump Instructions

Execution Time in s

tion

Length

ID

Words

CPU 412 CPU 414 CPU 416 CPU 417

JU LABEL Jump unconditionally 2 0.6 0.36 0.24 0.21 Status word for: JU BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – – – Instruction affects: – – – – – – – – –

JC LABEL Jump if RLO = “1” 2 0.6; 0.125 JCN LABEL Jump if RLO = “0” 2 0.6/0.125

2)

0.36; 0.075

0.36/0.075

2)

0.24; 0.05

0.24/0.05

2)

Status word for: JC, JCN BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – Yes – Instruction affects: – – – – – 0 1 1 0

2)

If jump is not executed

S7-400 Instruction List A5E00267845-01

0.21; 0.042

0.21/0.042

2)

91

Jump Instructions, continued

Instruc-

Address

Instruc-

Address

Description

in

Jump Instructions

tion

ID

JCB LABEL Jump if RLO = “1”.

Length

Words

CPU 412 CPU 414 CPU 416 CPU 417

2 0.6/0.125

2)

Execution Time in s

0.36/0.075

2)

0.24/0.05

2)

0.21/0.042

Save the RLO in the BR bit

JNB LABEL Jump if RLO = “0”.

2 0.6/0.125

2)

0.36/0.075

2)

0.24/0.05

2)

0.21/0.042

Save the RLO in the BR bit Status word for: JCB, JNB BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – Yes – Instruction affects: Yes – – – – 0 1 1 0

JBI LABEL Jump if BR = “1” 2 0.6/0.125 JNBI LABEL Jump if BR = “0” 2 0.6/0.125

2)

0.36/0.075

2)

0.24/0.05

2)

0.21/0.042

0.21/0.042 Status word for: JBI, JNBI BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: Yes – – – – – – – – Instruction affects: – – – – – 0 1 – 0

2)

If jump is not executed

2)

S7-400 Instruction List A5E00267845-01

92

Jump Instructions, continued

Instruc-

Address

Instruc-

Address

Description

in

Jump Instructions

tion

ID

JO LABEL Jump on stored overflow

Length

Words

CPU 412 CPU 414 CPU 416 CPU 417

2 0.6; 0.125

Execution Time in s

2)

0.36; 0.075

2)

0.24; 0.05

2)

(OV = “1”) Status word for: JO BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – Yes – – – – – Instruction affects: – – – – – – – – –

JOS LABEL Jump on stored overflow

2 0.6/0.125

2)

0.36/0.075

2)

0.24/0.05

2)

(OS = “1”) Status word for: JOS BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – Yes – – – – Instruction affects: – – – – 0 – – – –

2)

If jump is not executed

S7-400 Instruction List A5E00267845-01

0.21; 0.042

0.21/0.042

2)

93

Jump Instructions, continued

Instruc-

Address

Instruc-

Address

Description

in

Jump Instructions

tion

ID

JUO LABEL Jump if “unordered math

Length

Words

CPU 412 CPU 414 CPU 416 CPU 417

2 0.6/0.125

2)

Execution Time in s

0.36/0.075

2)

0.24/0.05

2)

instruction” (CC1=1 and CC0=1)

JZ LABEL Jump if result = 0

2 0.6; 0.125

2)

0.36; 0.075

2)

0.24; 0.05

2)

(CC1=0 and CC0=0)

JP LABEL Jump if result > 0

2 0.6; 0.125

2)

0.36; 0.075

2)

0.24; 0.05

2)

(CC1=1 and CC0=0)

JM LABEL Jump if result < 0

2 0.6; 0.125

2)

0.36; 0.075

2)

0.24; 0.05

2)

(CC1=0 and CC0=1)

JN LABEL

Jump if result 0 0 (CC1=1 and

2 0.6; 0.125

2)

0.36; 0.075

2)

0.24; 0.05

2)

CC0=0) or (CC1=0 and CC0=1)

Status word for: JUO, JZ, JP, JM,

BR CC1 CC0 OV OS OR STA RLO /FC

JN,

Instruction evaluates: – Yes Yes – – – – – – Instruction affects: – – – – – – – – –

2)

If jump is not executed

S7-400 Instruction List A5E00267845-01

0.21/0.042

0.24; 0.05

2)

94

Jump Instructions

Instruc-

Address

Instruc-

Address

Description

in

tion

ID

JMZ LABEL

Jump if result v 0 (CC1=0 and

Length

Words

CPU 412 CPU 414 CPU 416 CPU 417

2 0.6/0.125 2)0.36/0.075

Execution Time in s

2)

0.24/0.05

2)

0.21/0.042

CC0=1) or (CC1=0 and CC0=0)

JPZ LABEL

Jump if result w 0 (CC1=1 and

2 0.6/0.125

2)

0.36/0.075

2)

0.24/0.05

2)

0.21/0.042

CC0=0) or (CC1=0 and CC0=0)

Status word for: JUO, JZ, JP, JM,

BR CC1 CC0 OV OS OR STA RLO /FC

JN, JMZ, JPZ

Instruction evaluates: – Yes Yes – – – – – – Instruction affects: – – – – – – – – –

2)

If jump is not executed

S7-400 Instruction List A5E00267845-01

95

Jump Instructions

Instruc-

Address

Instruc-

Address

Description

in

Jump Instructions, continued

Length

tion

JL LABEL Jump distributor

LOOP LABEL Decrement ACCU1-L and jump if

Status word for: JL, LOOP BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – – – Instruction affects: – – – – – – – – –

1)

If jump is not executed

ID

This instruction is followed by a list of jump instructions. The address identifier is a jump label to subsequent instructions in this list. ACCU1-LL contains the number of the jump instruction to be executed (max. 254). The number of the first jump instruction is 0.

ACCU1-L 0 0 (loop programming)

Words

2 0.7 0.42 0.28 0.24

2 0.6/0.125 1)0.36/0.075

CPU 412 CPU 414 CPU 416 CPU 417

Execution Time in s

1)

0.24/0.05

1)

0.21/0.042

1)

S7-400 Instruction List A5E00267845-01

96

Instructions for the Master Control Relay (MCR)

Instruc-

Address

Instruc-

Address

Description

Length

in

Instructions for the Master Control Relay (MCR)

MCR=1³MCR is deactivated MCR=0³MCR is activated; “T” and “=” instructions write zeros to the

corresponding address identifiers if RLO = “0”; “S” and ”R” instructions leave the memory contents unchanged.

Length

tion

MCR( Open an MCR zone.

Status word for: MCR( CC1 BR CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – Yes – Instruction affects: – – – – – 0 1 – 0

)MCR Close an MCR zone.

Status word for: )MCR BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – – – Instruction affects: – – – – – 0 1 – 0

S7-400 Instruction List A5E00267845-01

ID

Save the RLO to the MCR stack.

Pop an entry off the MCR stack.

Words

1 0.1 0.06 0.04 0.03

CPU 412 CPU 414 CPU 416 CPU 417

Execution Time in s

97

Instructions for the Master Control Relay (MCR)

Instruc-

Address

Instruc-

Address

Description

Length

in

Instructions for the Master Control Relay (MCR), continued

Length

tion

MCRA Activate the MCR 1 0.1 0.06 0.04 0.03 MCRD Deactivate the MCR 1 0.1 0.06 0.04 0.03 Status word for: MCRA, MCRD BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: – – – – – – – – – Instruction affects: – – – – – – – – –

S7-400 Instruction List A5E00267845-01

ID

Words

CPU 412 CPU 414 CPU 416 CPU 417

Execution Time in s

98

Siemens CPU 412-2, CPU 414-2, CPU 412, CPU 414-3, CPU 414 Instruction Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

Applicability

Address Identifier and Parameter Ranges

Address Identifier and Parameter Ranges, continued

Address Identifier and Parameter Ranges, continued

Constants and Ranges

Abbreviations and Mnemonics

Abbreviations and Mnemonics, continued

Registers

Examples of Addressing

Examples of Addressing, continued

Examples of how to calculate the pointer

Execution Times with Indirect Addressing1

Examples of Calculations

List of Instructions

Bit Logic Instructions

Bit Logic Instructions, continued

Bit Logic Instructions, continued

Bit Logic Instructions with Parenthetical Expressions

Bit Logic Instructions with Parenthetical Expressions, continued

ORing of AND Instructions

Logic Instructions with Timers and Counters

Logic Instructions with Timers and Counters, continued

Word Logic Instructions with the Contents of Accumulator 1

Word Logic Instructions with the Contents of Accumulator 1, continued

Evaluating Conditions Using AND, OR and EXCLUSIVE OR

Evaluating Conditions Using AND, OR and EXCLUSIVE OR, continued

Evaluating Conditions Using AND, OR and EXCLUSIVE OR, continued

Edge-Triggered Instructions

Setting/Resetting Bit Addresses

Setting/Resetting Bit Addresses, continued

Instructions Directly Affecting the RLO

Timer Instructions

Timer Instructions, continued

Timer Instructions, continued

Counter Instructions

Counter Instructions, continued

Load Instructions

Load Instructions, continued

Load Instructions, continued

Load Instructions, continued

Load Instructions, continued

Load Instructions, continued

Load Instructions for Timers and Counters

Transfer Instructions

Transfer Instructions, continued

Transfer Instructions, continued

Load and Transfer Instructions for Address Registers

Load and Transfer Instructions forAddress Registers, continued

Load and Transfer Instructions for the Status Word

Load Instructions for DB Number and DB Length

Integer Math (16 Bits)

Integer Math (32 Bits)

Floating-Point Math (32 Bits)

Floating-Point Math (32 Bits), continued

Square Root and Square Instructions (32 Bits)

Logarithmic Function (32 Bits)

Trigonometrical Functions (32 Bits)

Adding Constants

Adding Using Address Registers

Comparison Instructions (16-Bit Integers)

Comparison Instructions (32-Bit Integers)

Comparison Instructions (32-Bit Real Numbers)

Shift Instructions

Shift Instructions, continued

Rotate Instructions

Rotate Instructions, continued

Accumulator Transfer Instructions, Incrementing and Decrementing

Accumulator Transfer Instructions, Incrementing and Decrementing, continued

Program Display and Null Operation Instructions

Data Type Conversion Instructions

Data Type Conversion Instructions, continued

Data Type Conversion Instructions, continued

Forming the Ones and Twos Complements

Block Call Instructions

Block Call Instructions, continued