Page 1
Silicon N-Channel MOSFET Tetrode
• For low-noise, gain-controlled input stages up to 1GHz
• Operating voltage 12V
• Integrated bias network
ESD: Electrostatic discharge sensitive device, observe handling precaution!
BF 1012
Type Marking Ordering Code PIN Configuration Package
BF 1012 MYs Q62702-F1487 1 = S 2 = D 3 = G2 4 = G1 SOT-143
Maximum Ratings
Parameter Symbol Values Unit
Drain-source voltage
Continuos drain current
Gate 1/gate 2 peak source current ±
Gate 1 (external biasing) +
Total power dissipation,
T
≤ 76°C
S
Storage temperature
Channel temperature
V
DS
I
D
I
G1/2SM
V
G1SE
P
tot
T
stg
T
ch
16 V
25 mA
10
3 V
200 mW
- 55 ... + 150 °C
150
Thermal Resistance
Channel - soldering point
Semiconductor Group
R
thchs
≤
370 K/W
1 Jul-29-1996
Page 2
BF 1012
Electrical Characteristics at TA = 25°C, unless otherwise specified
Parameter Symbol Values Unit
min. typ. max.
DC Characteristics
Drain-source breakdown voltage
I
= 300 µA, -
D
V
G1S
= 4 V, -
V
G2S
= 4 V
Gate 1 - source breakdown voltage
+
I
= 10 mA,
G1S
V
G2S
= 0 V,
V
DS
= 0 V
Gate 2 source breakdown voltage
±
I
= 10 mA,
G2S
V
G1S
= 0 ,
V
DS
= 0
Gate 1 source current
V
G1S
= 6 V,
V
G2S
= 0 V
Gate 2 source leakage current
±
V
G2S
= 8 V,
V
G1S
= 0 ,
V
DS
= 0
Drain current
V
= 12 V,
DS
V
G1S
= 0 ,
V
G2S
= 6 V
Operating current (selfbiased)
V
= 12 V,
DS
V
G2S
= 6 V
Gate 2-source pinch-off voltage
V
(BR)DS
+
V
(BR)G1SS
±
V
(BR)G2SS
+
I
G1SS
±
I
G2SS
I
DSS
I
DSO
V
G2S(p
V
16 - -
8 - 12
10 - 16
µA
- - 60
nA
- - 50
µA
- - 500
mA
8 10 -
)
V
V
= 12 V,
DS
I
= 100 µA
D
AC Characteristics
Forward transconductance (self biased)
V
= 12 V,
DS
V
= 6 V, f = 1 kHz
G2S
Gate 1-input capacitance (self biased)
V
= 12 V,
DS
V
= 6 V, f = 1 MHz
G2S
Output capacitance (self biased)
V
= 12 V,
DS
V
= 6 V, f = 1 MHz
G2S
Power gain (self biased)
V
= 12 V,
DS
V
= 6 V, f = 800 MHz
G2S
Noise figure (self biased)
V
= 12 V,
DS
V
= 6 V, f = 800 MHz
G2S
Gain control range (self biased)
V
= 12 V,
DS
V
= 1 V, f = 800 MHz
G2S
g
C
C
G
F
∆
fs
g1ss
dss
ps
800
G
ps
- 0.9 -
mS
- 24 pF
- 2.1 2.5
- 0.9 dB
- 22 -
- 1.4 -
40 50 -
Semiconductor Group
2 Jul-29-1996
Page 3
Total power dissipation
P
tot
= f (
BF 1012
T
)
S
Drain current
I
D
= f (
V
G2S
)
300
mW
260
240
T
S
220
200
180
160
140
120
100
80
60
40
20
0
0 20 40 60 80 100 120 °C 150
Insertion power gain
11
mA
I
D
P
tot
9
8
7
6
5
4
3
2
1
0
0.0 1.0 2.0 3.0 4.0 V 6.0
V
G2S
Forward transfer admittance
|
S
|2 = f (
21
f = 800MHz
10
dB
0
| S21|2
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
0.0 1.0 2.0 3.0 4.0 V 6.0
V
G2S
)
|
Y
| = f (
21
V
G2S
)
24
mS
| Y21 |
V
G2S
20
18
16
14
12
10
8
6
4
2
0
0.0 1.0 2.0 3.0 4.0 V 6.0
V
G2S
Semiconductor Group
3 Jul-29-1996
Page 4
BF 1012
Gate 1 input capacitance
f=1MHz
3.0
pF
2.6
g1ss
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0.0 1.0 2.0 3.0 4.0 V 6.0
C
C
g1ss
= f (
V
g2s
)
Output capacitance
C
dss
= f (
V
G2
)
f=1MHz
3.0
pF
2.6
dss
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0.0 1.0 2.0 3.0 4.0 V 6.0
V
G2S
C
V
G2S
Semiconductor Group 4 Jul-29-1996
Page 5
BF 1012
Package
Semiconductor Group
5 Jul-29-1996
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