Sharp QD101MM Schematic

QD-101MM

SERVICE MANUAL

SZ545QD-101MM

TFT DISPLAY UNIT

MODEL QD-101MM

• In the interests of user-safety the set should be restored to it's
original condition and only parts identical to those specified be
used.

CONTENTS

1. INTRODUCTION .........................................................................1

2. SPECIFICATIONS.......................................................................2

3. ADJUSTMENT OF PWB.............................................................5

4. CIRCUIT DESCRIPTION.............................................................8

5. TROUBLESHOOTING CHART.................................................21

6. CIRCUIT DIAGRAM & PWB.....................................................38

7. REPLACEMENT PARTS LIST.................................................54

8. ASSEMBLY DRAWINGS .........................................................60

9. INFORMATION..........................................................................64

SHARP CORPORATION

1. INTRODUCTION

The QD-101MM is a liquid crystal display monitor.
It employs a high contrast, high response, 10.4-inch TFT liquid crystal display panel,which can
generate a maximum of 16,000,000 different colors. It offers a computer graphic screen which
responds in real time.
Moreover, the built-in composite video circuit and audio circuit can receive video signals of
VCR, laser disc.
Their controls and images can be adjusted with the main-body's buttons referring to the menu
screen.
This monitor also has a speaker to monitor audio signal.
In addition, an external control terminal has been provided to facilitate control of the display
unit's functions.
The power source is an external AC adaptor that provides 12V DC to display monitor unit.

This unit can be used with the following models and signals.

1.Personal computers

1) IBM, PC/XT, PC/AT, PS/2, PS/1, PS/55, Think Pad 700

2) Apple, MACII, MAC+/SE, MACIIcx, MACIIci, MACIIsi, MAC LC,
Power Book 160/180, Quadra

3) AT&T, PC6300WGS

4) SHARP, AX286/386

2.Video adaptors and signals

1) IBM, MDA(720X350)

2) IBM, CGA(640X200)

3) IBM, EGA(640X350)

4) IBM, MCGA(640X400, 640X480)

5) IBM, VGA(640X350, 640X400, 640X480, 720X400)

6) Apple, MACII Video Card (640X480)

7) Apple, MAC LC (640X480, 512X384)

8) Hercules, Graphic Card/Plus/Incolor Card (720X348, 720X350)

9) Composite video signals (PAL/NTSC/SECAM)

1

2. SPECIFICATIONS

1.SPECIFICATIONS OF MAIN BODY

1.Display unit :10.4-inch TFT color LCD
(Amolphous silicone active matrix type : a Si TFT)

2.Display color :Approx.16,000,000 colors

3.Display area :211.2(W)X158.4(H)mm

4.Number of pixels :640X(RGB)X480 pixels (pixel = R+G+B dots)

5.Input video signal :TTL level R,G,B,r,g,b, Hsync, Vsync

TTL level R,G,B,I,Hsync, Vsync
TTL level Video, I, Hsync, Vsync
Analog IBM PS/2 type VGA signal
Analog Apple Macintosh II video card signal
Composite / S video signal (NTSC/PAL/SECAM)

6. Input connector :15-pin computer signal input connector (1)

Composite video input connector (1)
S-terminal video signal input connector(1)
Audio input connector (1)
12V DC input socket (1)

7. Switches and others :Power switch

MENU button (1), SELECT button (1),
UP button(1), DOWN button (1), RESET button (1)

8. Adjustment :Color adjustment, Brightness adjustment, Tint adjustment

Contrast adjustment, Audio level adjustment
Image horizontal/vertical position adjustment
Phase adjustment, Frequency adjustment

9. Functions Software reset

Freeze function
Input video signal auto-discrimination function
Menu screen control
Built-in speaker(1W)X1

10. Outside dimensions :280(W)X208(H)X47(D) [mm]

(11.0(W)X8.2(H)X1.9(D) [inches])

11. Weight :Approx. 1.3kg (main body alone)

(Approx.2.86lbs(main body alone))

12. Backlight :Fluorescent lamp

(cold-cathode Fluorescent X1)

2

2.SPECIFICATIONS OF INTERFACE

2.1.Computer signal input section

Signal layout

Pin No. Analog Signal Digital Signal

1 Analog Red N.C.
2 Analog Green Digital Green
3 Analog Blue Digital Blue
4 N.C. Digital Secondary Red(r)
5 N.C. Digital Red
6 Analog Red Return Digital Red Return(GND)
7 Analog Green Return Digital Green Return(GND)
8 Analog Blue Return Digital Blue Return(GND)

9 Test 1(Macintosh) N.C.
10 Test 2(GND) Test 2(N.C.)
11 GND GND
12 N.C. Digital Secondary Green(g,I)
13 Hsync/Csync Hsync
14 Vsync Vsync
15 N.C. Digital Secondary Blue(b.Video)

12345

678910

1112131415

Connector :Mini D-Sub 15-pin connector

JST EKHEY-15S-IF3P14-143
(applicable plug housing : JST KEC-15P)

Test 1 :When connecting to Apple Macintosh computer, this terminal must be

grounded.

Test 2 :This terminal must be grounded when inputting analog-type computer

signals.
Leave this terminal open(N.C.) when inputting digital computer signals.

2.2.Composite video signal input section

Connector :Pin jack (EIAJ RC-6703A)

2.3.Audio signal input section

Connector :Pin jack (EIAJ RC-6703A)

2.4.Power input section

Input pin :HEC0470-01-640 [Hoshiden Co., Ltd.] or equivalent

Center pin +
AC adaptor :Accessory AC adaptor DADP-2004PAZZ
Input voltage :DC12V (when main body is loaded)

2.5.S-terminal video signal input section

Signal layout : 1.GND

2.GND

3.Y signal

4

2

3

1

4.C signal

3

3.SPECIFICATIONS OF ENVIRONMENT

Basically, these environment specifications apply to the main body and its accessories.

Item Specification Remark

Type Single-phase 2-wire type, 1 ground line

Power

Operation

Storage

Frequency 50 / 60 Hz

Input voltage AC 100~240V

Output voltage DC 11.5 ~ 13.8V

Operating temperature 0 ~ 35 °C

Operating humidity 20 ~ 80 %RH

Storage temperature -20 ~ 60 °C

Storage humidity 20 ~ 80 %RH

Special AC adaptor accessory is
used.

Without dew condensation.
Absolute humidity shall be less
than 35 °C / 80 % RH.

4

3. ADJUSTMENT OF PWB

The QD-101MM has a Main printed-wiring board (PWB) that needs to be adjusted.
The following paragraphs describe how to adjust the Main PWB. Correct adjustments are
essential for the unit to operate properly. After repair or maintenance, it is necessary to readjust
them. Before adjusting the control block, be sure to verify that the power supply block is
adjusted, and then adjust the control block.

1. ADJUSTMENT OF POWER SUPPLY BLOCK

There are two power voltage adjusting points: VR1 for V

, VR2 for V

CPU

LCD

.

1) Connect the AC adaptor connector plug to J1.
Verify that the output of AC adaptor approximates 12V.

2) Before turning on the power switch, check the conductive pattern on the rear of the
PWB for defects or foreign material that may short the conductive paths.

3) Turn on the power switch SW1 to verify that the LED lights.

4) V

adjustment

CPU

Connect the + lead of DC voltmeter to TP203, and the - lead to TP206.
While turning VR1 with a flat-tipped screwdriver, observe the voltmeter.
Adjust the voltage to 5.15 ±0.05V.

5) VCC voltage check
Connect the + lead of the DC voltmeter to TP202. Verify the voltage of 4.90 to 5.15V.

6) V

adjustment

LCD

Connect the + lead of the DC voltmeter to TP200.
While turning VR2 with a flat-tipped screwdriver, observe the voltmeter.
Adjust the voltage to 5.05 ±0.05V.

7) +10V voltage check
Connect the + lead of the DC voltmeter to TP204. Verify the voltage of 10±0.5V.

2.ADJUSTMENT OF CONTROL BLOCK

2.1.Offset adjustment of computer signal input amplifier

1) Turn off the power, and connect TP10 and TP303 to the DC voltmeter.
(Connect the earth terminal of the probe to TP10.)

2) Input the signal of Fig. 1-B to J2.

3) Turn on the power. Observing the DC voltmeter, adjust the TP303 level to 1.15±0.05V
by turning VR303 with the flat-tipped screwdriver.

2.2.Gain adjustment of computer signal input amplifier

1) Turn off the power, and connect TP303 and TP300 to an oscilloscope.
(Connect the earth terminal of the probe to TP10.)

2) Input the signal of Fig. 1-C to J2.

3) Turn on the power. Observing the oscilloscope, adjust the TP303 level to be equal
to TP300 level by turning VR300 with the flat-tipped screwdriver.
(Output voltage is approx.3.8V at TP300.)

4) Turn off the power, and reconnect the probe from TP303 to TP304.

5) Turn on the power. Observing the oscilloscope, adjust the TP304 level to be equal
to TP300 level by turning VR301 with the flat-tipped screwdriver.

6) Turn off the power, and reconnect the probe from T304 to TP305.

5

7) Turn on the power. Observing the oscilloscope, adjust the TP305 level to be equal
to TP300 level by turning VR302 with the flat-tipped screwdriver.

2.3.VCO adjustment

1) Connect the + lead of the DC voltmeter to TP207, and the - lead to TP10.

2) Input the video timing of Fig. 1-A to J2.

3) After turning on the power, leave it as it is for approx. 3 minutes.
Then turn L200 with ceramic driver to adjust the voltage of TP207 to 2.5±0.2V. (*1)

4) Input the video timing of Fig. 1-B or C to J2 .

5) Then turn L201 with ceramic driver to adjust the voltage of TP207 to 4.1±0.05V. (*2)
(*1) Since the voltage of TP207 varies depending on the material of the driver used,

keep the driver away from the core when checking the voltage.

(*2) It is factory-adjusted at the timing of PC9801 640X400 at shipment.

2.4.Audio speaker level adjustment

1) Input the 1KHz, 500mV(RMS) sine wave from an oscillator to the audio signal input
terminal CN502.(The audio signal level should be adjusted when power switch of QD­ 101MM is on.)

2) Set the volume level to maximum and the audio mute switch to off.

3) Connect an effective value type AC voltmeter to TP502 and adjust the voltage of TP504
to 2.85V(RMS) by turning VR501 with the flat-tipped screw driver.

Video

Hsync

Video

Vsync

95 64 113 640dot

1H=912dot=63.696047µs

(1/H=15.699561KHz)

25 3 34 200H

1V=262H=16.688364ms

(1/V=59.92Hz)

Fig. 1-A IBM CGA 200-line 40-character

6

Video

Hsync

0V

96

1H=800dot=31.777557µs

Video

Vsync

Video

2

16 96 48

(1/H=31.468881KHz)

0V

1V=525H=16.683217ms

(1/V=59.94Hz)

Fig. 1-B IBM VGA 480-line Black-solid

0.7V

0V

640dot

Hsync

Video

Vsync

1H=800dot=31.777557µs

(1/H=31.468881kHz)

0.7V

0V

11 2 32 480H

1V=525H=16.683217ms

(1/V=59.94Hz)

Fig. 1-C IBM VGA 480-line

7

4. CIRCUIT DESCRIPTION

1. GENERAL

Circuit will be described in reference to the QD-101MM block diagram in Fig. 2.
Composite video signal which enters via pin jack connector is converted into the digital RGB
in the composite video input circuit by the control signal from the I2C bus controller. The signal
then enters the signal selector circuit.
Computer analog signal enters via the 15-pin connector and is processed through the computer
analog input circuit and the A/D conversion circuit. The signal is then converted into the digital
RGB signal and enters the signal selector circuit.
Digital video signal from IBM PC EGA or CGA enters via the 15-pin connector is input into the
signal selector circuit.
The signal selected in the signal selector circuit is written into the field memory. The writing
operation into the field memory is controlled by signals which are generated in the IC100 by
HSYNC. VSYNC. Since the LCD control is asynchronous with the computer signal, FRCK.
FRRS is generated in the IC100, and is read out at their timings.
The audio control circuit controls the audio signal input from the audio input terminal, according
to the control signal from IC100. IC400(MPU) controls IC100, IC107 (I2C bus controller) by the
key operation from SW PWB. Since control data from the key is stored into EEPROM, the set
data is memorized even if the power is turned off.

2. COMPUTER SIGNAL INPUT CIRCUIT

In addition to composite video signal, QD-101MM can receive the computer analog RGB signal
and the computer digital RGB signals of MDA, CGA, EGA. These signals enter each input
circuit via the 15-pin connector (J2), pin jack (CN600), and S-terminal(CN601). After they are
converted into the digital signals, they are input to the signal selector or directly to the signal
selector circuit.
Refer to MAIN CIRCUIT No.3.

2.1.Computer digital signal input circuit

The computer digital signal is input to Pins 2, 3, 4, 5, 12 and 15 of J2, and is directly sent to the
signal selector.
EGA outputs the video signal at the 6-bit TTL level. (R, G, B, r, g, b)
CGA outputs the video signal at the 4-bit TTL level. (R, G, B ,I)
MDA outputs the video signal at the 2-bit TTL level. (Mono, Video, I)
As basic, the pins of J2 output the following signals.

Table 1

Connector J2's Pin Number

Signal

12 15 4 2 5 3 14 13 11

EGA g b r G R B Vsync Hsync GND

CGA I x x G R B Vsync Hsync GND

MDA I MONO x x x x Vsync Hsync GND

x:Don`t care or N.C.

8

AC

J1

DC INPUT

HV

IC400

MPU

GATE ARRAY IC100

DATA REGISTER

IC108,111

VRAM

FIELD

MEMORY

WRITE

CONTROLLER

TFT COLOR LCD UNIT

MENU

CONTROLLER

MASK

CONTROLLER

COLOR

CONTROLLER

INVERTER PWB

OSC1,2

POWER SUPPLY

+10V VLCD AVCC DVCCVCPU

LCD CONTROLLER

FIELD MEMORY READ CONTROLLER

Fig. 2 QD-101MM Block Diagram

SW

CIRCUIT

IC413,414

2

E PROM

IC107

2

I C BUS

CONTROLLER

IC202,203

IC315~317

IC300~302

A/D

COMPUTER

J2

PDB

VCOIN

PLL

CLK

CONVERSION

CIRCUIT

ANALOG

INPUT

CIRCUIT

RGB SIGNAL

COMPUTER ANALOG

FIELD

MEMORY

IC103~105

SELECTOR

SIGNAL

IC600,601

J2

RGB SIGNAL

COMPUTER DIGITAL

IC308~313

COMPOSITE

VIDEO

INPUT

CIRCUIT

CN600

COMPOSITE

VIDEO SIGNAL

CN601

S-VIDEO

SIGNAL

CN502

SIGNAL

AUDIO INPUT

AUDIO

SP500

COTROL

CIRCUIT

SP

9

2.2.Computer analog signal input circuit

IBM computer and APPLE computer output the following analog signals at the load of 75Ω.

Table 2

Computer Analog Signal

R G B

IBM 0.7Vp-p 0.7Vp-p 0.7Vp-p

APPLE 0.7Vp-p

1.0Vp-p

(Synchronization signal

overlapped)

0.7Vp-p

The signals are converted into 8-bit digital signals by the A/D converter(IC315~317).
The computer analog signals are given to Pin 21 of the A/D converter, are divided by 256
between the voltages given to Pin 18(VRT) and Pin 24(VRB), and are digitally converted.
The following table shows the reference voltage which is given to the A/D converter.

Table 3

VRT VRB

Threshold
Level

3.8V(2.8~4.8V)

Adjustment are possible

1.0V

2.3.Threshold level generation circuit

In order to convert the computer and composite analog signal into digital, it is necessary to set
the threshold level on the A/D converter. As shown in Fig. 3, VRT and VRB voltages are set
on the basis of the reference power of ZD1. VRT can be varied by key operation.
As the adjusting method from the main body, the MENU button and SELECT button are used
to display the contrast adjustment in the screen and to allow the set value to be changed with
UP and DOWN selector buttons.

Fig. 3 Threshold Level Generation Circuit

10

3.VIDEO INPUT CIRCUIT

Fig. 4 shows the block diagram. Circuit diagram is shown in VIDEO CIRCUIT.
This unit automatically switches the circuit corresponding to the composite video signals of
NTSC, PAL and SECAM. The composite video signal and S-Video signal input to the decoder
are first converted into the 8-bit digital Y,UV signal, and is output as the 8-bit digital RGB from
the RGB converter(IC601).
Horizontal sync signal CSHSYNC, vertical sync signal CSVSYNC, ODEV signal and system
clock LLC2 are simultaneously output from the decoder(IC600), and are used in the process
circuit in the rear step.
Controls of brightness, color and tint, and the initial setting of decoder and RGB converter are
sent from MPU by the I2C bus.

38,41
30

COMPOSITE VIDEO

CN600

S-VIDEO

CN601

17,19

21

DECODER

IC600
SAA7110

40

45~50
53~62

CONTROL

29
31
42
32

Y,UV

8bit

16,17,
20~25

63
64
65
26

Y,UV/RGB
CONVERTER

IC601
SAA7192

30~34,37~39
40~47
48~50,53~57

CSHSYNC
CSVSYNC
LLC2
ODEV

RGB 8bit

5,6

2

I C BUS

SDA,SCL

Fig. 4 Composite Video / S-Video Input Circuit Block Diagram

4.AUDIO INPUT CIRCUIT

Fig. 5 shows the block diagram of the audio input circuit. Circuit diagram is shown in AUDIO
CIRCUIT.
The audio signal input to the audio input terminal is inputted to the audio level controller, and
is controlled to the level which corresponds to the volume signal output from MPU.
The output enters the mute switch circuit in the next step, and the audio signal is turned on and
off corresponding to the SMUTE signal which is output from MPU.

11

SMUTE

VOLUME

PHONE JACK STEREO INPUT

CN502

SPEAKER

SP500

MUTE SW

1

2

VR501

2

CONTOROLLER

IC503
TDA1905

AMPLIFIER

AUDIO
LEVEL

IC500
TA8184F

4
5

SPEAKER
AMPLIFIER
ADJUST

7

24

Fig. 5 Audio Input Circuit Block Diagram

5. PLL CIRCUIT

The dot clock (VCOIN) is generated by the PLL circuit shown in Fig.6. The dot clock is necessary
to sample the video signal from the computer and change it into the suitable dot data.
Hsync signal from computer enters into IC100. This signal is compared frequency and phase
with the feed-back signal, which is generated from VCOIN by the phase comparator in IC100.
If any error of phase or frequency occurs between Hsync and VCOIN, LOW or HIGH level is
output at PBD of IC100, and when both frequency and phase agree with each other, high
impedance is output.
The output signal from the PDB terminal is converted into a DC voltage by a loop filter and then
controls the VCO.
To select the high band or low band, either VCO is selected according to the signals from No.
120 pin and No. 119 pin of IC100.

12

Fig.6 PLL Circuit

6. MEMORY CIRCUIT

BLOCK DIAGRAM is shown in Fig.2.

6.1.Field memory writing

When data sent from the signal selector is written into the field memory(IC103~105), FWCK
(clock slightly later than CLK) generated from the memory controller in IC100 is used.

6.2.Field memory reading

The clock (FRCK) and control signals which are generated in the field memory reading signal
generating circuit in IC100 are used to read data from the field memory.
Reading is asynchronous with writing. In the ordinary mode, data written into the field memory
are color-compensated and are sent to LCD.
In the enlargement mode, the enlargement control signal is sent to the field memory from the
field memory writing/reading signal generating circuit in IC100 to make the enlargement display
possible.

6.3.Menu, message display memory

The menu and message display is stored in the ROM area of IC400(MPU).
When the menu button is first pressed, MPU will write data and address into VRAM (IC108, 111)
via IC100. Moreover, VRAM data is read via IC100.
The data is sent to LCD at the timing of LCD.

LCD

IC108, 111

VRAM

menu and
message data

IC100

display data

ROMMPU

IC103~105

FIELD MEMORY

Fig. 8 Memory Circuit Block Diagram

13

7. VARIOUS FUNCTIONS OF IC400(H8/3256 M.P.U)

IC400 is a microcomputer which is provided with a set of 16-bit free running timer and 2
channels of SCI in addition to 48K-byte PROM/2K-byte RAM.

7.1.Key data and various functions

The keys (DOWN, UP, SELECT, MENU, RESET) provided on the main body of QD-101MM
switches and selects the adjustment mode displayed in the LCD screen as well as gives the
direct commands to IC400.

1) DOWN
This key decreases the adjustment items selected by the select key, step by step.

2) UP
Being opposite to DOWN, the key increases the adjustment item, step by step.

3) SELECT
This key is used to select the adjustment mode in the menu screen which is displayed
by the MENU key.
Every push of this key can change the adjustment item, step by step.

4) MENU
This key is used to switch the menu screen.

5) RESET
This key is used to set the initial values of the computer. When this key is pressed,
the adjustment items are all returned to the initial statuses.

7.2.EEPROM control function

The EEPROM(IC413, 414) area is provided to write the timing set values of each computer
when it is connected to QD-101MM. The timing set values are written into EEPROM under the
following four conditions.

1. All resetting

2. Resetting

3. Power turn-off

4. The connected computer is changed.

Here, writing into EEPROM is executed only when the set value is changed.

7.3.Reset circuit

The circuit diagram is shown in MAIN CURCUIT No.4.
IC407(TL7705CPS-B) detects the power voltage, V
and generates the RESET signal. If V

drops below the detection voltage (TYP4.5V) when

CPU

, of IC400 and its surrounding circuit,

CPU

the power is turned off, IC407 shifts the level of the RESET signal to “Low”.
If V
V

rises to exceed the total voltage of the detection voltage VS1 and hysteresis width

CPU

(TYP15mV), IC407 starts charging the timing capacitor(Ct) with a constant current.

HYS1

After (TP0=1.3XCtX10[S]), IC407 shifts the RESET signal to “High” level. (See Fig. 8.)
IC411(S-8054ALB) detects the power voltage VCC to generate the power OFF signal. If V

CC

drops below the detection voltage VS2 (TYP4. 15V) when the power is turned off, IC411 shifts
the power OFF detection level to “Low”.
If VCC rises beyond the total voltage of the detection voltage VS2 and hysteresis voltage V

HYS2

(TYP200mV) when the power is turned on, IC411 shifts the power OFF signal to “High” level.
(See Fig. 9.)

14

VCPU

(4.5V)

RESET

signal

VCC

(4.15V)

V

S1

PO TPO TPO

T

VHYS1

(15mV)

Fig.8

V

S2

VHYS2

(200mV)

POWER OFF

DETECTION

signal

Fig.9

When the power is turned on, V

, VCC and V

LCD

rise. If V

CPU

exceeds VS1+V

CPU

, the RESET

HYS1

signal is shifted to “High” level at the timing shown in Fig. 10. The reset operation of IC400 is
canceled and executes the program.
When the power is turned off, the power OFF detection signal is shifted to “Low” when VCC and
V

drops sharply below VS2.

LCD

On the other hand, Vcpu is backed up by C425 (220mF) so that it can maintain 4.5V for the time
of TW after the trailing edge of the power OFF detection signal. See Fig. 11. (TW is the time
for IC400 to retreat the data to EEPROM.) If V

drops below VS1, the RESET signal level is

CPU

shifted to “Low”, and IC400 starts resetting.

15

VS1(VCPU)

S2(VCC)

V

POWER OFF

DETECTION

signal

VCPU

VCC

RESET

5.0V

VS1(4.5V)

4.0V

POWER OFF

DETECTION

signal

TPO

Fig.10

VCPU

V

S2

VCC

TW

RESET

Fig.11

16

8. LCD CONTROL CIRCUIT

LCD control signal is slower than the video signal of the computer. While the video signal is
serial data, the LCD display data is given as 4-bit parallel data for each RGB. In order to display
the bit signal of the computer in LCD, it is necessary to store the data of one screen in the
memory and read out the image data of one screen at the drive timing of LCD. To control them,
the field memory is controlled by the memory controller in IC100 as shown in the block diagram
in Fig. 2.

9. LCD UNIT

9.1.Interface signals

3 1

22 20 18 16 14 12 10 8 6 4 2

CN1 Pin assignment

Table 4 Pin assignment of LCD unit

Pin Code Function Remark

1 GND
2 CK Sampling clock signal of data
3 Hsymc Horizontally synchronous signal (*1)
4 Vsync Vertically synchronous signal (*1)
5 GND
6 R0 Red data signal(LSB)
7 R1 Red data signal
8 R2 Red data signal

9 R3 Red data signal
10 R4 Red data signal
11 R5 Red data signal(MSB)
12 GND
13 G0 Green data signal(LSB)
14 G1 Green data signal
15 G2 Green data signal
16 G3 Green data signal
17 G4 Green data signal
18 G5 Green data signal(MSB)
19 GND
20 B0 Blue fata signal(LSB)
21 B1 Blue fata signal
22 B2 Blue fata signal
23 B3 Blue fata signal
24 B4 Blue fata signal
25 B5 Blue fata signal(MSB)
26 GND
27 ENAB Data enable signal(Horizontal display position signal) (*2)
28 Vcc +5V power suppry
29 Vcc +5V power suppry
30 TST Open
31 TST Open

24

29 27 25 23 21 19 17 15 13 11 9 7 5

31

30

28 26

The shield case is connected to GND in LCD module.
(*1) The line mode(480 or 400 or 350) can be selected by the polarity of Hsync and Vsync.

Mode 480line 400line 350line

Hsync Negative Negative Positive
Vsync Negative Positive Negative

(*2) Don't use "High".

17

9.2.Sequence circuit of LCD panel

In QD-101MM, it is necessary to conform the power ON/OFF sequence of the LCD panel as
shown Fig.12.

LCD

V

T1 T2

Signal

0 T1
0 T2

Fig. 12 Power ON/OFF sequence

Fig. 13 shows the panel sequence generation circuit.
The gate signal which has the same timing as the input signal in Fig. 12 is output by the RESET
IC of IC4 and IC5.

Fig. 13 Panel Sequence Generation Circuit

9.3.Handling the LCD panel

1. The LCD unit is assembled to very high density, do not attempt to disassemble it.

2. The polarizing plate is very easy to scratch, take extra care when handling it.

3. When cleaning the surface of the LCD panel, use absorbent cotton or soft cloth and
carefully wipe the surface.

4. The LCD panel will become discolored or stained if any moisture remains on the surface
for a long period of time.

5. The LCD panel is made of glass. If it is hit by any hard object or is dropped, it may
crack.Handle it very carefully.

6. CMOS LSI which is used in the LCD unit is very sensitive to static electricity. To prevent
damage to the LCD unit from static electricity it is necessary for all service technicians
to use a conductive mat and wrist strap to ground themselves when servicing the unit.

10.POWER CIRCUIT

The AC adaptor which is connected to QD-101MM supplies stable power to the unit, and
generates 5V power (VCC, V
power(12V).

CPU

, V

), VPP power, +10V power and the inverter circuit board

LCD

18

10.1. +5V power (VCC, V

CPU

, V

LCD

)

IC1 in Fig. 14 is a controller for a fixed frequency pulse width modulation(PWM) switching
regulator and has two constant voltage controllers. One controller is used to generate a 5V
power supply(V

CPU,VCC

) from the input power supply VIN(12VDC). The other one is for V

LCD

IC1 has a saw-tooth wave oscillator built in whose oscillating frequency is determined by
capacitor C30 connected to pin 1 and resister R29 connected to pin2. In this circuit
configuration, a saw-tooth wave of approx.75KHz is observed at pin 1 of IC1. Basically this saw­tooth wave is compared with a control signal observed at pin5 of IC1. Only while the voltage
of the saw-tooth wave is lower than the control signal voltage, the period between pin 7 of IC1
is "L" becomes longer. As a result the period between external transistor Q11 and Q10 is
conductive becomes longer. The output voltage is fed back to pin 3 of IC1. An error amplifier
in IC1 makes a comparison between the half of the reference voltage and the feed-back signal
to pin 3 and generates a control signal(pin5 of IC1). As explained above the output voltage is
stabilized by the pulse width from pin 7, which is generated by comparing the control signal with
the saw-tooth wave.
V

is adjusted to 5.1V while VCC is 5V. This is done because the load on the VCC is greater than

CPU

the load on V

and the forward voltages of D8, D9, and D10 are higher than that of D7.The

CPU

voltage supplied to pin 6 of IC1 is called a dead time control signal. It controls the maximum
ON period of the output transistor in IC1. The maximum ON period is realized on IC1 by shorting
pin 6 and pin 16.
The saw-tooth wave oscillator of pin 1 of IC1 is used also for the control of this 5V power
supply(V

). The operation of the circuit is similar to that of the other 5V power supply(V

LCD

CPU

and
VCC). The output voltage is fed back to pin 14 of IC1. The control signal is produced using a
voltage generated by dividing the reference voltage inputted to pin 13 of IC1, and the feed back
signal. The output voltage is stabilized by the pulse width from pin 10, which is generated by
comparing the control signal with the saw-tooth wave. V

is adjusted to 5.0V with VR2.

LCD

.

Fig. 14 +5V Power(VCC,V

19

CPU,VLCD

) Circuit