Sharp MZ-3500 User Manual

MZ-3500

SERVICE

PERSONAL COMPUTER

MODEL

CONTENTS

MANUAL

CODE:

OOZMZ

3500SM/E

Z-350

1.

Specifications

2.

Software (Memory) Configuration

3. CPU and

4. CRT

display

5. MFD

interface

6.

R232C interface

7.

Printer interface

8.

Other interface

9.

Power

10.

Keyboard controller

11.

Self check functions

12. IPL

flow

13.

Circuit diagram & P.W.B

Parts

1

memory

circuit

chart

list & Guide

12

25

52

72 yg

81

description

103

gy

circuit

94

7

discription

90

SHARP

CORPORATION

1-1.

Specification

Outline

of the

1)

High

speed

2)

Built

in

3)

4)

5) Model 3530

disk Model MZ3540

64 KB

LSI

DISPLAY

MFD

Other

Other functions

Software

Accessories

mini

Built

in

printer interface

Connection

monitor

Permits

units)

the use of

and 64 KB

RAM.

I/F

main

unit (Model

processing

floppy disk

of up to two

standard CP/M

incluse a single

RAM.

has two

double-side,

CPU

MEMORY

I/O

MZ353X

MZ354X

Light

pen Keyboard Printer RS232C

Speaker

(500mW) Battery backup clock HALT

FDOS

CP/M

Intstruction master

floppy

power

cord

1.

SPECIFICATIONS

35XX)

using multi-CPL'

and

RS232C

video displa,

double-side, double

density

Multi-CPU

ROM

RAM

Custom

GDC FDC PIO SIO

TIMER CLOCK Screen Elements Attribute Colors

I/F

One double floppy

Two double floppy

Dedicated keyboard

Centronics interface

No

BASIC

Utilities

Basic Expanded CP/M

Manual

disk

processing

LSI

structure

double-side,

density

disk

double-side,

density

disks

protocol,

CP/M

Aerial

interface

mitt

(separate

density

mini

floppy

IPL

C, G

For

For Shared VIDEO

RAM

Memory mapper Screen CRT

Floppy disk controller Parallel Serial Counter Clock 80 8 x

Reverse, 8

colors

2

channels (applicable

256

Built-in

asynchronus

High control commands

Expanded BACKUP,

graphic

mini

floppy

disks

and

main

CPU

sub-CPU

RAM

controller

I/O

port

I/O

port

characters

16,8x8

blink,

on

each character

bytes/sector,

interface

mode,

110 to

class

compatible

RS232C, GPIB, INIT,

display

or

overlaid display

Model double Model 3541 density

Z80A 8K 8K 64K Bit

16K Bit 16K Bit 16K B't

MPD7220 pPD765 8255

8251

8253 /iPD1990AC

x 25

lines.

80 x 20, 40 x 25. or 40 x 20

line

(horizontal, vertical)

and

CRT 640 x

16

sectors/track,

for

optional

9600

bps, half-duplex

SW

with

COPY, DEBUG,

possible

on two

3531 includes a single

density

mini

floppy double

disks,

x 2

chips chips chip chip

chips

200,

disk

side,

and 128 KB

or 8

B/W or

has two

mini

floppy

microprocessor

Byte

ROM

Byte

ROM

DRAM

x 16

SRAM

x 4

SRAM

x 1

SRAM SRAM

x 2

400,

640 x

80

tracks/disk

KILLALL

x 1

volume control

4K Bit

TH

SP6102R001

CSP-1

SP6102C002

CSP 2 SP6102C003

background color

MFD

Speaker

PC3200 BASIC, supplemented

and

GPIO

individual

double

and 128 KB

double

chips

color)

and

M 7 3500

color

side,

graphic

MZ3500

1-2. MZ-1K01 (Keyboard)

Outline

Specification

Keyboard

MZ1K02 U.S. keyboard MZ1K04

German

LSI,

1C

Keys

(98)

Interfacing

Other

Cabinet

cables

layout

specification

(ASCII)

keyboard

MZ1K05:

Keyboard CMOSIC Sculpture

Alphanumeric

For Use

Repeat

Indicators Molded Size

controller

key

Mode switch data transfer of

coiled

function

(4

(W x H

MZ1K03: U.K. keyboard (ISO).

keys

cable

LED's)

Color

xU

with

61

1

the CPU

8-pin

Automatic continuous

POWER,

French keyboard

80C49

or

8749 4049x2,4514 Mechanical contact key,

Ten key

(serial)

and

power

DIN

plug

repeat occurs 0.64 seconds after

....

depression

Alphanumeric

Office gray

467

x 35 x 190

with

15

Function

supply

. 2

of the

same key.

keys

Weight | About 1 .5kg

(transmission under

life

of

10,000,000

keys

6

operations.

Definable

15,000

Two-key rollover

(3.3

keys

baud)

Ib)

10

1-3. MZ-1U02

Outline

Specifications

Expansion Optional The

expansion

Number

of

Slot

connector.

Area

of the

Slot

for

option

Refer

unit

for the

boards

are

box

slots: 4 slots

60-pin

slot

inserting

and

to the

MZ-3500

plugged

will

accomodate

edge

option

slot

number

page

series

in to the

expansion

up to

connector

board:

(expansion RAM)

Expansion RS232C

TIN

"CIRCUIT

CPU, which

four

option

x 4

140.5

x 140

MZ-1R06

SFDI/F

GPIO GPIB

(IEEE

I/F)

can be

box.

DIAGRAM"

attached

boards.

Slot

o

o o o

1

to the

rear side

Slot2

o o o

0

of the

main

Slot

unit.

Slot

3

O

o o

4

O

0

o o

-2-

MZ3500

1-4. MZ-IR03

Outline

Specifications

Optional board It is

inserted

The

MZ-1U02

LSI

Graphic

functions

(Color

must

specified

for

dot. when

video

the

unit

is in

Software

used

through

expansion

be

each

color

use)

Screw

graphic display

the

slot

on the

box is not

GDC

Graphic

vinrn

HAM

~~~~~

—

BASIC

graphic

(1)

functions

front

required.

controller

Basic Expansion

(optional)

____WDEO

640 x 200

green

monitor

640 x 200

color

monitor

640

x 400

green

monitor

640 x 400

color

monitor

control

with

panel

(buit-in)

statements

the

Model-3500

of the PU.

RAM

series

MPD7220 16KDRAM

16KORAM

640 x 200

_____

640 x 400

^______-

SDISP ODISP CHANGE DISP GCOLOR

CLS

PSET PRESET

LINE GTABLE

CIRCLE

PAINT GINPUT GDISP GPRINT GREAD CENTER GCURSOR GSCROL SYMBOL SCALE

Expansion

CPU.

x 16

(32KB)

x 32

(64KB)

32KB

(basic)

Two

screens

One

screen

— ~"

unit

It

includes 32KB

dots

Screen

Designation Mode designation Graphic

Cleared

Dot set

Dot

reset

Line

creation Table creation Circle creation Paint over

Input

of

Display

Output

Read

of

Input

of Graphic Graphic Graphic Scren

scle-down

of

RAM.

(maximum

640 x 200

640 x 400

designation

pattern

by the

graphic pattern

of

coordinates

pattern cursor position screen symbol displaying

for two

of

output

designation

color specified.

graphic pattern graphic pattern

within

scrolling

designation

96KB

expansion)

640 x 200

Six

screens

Two

screens

Three

screens

One

screen

video units.

screen.

on

printer

the

specified

designation

dots

area

-3-

MZ3500

1-6.

MZ-1R06

Outline

Specifications

Optional board up to a

maximum

This

option

plug

LSI

Memory

and

area

user

for

memory expantion

of 256 KB.

into

the

expantion Basic Expansion

Total capacity

the

BASIC

(RAM

BASE

main

of the

box in

64KDRAM 64KDRAM

CPU RAM

SYSTEM

:

AREA

USER

'

AREA

MZ-3500

slot

1 or 3.

of

x8

(64KBI

x8

(128KB)

Main

• 57 KB

sries

CPU. with this option

CPU

only

Use

128 KB

80 KB

of

MZ-1R06

192 KB

«-

128 KB

the

main memory (RAM)

Using

eight

64K

on

theMZ-1R06

256KB

*-

208 KB

RAM's

can be

expanded

- 4 -

MZ3500

1-7.

MZ-1D07

High

Outline

Specifications

resolution

Video

Display

Input

signals

Power

Cabinet

Adjusting knobs Accessories

tube

capacity

size

supply

MZ

3500

series

Type

Fluorescent

Total

number

display

characters

220 x 145

Method Horizontal 29W

power consumpt Molded Size

(W x H x U

3

CPU

connection

12

green

monitor

Non

glare

green

color

P39

(green,

long

of

Separate

20

Color

Vertical synchronization,

2,000 (80

input,

86kHz

ion

324x310x356

cable

and

characters

TTL

Office

power

PERSISTANCE)

x 25

level

gray

contrast,

cord

and

lines)

Tilt

Size

Display capacity

Vertical

Weight

brightness

stand

12",

90"

640

horizontal

400

vertical lines

47

8 Hz

7.2kg

deflection

dots,

r

- 5-

MZ3500

1-8.

System

configuration

of

Model 3500

Keyboard

MZ-1K02 MZ-1K03 MZ-1K04 MZ-1K05

Printer

IO2824E

I I

Option

I

CE-331M

I I

'

I

MFDI

|

"Model-3541 = Model-3531 + MZ-1F03

6

Memory depending In the

paragraphs

those

four

will

on the

states.

be

operated under

hardware

to

follow,

MAIN

2.

SOFTWARE (MEMORY) CONFIGURATION

four

states

of

and

software configurations.

description

CPU

will

SDO ~ SD3,

be

made

for

2-1.

SDO

can

system

for

SD1, SD2.

(INITIALIZE

only

exist executes thus loaded

IPL

and

immediately after power

under this

will

automatically

SD3.

SUB

CPU

STATE)

condition

assign

MZ3500

on, and the

and

that

the

memory

area

MAS MA2

MAI MAO

FFFF

cooo

BFFF

8000

7FFF

0

0 0

RAMA

0 0 0

1

V

RAMA

1

1 1

FFFF

T

?

IRAM(COM^

1

jOO1——

reoo

^\

MS1

= ° (D

MSO

= 0 (L)

\\

u

\\

N

v

V

\

ROM

(SPAPE)

4000 3FFF

2000

OFFF

0000

i

|

ROME

[

I

I '

ROM

JPL

4000

(COM)

IPL

27FF 2000

1

FFF

0000

RAM

ROM

*7

M 7.

3500

Operational

(1)

Upon

reset contents starting applied

TIMING

description

after

of the

at

address

to the

OF

Vtc-

SYSKES-

SKES-

jJSUB

pr)WF PO*E

MAIN

START

Memory

1.

2. The

3.

Map

Data:

ROM-B

is

tested

ROM-IPL functions under

at

first,

but

later

the IPL

program

RAM-COM

is

shared

CPU.

INITIALIZE

power

initial

program

4000H,

sub-CPU.

RESET

SIGNAL

CPU

^

START

CPU

to

determine

it

functions under

has

been

by

both

FLOW

«T

on, the

main

loader

(IPL)

during which time

if

ROM's

control

are

of the

the

loaded

in

RAM.

the

main

CPU and the

ABT

CPU

loads

the

into

RAM

reset

present.

main

CPU

sub-CPU after

sub-

is

POWER

OFF

(2)

The

main

and

starts

IPL is

assigned

(3)

The

main

to

SD1,

and

disk.

Signal

generated

CR

network

Output

a.

Main

CPU

b.

Main

CPU IPL

4.

Memories

under

5.

Bank

other

the SDO

select, MAO~MA3,

ofCOOOH-FFFFH.

CPU the

CPU

starts

signal

reset

then

sub-CPU.

to the

then

to

from

and

power supply

from

time

load time

than

described

state.

terminates

At the

sub-CPU.

send

the

load

DOS

the

main

is

used

resetting same

memory

from

CPU

port

above

within

time,

allocation

the

system

cannot

the

address

the sub CPU

the ROM

(state) floppy

be

accessed

range

MZ3500

ROM-IPL

1. An 8KB ROM for the

ROM-IPL.

2.

When

the

system

state

after

power

this

stage,

the

3. The CPU

4. The high mapper the

5.

Address

The be program

2-2.

SD1

determines system processors)

main

state

ROM-IPL

memory

used

SD1

is

loaded

starts

CPU as it

and the

0000

by the

has

(SYSTEM

mode.

(2764

or

mask

reset

signal

on, the

ROM-IPL

from

sets

goes

sub-CPU

is

addressed

of the

area

sub-CPU

been loaded

main

is

address

the

sub-CPU

out of its

starts

sub-CPU

above

there.

addressed.

OOOOIROM

by the

ROM

because

LOADING & CP/M)

which

operating

in the

CP/M

(Control

ROM

equivalent)

turns from CPU

starts

reset

initial

state

to

operate.

sub-CPU.

is ROM

address

the mam CPU

system

Program

low to

to

operate

address

signal from

via the

At

this

address

(1000)

ts in

use.

for

is

used

high

At

10000) low to

memory

point,

(0000)

cannot

initial

The

Micro-

Mam

CPU

OfFF

0800

0000

MS1

= 0( L)

MSO=l(Hj

logical

Logical

address

1

FFF

1

800

1

7FF

1

OOP

OFFF

0800 07FF

0000

address

(during

of the

ROM

physical

1

FFF

1

800

I

7FF

1

OOP

OFFF

0800 07FF

0000

IPL

operation)

sub-CPU

address

ROM IPL

r r

F?'

MAIN

r

^

CPU

RAMicnu:

\

>

\

x

\

V

4

\

^ \

3

\ \

\

\ \

\

\ \ \

\ \

RAM sn

RAM SA

KAM«.(IH) 2000

1FFF

\

\ \ \

i

f. ft f

n

- 9 -

MZ3500

Operational

(1)

As

soon

port

and main CPU. is

the

(2)

As the

Communication

description

as the

sub-CPU

waits

for

program transfer (IOCS)

This

IOCS

program resident

main

CPU

loads

is

started,

(Input at

address

the

between

it

initializes

Output

Control

4000H-5FFFH.

information

Main

and SUB CPU

from

the I/O

the

System)

sector

(3) (4)

"1" of

track

"0" of the

and

bootstrap routine

The

bootstrap program

The

bootstrap program determines

BUSRQ

to the

H

OUTPUT

|

(ISOLATION

floppy

sub-CPU.

is

loaded next.

disk,

rnemory

OF COM

it

loads

the

IOCS

allocation.

RAM)

2:3.

SD2

SD2 is

MA2

BANK SELECT

(ROM based BASIC)

active when

MAS

MAI 0 0

MAO

FFFF

Sffi

"SHARP

00

0000

° °

00.1 1100

01

0101

1

III

R\MA KAMB

i

4

1

1, 2, 3| 4

3

i

\

IFF? IFF?

0000

(MO2

MO1 MOO

2

ROME

ROMC ROMU ROM!

J

ROMA

0

0001

00110

01010

BASIC"

is

executed

ROM 2

via

MAIN

ROM.

CPU

0

1

I

0

1 1

0 1 1

1

0 0 I 0 0 1

0 1

1 1

1

K

\M L

2| 3, 4

MS]

= I (H)

MSO

= 0 Li

1 I 1

0 0 1

1 I 0

0 1 0

1

1 1

KAMI!

2,

3 |

1 1

SUB CPU

4

1.

Bank

select, MAO~MA3.

2.

Bank

select, MOO~MA2,

is

effective

is

effective

for

memory

for

memory

area

COOOH-FFF

area

2000H-3FFFH

-

10

FH.

-

2-4.

SD3 is "SHARP

RAM

BANK

SELECT

SD3

(RAM based BASIC)

active

when "SHARP BASIC"

BASIC"

MAS MA2 MAI

MAO

Ffft

gFFF

is

loaded

0000 0000

0011 001) 0011 0101 0101 0101

III III III

\

1

2,3,4

-

, \ ,

RAMA

1FFF

ROM

0000

]L

in RAM

from

MAIN

0000 III! 1111

RAMB

RANC

1,2,3,4 1,2,3,4

ROM!

ROM2

is

ececuted

the

CPU

via

RAM.

floppy

disk.

MSO

0000

lRwnuf

KAMI)

KOM3

K(IM4

\\ ROM BAS

MSI

= 1< H)

= HH) SUB CPU

1

r

%

\\

v

\\

\

\v

\\

N\

v

x

\\

RAN.

\\

RAN

RAM

MZ3500

1

SP

SC

SB

k

' SUB CPU

1 PI

KU

"°

M02

ROM

BANK

SELECT

000 0 ) i ]

[NOI

0

0 1 " 1 0 0 1

MOO

010

1.

Bank select, MAO-MA3.

2.

Bank select, MOO-MO2,

Operational description

The

state

of the

system

program

before

the

load

10 1 0

is

effective

for for

by the

memory memory

bootstrap

is

determined

of the

is

system

effective

program.

area

COOOH-FFFFH.

area

2000H-3FFFH.

3-1.

Block

1)

Relation between

main

diagram

memory.

MMR

(Main Memory Mapper)

I

JK» 2K*

and

, RAM

I

(II'TION

1

RAN

4-

'

64KBV2)

J

3. CPU AND

||

'7220

MPXR

i

(,

,APM,C

{)

MEMORY

I

RECEI

VFR

VI

°l

1

OPTION

1

.

Ml

DM1 I MO*J

OK

II K U MO* 400

kl Mil I 1 ION

si v i

(.us

1

SI CSI -2

SEMI

CUSTOM

IS!

CSI'-I

TOM

R

It

L

VIIIK1

RAM

32KB

V

1 HI O RAM

32KB

VIDH)

RAM

32KH

RS-232C

l/f

3-2.

Main

M A

I

N

C

P

u

CPU and I/O

r^

IX

—££-1

port

A6

A

M

P

A2 A3 A4

IORQ

M

i

v~\

r

C

j^

Y 1

(jtA.

Y3

G2

B

Ol Y6

Y4

Y5

74LSI38

v

"" ~s

f^-r-^r-. — r

~~>

\J>

iZ

J

\J I

-)

f\

J -\J

^

0

5 O

Connector

|~^T

1 is

I

PC

2 The

Port

select

Table

-•>

r DL

Obr

MFUC

•

\J

lUMr

IOABCMEMORY

This

paragraph select

address

decoded

signal.

below

signal

functions.

MAPPER)

discusses

and

addressing.

output

in the

describes

main

from

74LS138

address

MZ3500

CPU I/O

the

main

to

create

map and

CPU

the

ADDRESS

A7 A6 A5 A4 A3 A2 A1 AO

00000000 00000001

11011110 11011111

^^^Qooxx

^^^QO•^xx

iiiotoxx

11101

1111QOXX

1 1 1 1 0 1 X X

1 1 1 1 1 0 X X

1

1 1 1 1 1 X X

1 X. X

HEX

00 01

DE DF EO

E3 E4

E

E8

EB EC

EF FO

F3 F4

F

F8

F

FC

F

7

B

F

NOT USE

SFDC

(UPD765)

IOSF

INTR

NOT USE

MFDC (UPD765)

IOMF

IOAB

(MEMORY

MAPPER)

SFD

interface

AO

used

A1 is

"don't

SFD

interface

Interrupt

Flipflop

MFD

interface

MFD

interface

AO

used

AT

is

"don't

I/O

port

AO

and A1

FDC

chip

for RD and WR.

care".

I/O

port

signal

from

the

resetting signal.

FDC

chip

I/O

port.

for RD and WR.

care".

select

in the

memory mapper.

used

during

select.

and

DMAC chip select.

sub-CPU

select.

~W5.

to the

WR.

main

CPU.

MZ3500

3-3.

Sub CPU and I/O

SUB

CPU

port

AS6 5

ASS

2

AS4

i

AST 4_

"MT

6

*""

5

Gl

Yl

74LS138

4G

s07

J

~9

S06

Y6

_JQ

SOS ^

J

r

.Jl

Y4

SO4

12

S03 ,. -^

0

15

S°2

D

14

"SOT

D15 '*°° r MAIN

YO

*.

CKP

^ . .

HEC3

-^

1 .

CSP

......

-C*

CPU

2

\m

Shown

at the the CPU to put

address

by the

74LS138to

Shown

below select

signals.

left

is the

select

the I/O

from

the sub CPU is

create

is the

circuit

ports

the

select

address

used

by

The out

decoded

signal.

map and

AS

7654 M£X\

0000

0001

0010

0011

0100

0101

0110

0111

1000 1001

1010 1011

1100

1101 1110 1111

8

1

23456789ABCDEF

8

soo

S01

8251

S02

8253

S03

8255

S04

input port

805

S06

S07

select

NOT USE

Output

signal

to set the

main CPU.

8251

ASO

AS1, 8253

ASO

AS2 and ASS are 8255 ASO AS2 8-bit Used

AS3

CRT AS1, ASO

UPD7220

ASO

AS1,

UPD7220 ASO AS1, AS2,

Enables

SIO

chip

is

used

for

AS2,

and ASS are

counter

chip

and AS1 are

PIO

chip

and AS1 are

and ASS are

input port.

for

read.

are

"don't

control

I/O

AS2,

and ASS are

is

"don't care".

(graphic)

is

used

for

AS2,

and AS3 are

(character)

is

used

for

and AS3 are

Signal

description

flipflop

to

communication between

select.

data

control

selection.

"don't

care".

select.

used

for

programming during write.

"don't care".

select.

used

for

port/control

"don't care".

care".

port

chip

select.

used

for

write.

chip

select.

read

and

write.

"don't

care"

chip

select.

read

and

write.

"don't

care"

apply

interrupt

CPU's.

selection.

(INTO)

to the

-

18-

MZ3500

3-4. Memory mapper

1)

Block

diagram

ADDRESS

CONTROL

AO

. i. is.

DATA

DO-D7

BUS

COAB

BUS

MERQ

RFSH

RD

"WR

BUS I — \

(MMR)

A15 A14 AI3

A] AO

COAB

MKEQB

RFSH

RB

OAB

V

SP6102R-001

~L

I/O

PORT LOGIC

—

L

n

Memory

mapping

A 15

AU

logic

-

INTB

WAITB

SYSR

WAIT TIMING GENERATOR

CLK

->TO

RESET

-

19

INTERRUPT PRIORITY ENCORDER

1NTFI)

-

MZ3500

2)

Memory

mapper

Polarity

Signal

Name

(MMR)

SP6102R-001

signal

description

1

2

9

10

12

13

14

15

16

18

ST

DO

D7

A15

A13

A1

SRES

SRQ

AR13

AR15

IN

IN/OUT

IN

OUT

Main

CPU

DRAM

output

buffer

(LS244)

switching

Bidirectional main

Main

CPU

Used

in the

shared

RAM. (Address

Main

CPU

Used

in the I/O

Sub-CPU

•

After power

•

After write command (LDA-80H: OUT#FD)

This

signal

Sub-CPU

bus

•

After power

•

After write command (LDA-02H1 OUT#FC) This signal parameter

Address

signal

The

main

AR13-AR15. This

and

MSO.

CPU

data

address

bus.

memory mapping logic

address

bus.

port

select

logic

bus

request

signal.

on:

Halts

the

is

issued after transfer

request

signal.

on:

Resets

bus

is

issued

to bus of the

to the

CPU

sub-CPU

to the

address

main

signals, A 13-A

is

means

or

CPU

by

bus.

of the MMR for

of the MMR to

sub-CPU.

of the

request

sub-CPU, after

reads

the

dynamic RAM.

15,

which

the 4

main

to

sub-CPU.

message

merged

basic

CPU

strap.

(Data

bus 0 ~ 7)

address

output

for the

bus 13 ~ 15)

assign

device

number.

by the

main

CPU-

Starts

program contained

(Sub

CPU

Reset)

by the

main CPU'

the

main

CPU

status

from

(Sub

CPU

in the

memory mapping logic circuit

and

CP/M memory

writes

the

sub-CPU.

Request)

Place

maps

in the

to the

DRAM,

the

sub-CPU.

ROM-IPL.

bus

request

shared

are

made,

ROM,

to the

RAM a

to

produce

along

and

sub-CPU

command

with

MS1

BASIC

interpreter 32KB

19

20

21

R32

IOAB

SRDY

OUT

IN

Valid

Internal

Goes

low by the

Input

when

MMR I/O

of

ready

SD2 is

signal from

Chip select signal

22

23

26

27

~

30

31

ROPB

ROAB

RODS

RSAB

~

RSDB

SACK

OUT

IN

Valid

with

SDO

Chip select Valid

with

signal

SD2

"R32B (alternate choice

Row

address

select

RAS

(ROW

ADDRESS

Input

of bus

acknowledge

command

is

written

At the end of the

mask

active (Sharp

port

select

command

IN/OUT

the

issued

from

active

(initialize

for

four

chip

active (Sharp

with

signal

for the

SELECT; LINE

signal

in the

shared

command

ROM

chip

select

ROM

based

logic

signal.

#FC-#FF.

sub-CPU.

the

main

CPU to the 8KB

state).

BASIC interpreter

ROM

based

BASIC).

the

32KB

mask

main

CPU

ADDRESS

from

the

sub-CPU.

RAM

after

cycle

bus

request

signal.

BASIC). Command (LDA

(ROM

32K

select)

(Input/Output

(Sub

CPU

mask

(ROM

8KB

EPROM

ROM

chip select signal). (ROM

dynamic

RAM

SELECT)

(Row

acknowledgement

is

released

and the sub CPU

Address)

Ready) ROM.

ipl)

(A. B. C, D).

A~D

Buffer)

(block A-block

SIGNAL

address

Select)

from

02H OUT

D).

the

sub-CPU

executes

3FD)

1

the

command

/

-

20-

M 7,

3500

32

33

34

35

36

37

38

39

40

No.

Polarity

Signal

WATB

RCMB

MRQB

Name

RF1B

RF2B

ITFB

ITOB

IT1B

TT2B

IN/OUT

OUT

IN

Main

CPU

128KB

dynamic

Signal

identical

to R F 1 B For

Wait

signal

to the mam CPU

(One

wait

cycle

period)

Chip

select

the

sub-CPU

Interrupt

Memory

15

(WA|T)

signal

issued

input

from

input

from

input

from slot

request signal

RAM

applied during

from

the mam CPU to

the

UPD765

the

sub-CPU.

1 or 2.

from

the

output

option

RAM

the

memory fetch cycle

FDC

(Floppy

main

CPU.

buffer

Function

(LS244)

(RAM

select

(RAM

Disk

(Interrupt

(Memory

output

buffer

of the

the RAM

Controller).

shared

Common)

from

Request)

enable signal.

1)

2)

main CPU.

by the

Floppy)

No. 0)

No. 1, 2)

It

consists

main

of one

CPU and

clock

41

42

43

44

45

46

47

48

49

50

51

52

Write

WRB

IT3B

IN

IT4B

SEC

GND

Vcc

IN

SW1

IN

SW2

AO

RFSH

IN

SW3

IN

SW4

53

GND

IN

signal from

Interrupt

Input

from

'See

the dip

Ground

5V

supply

Input from "See

the dip

Mam CPU

Used

rn the I/O

Refresh

signal from

Input

from

•See

the dip

Ground

input

the FDD

switch

The

switch

address

the

switch

the

main CPU.

from slot

svstem

port

system

3 or 4.

(Floppy Disk Drive) assignment

description,

assignment

description,

bus

select

the

assignment

description,

provided

logic

in the MMR to

main CPU.

provided

dip

switch,

switch.

separately.

designate device

separately.

(Write)

(Interrupt

dip

switch

(Section)

(Refresh)

from

(A),

number.

No. 3, 4)

No. 1.

54

56

Input

from

the

system

FD1

55

Vcc

FD2

IN

'See

5V

supply.

Input *See

the dip

from

the dip

switch

the FDD

swi'ch

assignment

description,

assignment

description, provided

dip

switch.

provided

dip

switch (A),

separately.

No. 2.

separately.

MX

3500

60

61

62

63 64

65

66

57

58

59

No

Polarity

Signal

SYSR

COAB

RO1B

RO2B R03B

Name

FD3

GND

Vcc

RDB

CLK

IN/OUT

IN

OUT

IN

OUT

IN

System

reset

signal.

Used

to

reset

I/O

port

Input

from

the

sytem

"See

the dip

switch description, provided

Shared

RAM

select

signal.

Address

of the

shared

Select

signal

for 8KB

Valid

when

SD2 is

active (ROM

Ground

5V

supply

Select

signal

for 8KB

Valid

when

SD2 is

active (ROM

Read

signal

from

the

EAIT signal generation

in the

MMR.

assignment

RAM is

area

allocated

area

allocated

main CPU.

clock.

dip

switch.

separately.

*F800-#FFFF

to

slot

1.

based

BASIC)

to

slot

2 or 3

based

BASIC)

Function

(System

for the

(Common

and SD3

(ROM

and SD3

(ROM2,

(Read)

(Clock)

main

(RAM

Reset)

CPU

1)

3)

RAM

based

Address)

BASIC)

BASIC).

Select

signal

for 8KB

area

allocated

67

68

R04B

MPX

OUT

Valid

when

RAS/CAS High:

Row

SD2 or SD3

address

(RAM based BASIC)

switching

address Low: Column

signal

to

slot

for the

4.

main

are

active.

CPU

address

(ROM

DRAM.

4)

(Multiplex)

69

70

71

72

73

GND

CASB

GND

INTB

IN

OUT

IN

OUT

Ground

CAS

(Column

•Refresh

Ground

Not

used

Address) signal

for the RAM

only.

for the

main

CPU 64K

DRAM.

(Column

(Interrupt)

Address

Select

Buffer)

-

22

-

MAIN

CPU

I/O

PORT

IN

MEMORY

ADDKKSS

A7

A6

A5|A4|A3|A2|Al|AO

1

1 1 1 1 1 0 1

11111110

11111111

MAPPER

HEX

KI)

FE

FF

UHUS

01 DO D7

Dl

DO

1)7 D6 D5 D4 D2 Dl DO D4 D3 D2 Dl DO D7 D6 D5

1)4 D3 D2 Dl DO D7

D6

1

O

r\i IT

OUT

INI

IN

SKQB

1 1

SKI

S

MS] MSO

M<\3

MA2

MAI MAO

MO2 MOI MOO

SW4 b«3

M\2

Sttl

she

FD3 FD2

H>1

SKDY

SACK

1NP2

I

MM

IN'1'0

MF2

Mhl

SRQ

Bus

request from

Sub-CPU

Memory

Bank

reset signal

system

select

signal

define

to

memory

_J

Bank

select signal

System

FD

assign

•f>

Sub-CPU READY

•p

Sub-CPU acknowledge

Interrupt

assign

status

to

memory

switch

the mam CPU to the

area

of

COOO-FFFF.

area

of

2000-3FFF.

(SW8)

signal

M

7.3500

sob-CPU

1. All

output

signals

except

for

SRBQ

2.

Noted

with a star

rest

of

others

are

#1 I/O

port

output

the

addresses.

(

ME2->8000~BFFF

I

ME1->-4000~7FFF

When

ME1 and ME2 are in

inhibited correspond This

during memory

to

is not

true during

are

reset

to low

that

goes

high.

mark

"£" are

processed

in the

of ME1 and ME2

high state.

addresses

overlayed

addresses

SD1

mode.

level

upon

input/output

signals,

LSI.

uses

the

memory

RSAB

in

RAM-A

for MET and ME2

power

on,

and

(RASA)

that

at

is

i i -^.

"fJ~

11

" I "

H

Wait WAIT

Its

outut

Mm

t

1 H

j H

i

timing

is

issued once

M II TO t

n (i H j 1 I 1 H M 2 h

,

<|

TvfT J i\=TjTNT7

1

j X X

H 1 H | 1 H j H j H H

j H j H | H

l

FKOM

M" l

""•»

generator

is tri

state

MOI«m

"

per

01

Tisn

JM3

SI

main

in

iri T

1

T4h

IM 2

IM 1

1

X 1 1

H L

H H

I ' 1 H

L

TO

CPU

fetch

cycle.

hkoM

"-

L

1 H |

fMont

|M It

T"

H I H

1

h

HA

MZ3500

3-5.

Memory

(ROMIPL,

RAMCOM,

To

main

CPU

S-RAM) select circuit

1)

ROM-IPL

As bus (LS245) is 2Y of the the the connected address operation times.

2)

RAM-COM select

When select so put 4Y is low and low

3)

ROM-IPL

Normally, to Vcc

If A13 of the of the level. output

to low

can

ly, it

select

ROM IPL

buffers

are

set to a low

outputs

IPL-ROM input

that

level,

of the

ROM-IPL

to

1000

test

RAM COM is input

input

so as to

select

the level thru

LS139 LS147

Should

2Y of the

lebel

access

an

would

by the

turns

to low

(LS244,

enabled.

of the

S of the

1A-4A

that A15

SRD, SMRQ

to

be

S of the

level

to

LS157

are

from

are

then

(^16)

of the

Vcc,

IPL for the

IPL-ROM.

dip

switch

by the

low, SRES

selector

becomes

either

enable

by

sub-CPU

select

signal

inputs

were becomes or CE of the

LS157

read

the

address

range

from

0000

main

CPU

level after

LS367)

enable

read

to be at low

low

and

data selector

input

then

go low so

main

CPU.

by the

address

main

Switch

which

main

CPU

high,

1C

(LS157)

effective.

1Y

(WE)

to

read

or

S of the

1B-4B

are

level

so

ROM-IPL

be at low

or OE of the

ROM-IPL.

of

0000

to

OFFF, actually.

power

on

data

bus

1C

1A-4A.

main

should

or 2Y write

selector

enabled

level,

Though

to

The 3Y and

that

CE and OE

The

contents

CPU. Because

buffer

(LS367)

CPU

will

SW2BA

be ON at all

and

SACK low,

is in low

That

is, the

(OE) becomes

RAM-COM.

is

by sub

the

output

that

the

output

should

be at low

lebel

as

ROM-IPL

the

1FFF theoretical-

address

buffer

(LS157)

be at is the

the

state

out-

pulled

up

CPU.

YO

3Y

well,

the

turnde

sub-CPU

of

is

4)

RAM-COM

Y1 of the and

AS14 4B of the Y4 to low signal

If

SMRQ, point, however,

5) RAM SMRQ, to

select following these

RAMSA

RAMSB

RAMSC

RAMSD

select

by

sub-CPU

LS139

changes

and

AS15

LS157

is at low

level,

so

should

become

SRD or

it

enables

(SA,

SRD

conditions:

..

read

is

2000

to

SB, SC, SD)

(Of)

the

sub-CPU dedicated RAM, SA-SD.

chip

select

ASVi,

(address

AS11,

(address

AS11, AS12, AS13, AS14, AS15

(address

AS11, AS12, AS13, ASK,

(address

to low

are

low.

In

level

which

that

CS of the

effective.

SMRQ,

3FFF

or

AST2,

SWR is in low

(OE)

or

write (WE). Address range,

select

by

SMRQ,

signal, then becomes valid under

AS12, AS13, AS14, AST!

4000^17FF)

4800-4FFF)

5000-57FF)

5800-5FFF)

SWR

AST3,

level

when AS13

other words,

brings

RAM-COM

sub-CPU

(WE)

is at low

AS14, AS15

ASHi

the

chip

level

is

high

input

output

select

at

this

level Tne

-

24

-

4-1. Specification

Display

memory

3KB

(characit>-s!

96KB.

max

4. CRT

Ust

of

high

(graphic

DISPLAY

resolution

Option

i

CRT

Use

of

medium resolution (,RT

Character

Graphic display (option)

Merge

display

of

chracters

and

Screen

structure

Colors

32KB

96KB

Screen

graphics

structure

Programmable

Character

Attributes

type

merge

80

chrs

x 25

lines.

40

chrs

x 25

lines,

8x16

dots

With

lower

case

descenders

255

characters Alphanumencs 26

small

97

graphic

Revers, Programmable

8

colors, programmable

640 x 400

Color

designation

640 x 400

Color

designation

Color

(one frame)

Merge

any

Merge a character

and 69

characters

patterns

vertical

line,

for

dots,

B/W

dots.

B/W

graphic screen

each

for

possible

screen

80

chrs

x 20

40

chrs

x 20

symbols

blink,

horizontal line

character

for

each

(one frame) each

character

(three frames)

for

(1 to 3

with a graphic

lines lines

character

each

frames)

character

screen

8x8

dots

Blink,

revers

Programmable

640 x 200

Color designation possible

640 x 200

Color designation possible Color

(Two

for

dots,

dots.

frame)

B/W

each character.

(Two frames)

(six frames)

for

each

character

for

each character

Background color

Control

of two

independent

Control channel number

Light

pen

input

(option)

screens

Choice

of 8

Possible

to d

Separate

graphic

Possible

to

affix

Selection

of

Incorporation

Scans

coordinates

colors

aplay

on

separate

two

screens

can be

merged into

attributes

character/non-character

of two

(CRT2 only)

independent video

and

character

code

screens

screen

outut

ongind1 graphic

one

display

channels

screen

and

character

screen

Summary

Character

Screen (Characters x ines)

Color designation

Small Line Display

Frames

Screen overlay

of

video

^""~-\^

Function

^^\^^

Elements

structure

tetter

descenders

creation

memory

display

specification

Type

of

monitor

Basic Option 1 (48KB) Option

II

(96KB)

Basic Option 1 (48KB) Option

II

(96KB)

Basic

Option 1 (48KB)

Option

II

(96KB)

Characters

ASCII

8x16

8 x 20

5x14

80 x 25 80 x 20 40 x 25 40 x 20

1

One

character

one

graphic

One

character

three

graphic

mode mode

mode

O O

3KB

frame

t t

Green

Not

possible

screen

srrpens

High

resolution

monitor

Graphics

640 x 400 dot

No

Against

igain-,t

B/W

32KB

frame

1

frame

3

frames

CRT

(option)

(640

x 400

dots

Characters ASCII

8x 16 8x 20

5x14

80 x 25 80 x 20 40 x 25 40 x 20

By

character

t

O X

3KB

1

frame

t t

One

character screen against

one

graphic screen

One B/W

character

three

graphic

One

color

one

character

graphic

Table

mode)

Color

screens

screen

1

monitor

Graphics

By

32KB

*-

screen

(option)

Color

640 x 400

character

By

dot

II),96KB(II)

No

frame

1

frame

1

frame

against

Characters ASCII

8x8

8x10

5x7

80 x 25

80x20

40 x 25 40 x 20

1

frame

One

character

three

graphic

X X

3KB

(1

t t

Green

page)

screens

Medium

monitor

«-

screen

'

resolution

Graphics

640 x 200

No

3

frames

6

frames

against

(option)

B/W

16KB

frame

CRT

(640

1

frame

One B/W

three One one

x 200

dots

mode)

Color

monitor

Characters

ASCI:

8x8

8x10

5x7

80 x 25 80 x 20 40 x 25 40 x 20

By

character

t t

X X

3KB

(1

page)

t

character screen agamst

graphic

screens

color

character

graphic

screen

Graphics (option)

Color

640 x 200

By

dot

t

48KB

No

frame

1

frame

2

frames

-

screen

against

•

I

NOTE

Graphics option

1)

Character

1.1.

Screen

CRT

Character

ASCIL

Dip

switch

high

resolution/medium resolution CRT.

Display

1-2.

Character

ASCII

Graphic symbol

NOTE:

structure

used

in the mam

mode

In the

vertically together As or 7 x 7,

display

High

resolution

(640

fH = 20

(New)fV

80 x 25 80 x 25 40 x 25

40 x 20

must

structure

Elements

8x 16

8 x 20

1

Small

letter

and

line creating

functions

case

x 400

be

640 x 400

CRT

dot)

9KHz

= 47 3Hz

lines lines lines lines

unit

is

used

chosen

by

and

picture elements

Structure

5 x 14

8 x 16

descenders

are

available.

of 8 x 8 and

programming.

adjoining graphic symbols

in the

25-line mode.

for

character

structure

decision must

Medium

resolution

(640

x 200

dot)

fH = 15

7KHz

fV =

60Hz

-

to

select assignment

640 x 200

creating

are not

Structure

5x7

8x8

Elements

8x8

8x10

I

Small letter descenders and

line functions available.

8x16 picture elements,

will

of 6 x 14, 7 x 14,

be

given

on an

actual

pattern.

2)

Graphic display

(option)

(High resolution CRT) (Medium resolution CRT)

640 dot 640 dot

400 dot

Dot

pitch

Horizontal

vertical

= 1

Dot

pitch

Horizontal

vertical

= 1 : 2

CRT

joint

6x7,

dot

200

of

dot

4)

Attribute

AT1

Horizontal

AT2 AT3 AT4

5}

Screen

It

will

be of one graphic Table

1.)

In the screen screen the

character — both

to

produce image.

00

o

Three

basic

colors

B/W

Vertical

Reverse

Blink

line

Color

line

Blink

overlay

possible

to

have

character (screen

screens.

color and element

(For

mode,

other

— the one

detail

if

there

designated

colors

o

O

o

Designated

cter.

B

R

Line

G

exist

(Line played ters

an

overlaid

and a

of

overlay

are two

for a dot on the

designated

will

(Red)

color designated

character

(Blue)

O Dot

graphic

(Violet)

Q Dot

two

M7

W

Whne

for

and

character r,,uy

in the

same

may

also

on the 80

x 25

lines

screen.)

screen

that

maximum

screen,

colors

for a

character

be

merged sltorjpther

attribute

color

designated

dot.

composed color

of

Jj>i"jrn*ion:.

3500

each

element

be

consists

of

refer

in the

graphic

more

chaia-

dis-

charac

three

to

same

on

by

than

3)

Color

designation

Eight

colors

are violet, red, blue, black) Color

designation

ASCII

48K

Graph

Background

8

colors

|

96 K

for

byte

color

designation

usable

640 x 400 dot

By

(white,

character character

dot

yellow,

cyan, green,

640 x 200 dot

By

character

By

dot

By

dot

MZ

3500

6)

Screen overlay

CRT's As

there

are two

sible

to

display

video

display

and

video

two

unit

displaying

output

independent

Overlay

is

on two

channels

screens

possible

independent

it

will

be pos

on

separate

on

either

of

screens selection

(See

is

needed

preceding

for

screen

item

5) ) The

overlay

following

bit

Address

AS AS AS AS

Hex

3210

50

0000

;p

i

51

52

53

54

55

(50)

000

0010

0011

0100

0101

Data

DS

DS DS

2 1 0

1

Internal

S

gnat

of CSP

ECH1 ECH2 EAT2

SR1 SR2 SR3 SR4 SR5 SR6

BGC

B

BGC R

BGCG COLOR BODER

08/16 40/80

name

Choice

of Cho ce of Choice

of on

CRT2

Displays

on

Displays

on

Displays

on

Displays

on

Displays

on

Displays

on

[

Choice

Color mode Border

color mode

Defines

the

Defines

display digits

(0

40

digits

outputting outputting whether

(0 No 1

CRT1 CRT1 CRT1 CRT2 CRT2 CRT2

of

data

the

character

the

character

attribute

or

Yes)

the

blue elements contained

the red

elements contained

the

green elements contained

the

blue elements contained

the red

elements

the

green elements contained

background color display

in

effect

size

for the

graphic

for the

character screen

1 80

digits)

Function

screen screen

cursor

contained

RAM (0 8

on

CRT1

on

CRT2

be put on the

in the

m the

bits,

0 No 1 Yes 0 No 1 Yes frame that displayed

VRAM

1 16

bits)

;P2

56

0110

57

0111

5D

1101

NOTE Both CRT1

Output

to

CRT1

CH

( AT )

C.KA7

)

CH AI

)+(,!

Output

each

^ AT)

1

and

CRT2 must

to

each

CRT may be

CH(

(,f-

AT)

CH(Ar)+(,!

CH

(.1-

CH+GI

1

CRT2

AT)

1

possible

RA-400 V

RAM2

V

RAM1

25/20

08/16 40/80

be

high resolution CRT's (640 x 400)

possible

in the

Connection

Connection Connection 25

Defines Defines (0

in the

following

40

M

of a 400 of the 96K of

graphio

lines/20 lines switching

data

size

display digits

digits,

1 80

combination

CH

ASCII

GF

Graphic

screens

(AT)

Attached

raster

for the

digits)

screen,

bytes

GDC

graphic

with

CRT

VRAM

(0 25

RAM (0 8

character

or

medium

.

including

attribute

lines,

1 20

bits

screen

resolution CRT's

overlay

lines)

1 16

bits)

of two

'RO x

graphics

7)

ASCII

Uses 640 x 400 dots)

CG

an 8KB

MROM

dots (8x16 dots)

#OFFF

#0000

#1 FFF

contains

8x8 dot

(2K

byte)

! x 8 dot

(2K

byte)

two

patterns'

and 640 x 200

pattern

dots

For

Model

Without letter

descenders

(8x8

3200

lower-case,

series

With two

Refer

code

8 x 8 dot

kinds

of

to ROM

on

separate

format

patterns

address

information

coexist

and

data

MZ3500

#1 000

Address

and

(Example

8)

Element structure,

1)

25

of 5 x 12

line

8 x 16 dot

pattern

character

display

(4K

in

picture

dots

pattern

Element

640

mode

pattern

byte)

element

for 1 x 16

structure,

x 200 dot

With letter

elements)

and

line

character

lower-case,

(h i j)

D7| |

12

structure,

descenders

O

o

O

0

o o

ooooo ooooo

o o

0 0

o o

0 0

and

line

1)

25

line

DO

(Address)

/—

Character

\—

Line

area

X—

Area

where

640 x 400 dot

display

mode

Model 3500

.

#1000

#1001

#1002 #1003

#1004 #1005 #1006 #1007

#1008

#1009 #100A #1006 #100C #100D

#100E

.-

#100F

pattern

area

and

line

are

(Data)

#00

10

28 28 44 44

7C

44 44 44

44 00 00 00

overload

15 2

IASCD/JIS]

8

[Graphic

symbol

Without

line

12

'With

line

HL On

16th

ot the

element

case

display

HL and

to the

line

of

graphic VLare

right

of

pattern

VL

Line

In the

symbol

Both

overlaid

-

29

-

MZ3500

2)

10

20

line display mode

Graphic

Without

symbol

line

2)

20

line

20

\\NS\\\\Mi

20

display

8

ASCII

mode

With

HL On

VL

Line

e

VL

a In the

symbol display,

overlaid

j I Graphic symbol

line

18th

to the

element

does

case

to the

raster

not

of

right

join

graphic

VL is

pattern

of

9)

Cursor

Sharp

Reverse

10)

Light

Incorporates face. Accuracy:

Function:

11)

Difference

(1)

(2)

of the

pen

The

and

input

light

By

blink)

the

each

cursor:

light

Same

pen

input

pen, however,

character

as

connector

is an

seen

in

option.

Coordinates/character code

in

specification

There

are two mode (6x9 elements) ments).

In the

the

PC-3200, vertically adjacent graphic symbols

not

joint.

But, they

Model-3200

No

line

will

be

CRT

(640x200 dot).

It is

possible CRT, the

Model 3200

to

compatible

with

modes

for the

and

normal mode

will

joint

displayed

for the

display line

to

line

the

that

of

Model

graphic mode (6x8 ele-

of

25-line displaying

with

the

Model

3500

medium resolution

on the

high resolution

utilizing program

Model 3200

and its

inter-

3200

3200;

normal

of

do

Model

3500.

of

4-2.

1)

Structure

GDC1 (for

*07FF

#0000

DO-

VRAM Basic

3KB

Bit

structure

— — ______

Character

Graphic ! 48KB VRAM [ 96KB

Video

character)

2Kbit (

S-RA.M)

(ASCI

capacity

(including

VRAM

RAM

of

VRAM

#BFFF

Attribute

I

> 8

2Kbit

x4

ts-

L

of

RAM)

'

0000

-D7

1)8—Oil

Solid

line

48KB

Broken

line.

To be

the

Graphic

attibutes)

VRAM

CRT

j

640 x 400 dot

' 16 bit ,'

16

8

bu /

bit /

Graphic

word

GDC2 (for graphic)

16Kbit

xg

(G)

(D-RAM)

16Kh,t

(B)

DO-

-D7

D8-

option

added

to

comprise

96KB

option.

option

1:

option 2 96KB

640

x 200

8 bit / 8 bit /

16

bit /

16Kbit

(R)

-D15

48KB

do

i

word word

wo-d

i i t 1 1

j

i 1 1 1 1 i i

-

30-

2)

Read/write

(1)

Timing

V-RAM

from

Z 80 to

period

for

Read/write.

VRAM

display

and

H •

SYNC-

BLNK-

M 7 3500

//><-'

Range

wh°r?

GDC can

Fly

back

period

J

draw.

(2)

Timing

3)

Structure

(1)

When read/write

The buffer

that

Z-80

is

of

either

#07FF

#0000

(2)

During display

#07FF

the

Z-80

can

read/write VRAM

can

read/write VRAM when

empty

or

Full,

character VRAM

from

GDC

2KX8

ASC I I

8bi t

DO

"D7 V&

4bit

2KX8

and can be

(A)

2KX4

GDC

accessed

«-Dll

(B)

FIFO

by

refreshing characters any

during that

mode.

(A)

ASCI

I(8bit)

(

12bit

)

DO

Dl D2 D3 D4 D5 1)6 D7

the

can be

DO

display

read/write

(B)

Dl

D2

period.

within

D3

Number

one

raster

•

Blink

Reverse

(G)

Vertical

line

.

Horizontal line

of

in

(R)

(B)

#0000

12bi

t

MZ3500

4)

Graphic

1.

read/write Mode

The RAS,

The

(1)

VRAM

•

Block

Diagram

select signal

A14 and A1 5

address

640 x 200

memory

RASA, RASB

which

is

allocated

is

to

each area selected

Read/write

dots display mode

(MZIR03)

and

of

by

RASC

GDC-2.

Z-80

signal

are

generate

by

above

via the GDC

from

signal.

R

ASA ^ RAS • A14 • A15

RASB~

RAS • A14 • AlS ...

RASC

=• RAS • A14 • A15

2.

Display

mode A14 and A15 are not together.

By the

ated

by

CSP-2.

The

signal

output

signal

to VB and VR.

select:

of

08 for 200

During

RAMB the (08/16

0000 ~ 3FFF

8000 ~ BFFF

valid

DBIN

08/16 select,

signal then

and

signal

output

rasters.

displaying

4000-7FFF

RASA, RASB, RASC

from

GDC-2. 08/16 signal

after

P-5

conversion

to VB by

16 for 400

serial

rasters)

are

for

signal,

selected is

gener-

RAMA,

or

sprit

Option I #BFFF

(48K byte)

8bit

structure

+

8000

#4000

#0000

Option

II (96K 16bit

#BFFF

byte)

structure

#8000

#4000

*0000

Low

byte

G

B

8bit

High byte

R

8bit

B/W: 3 frames

1

Color: 1 frame

#3FFF

16K

A

16K

i

#0000

8bit

8bit 31,L

B/W: 6 frames Color: 2 frames

#3FFF

16K

#0000

16K

I

1

ifit.it

16bit

-

32-

(2)

640 x 400

Option

(48Kbyte) 16

Option

(96K byte)

dots display mode

I

#4000

bits

structure

II

16

bits

structure

# 3 KKK

*0000

(

BFFF

#8000

16K

#3FFF

#0000

B/W: 1 frame Color: 1 frame

i

16K

B/W: 3 frames Color: 1 frame

Color

can be

designated

sach

character.

M Z 3500

for

5)

Synchronize signal timing

(1)

For 640 x 200

Dot

2XCCLK

Horizontal display

HFP

HS

HBP

Vertical

VFP

VS

dots

fH =

15.87kHz

fV

= 60 Hz

clock (OD)

display

time

#4000

#0000

display

time

mode

16bit

GDC-1

Character

16K

(80

display

(16MHz) (

8MHz)

(4MHz) <2MHz>

40MS

?A«

6>js

10/js

1

2.6ms

1.2ms

1 ms

digits)

(40

digits)

#0000

16bit

8

bits

16MHz

4MHz

-

•^(14 Chr.)

(1?Chr

(tREF-0.8ms)

-

(20

Chr.)

-

16K

16bit

X

: Y - 1 : 2

graphic)

GDC-2

)

16

bits

16MHz

2MHz

-

10MS

5^s

(tREF = 1.6ms)

8ns

-

j

VBP

Total

rasters:

Display

raster:

261

200

rasters

1.8ms

—-1 r~-

•—n.

-

MZ3500

(2)

640 x 400

bits

fH =

fV =

Dot

clock

2XCCLK

Horizontal

HFP

HS

HBP

Vertical

VFP

VP

display

20.92

47.3

(OD)

display

kHz

Hz

time

mode

time

GDC-1

Character

32

55^s

(80

digits)

display

(40

(19

66MHz)

(9

83

MHz)

(4.9152MHz) (2.4575MHz)

80

Chr.

/40

4.88fjs

4^is

6 5ys

19.16ms

0.527ms

0.24

ms

digits)

Chr.

8

bits

19.66MHz

4.9152MHz (203.45ns)

*~

(tREF=0.6ms)

(50.86ns)

-

«-

-

«-

GDC-2

X

: Y : 1 : 1

graphic)

9.83MHz (101

24575MHz (406 9ns)

*~

(tREF = 1.23ms)

16

5

bits

92ns)

-

Chr.

-

VBP

Total

Display

(3) CRT

rasters:

synchronizing

rasters

441

400

rasters

signal

specification

CRT)

1.

Horizontal

2.

Vercial synchronization frequency (fV): 47.3Hz

3.

Total

4.

Rasters

5.

Display

6. Dot

7.

Timing

synchronization frequency

rasters:

clock:

441

used:

400

dots:

640 x 400

(19.66MHz)

rasters rasters

(fH):

dots

1.198ms

(400

20.92kHz

raster

9. HS, VS, and type

TTL 1C

6)

Setup

of GCD

(1)

Master/slave setup

^^•v^^

Graphic

GDC

(2)

Character

^^•\^^

^^^^

^"\^

Without

VRAM

8 bit

structure

48K

byte

200

rasters

16-bit

structure

96 K

byte

48K

byte

400

rasters

I/O

signal

-

VIDEO (totem

master/slave

by

GDC

PWB

Master

switching

signals

pole)

combination

Character

should

are

40

be

digits

supplied

setup

in the

-

from

above

the LS

80

digits

Character

Ch3rai.te'

Graphic

i.ia.

8.

Output

outputs.

method

VFP: VS-

5

VBP-

!

HS, VS. and

11

rasters rasters

25

rasters

VIDEO

(0.5ms) (0.24ms) (1.2ms)

are

indpendent

PIT A ft to

(8255.PB7

fiQ /I p ,, ,. ,

(CSP-2)

)

VSYNC

fc

Switching

Circuit

M-3500

CH48

-

I

08/16

- I/O

7)

Graphic

Relation between

0000

t

"~^

lnntn

0050

00\0

OOFO

LXH)

liytr

0 For 40

1

: For 80 There in the signal

digit digit

is a

gate

called

port.

port

inside

V-RAM

Address

VRAM

address

~

display display

40/80 digit switching

array

of

CSP1

and

CSP2,

CH48

is

bOb\ir

CSP1

and

—

provided

and

screen

apart

CSP2.

(640

x 200

signal

8-bit

I/O

but,

the I/O

from

the I/O

dots)

structure

Graphic

address

map

200

port

for

rasters

Relation

between VRAM

address

and

screen

16-bit

structure

Graphic

address

map for

400

rasters

CRTC block

diagram

Color graphic

VRAM

PWB

(option)

4/6.

4-6

7-9

16-18

20.21

26-28

Master

1

2

3

10 11 12 13 14 15

19

22

23 24

25

29 30 31 32 33 34 35 36

37 38 39

40

slice

Priority

Signal

Name

HSYi

NABC

CSR

ASO - AS2

DSO - DS2

G2

NWRO

NVB NVR NVB

FYD2

AT2 - AT4

CH

GND

DSP2

VID2

LCD

AT1

LC1 - LC3

NCL4

HSYO

RA40

VIDI

B1 R1 Of

SL1

B2

R2

BLNK

Vcc

LSI

(CSP-1)

IN

OUT

IN IN IN IN IN

IN

IN IN IN

OUT OUT

IN

OUT

OUT OUT OUT OUT OUT OUT OUT

IN

OUT OUT

IN

SP6102C

Horizontal

dynamic

Input

blinking timing

Input

mode. Address

Data

Green CSP1 Input Input Input Input

(Used Attribute

f

AT-2 - Horizontal Ime/R

|_AT-4 - Blink

Input

0V

Input

two

VIDEO

Character

(Becomes Attribute Character

(LC1 Character CRT1 The VIDEO Blue image Red Green Character

latch signal

Blue image Red Erase

1.

Horizontal flyback period

2.

Vertical flyback period

3.

Period from

command.

4.

Line drawing period

+5V

002

signal

synchronizing

RAM

mode.

from

the

UPD7220

and

from

the

GDC1 which

bus

input

ABO

=

bus

input

DBO

=

image I/O of the of the red of the of the

to

latch

AT-3 - Reverse/G

of

character display data signal.

supply

of

display

flipflop

output

= A1, LC2 = A2, LC3 =

, 2

horizontal

signal that turns high

output

image

signal

delay

image

signal from

supply.

from

ASO,

AB1 = AS1 , AB2 = AS2

from

DBO,

DB1 = DB1 , DB2 = DB2

output

port

select

blue image from

image from

green

image

graphic

the

image

data

input

J

timing

intervals

to

CRT2.

CG

line counter

address

input

data

input

CG

line

counter

CG

output

to the

output

to the

output

to the

output

CG

output

input.

(Used

flipflop

output

to

output

to

the

execution

description

signal

from

the

GDC1. When

line

counter

is the

the

sub-CPU.

the

sub-CPU.

to the

CRT2.

signal

(OUT #5X)

the

from

the

RAM

parallel/serial

data

in

from

the 21

"]

signal supplied from

in the

CSP-2

output.

to the CG

(vertical line/B)

output.

A3CG

data latch

synchronizing

level

CRT1

.

CRT1

CRT1.

to the

CRT1.

parallel/serial converter

for the

clock.)

CRT2.

GDC1 which

of the

the

ciear

signals

cursor

graphic

RAM

graphic

CSP1

.)

14A-1

attribute

to

creat

when

from

= A3)

timing.

signal

when

the

.

image data latch signal

becomes

SYNC

GDC1

Also,

it

becomes

GDC1

is in the

are

multiplexed.

display

input when

RAM(A)

and

(B).

(B), (C),

RAM (E) and

conversion

the

this

LCD = CG

the

400-raster

1C

input

SET

and

(F).

1C

74LS166

RAM.

CSP-2.

(BLINK signal

signal.)

address AO.)

2114A-1 attribute RAM.

CRT is in

74LS166

in the

at the

following

command

the

refresh

character

(D).

shift

to the

display

the

GDC1

shift

out

from

connection. LDA,

load

signal,

CSP-1

and

times.

execution

MZ3500

timing

signal

in the

mode,

the

attribute,

is in the

character

clock.

the

GDC2

01 H

and

character

horizontal synchronizing

of the

OUT??56

DISP

display

is

delayed

CG

START

address

by

-

39

-

MZ3500

CSP-1

Block Diagram

ASO AS1

AS2

MkRO

DSO ' DS1

I)S2

HSYI NABC

SL1

FYD2

BLNK

DSP2

ATI

AT 2

ATS

AT 4

CSR

CH

NVB NVR

1

4

1

s

**

J

-C

-c

-*

l-»

'

1

i >

CK

D

—

F/F

,. ..

o

t —

*

(bO)

Jl

J, „

n o > x — H

—

to fO

} } }

CK

n F/F

CK

D F/F -|

CK

n F/F .V j

n t» o u:

r \

SO

5C

1

<

to

D

ECH1

J?^"

(51)

(52) 'S3) (54)

J 1 1 II

1

1 I I I c n n r-

—

ro CO ^. Cn <7> ] | C

"\

"N .

* * .

BINK

1 1 Merge

» T circuit ? P -»-DSPT

X

<

r- r~

~ X O X

j 1

25 /20 —

HSYI

y^m-i™

1

^

Line

RA400 — 1

0/1..

>

n

1

^

B-VL

4 1 '^

'p

. . , , h r 1

« " + i I1 H

__

..._.

*- • 1 ^

\ \ 40 80

" ,.„

'

*

,

)FXF DF/F

I ) —

M~^y_

j

~* — ndividual

9/VL~*

character]

0

O m ^

m o re —

3

'55,50)

• 5fi .

,r»T

,

" ? - _ i "

0=5°

fr

counter/

Line

. . < — 1

shift circu

^ , ^ „ _

I

signal generator

40/80

d,q,t

r

tr r- < t~ r-

' — .

. ,.

t

14414

B/W

attribute

»-

merge

circuit

>J

5-

>-

K

\ 400

HSYO

VID1

£

???

U

s

^ '

S

''

-

s

o~"^o

Cursor erase circuit

JTV " - -

-^ " background

— — -D "c

*ili

Boder

merge

1—

=H>-^

(

>

V-RAM2

08

-'16

RA400

'"'

\

"

5

*

'• ~^ *— ~*^

CSR-2D

^

"O

r-| < r- ~

{>

ECH2

^

^SR4

°^SR6

I

L

graphic

c

designation

n

X

C

during

mode.

color

1

-J .

-

— ' '

' — 0 O-l B

V

f.

/ »

/ *

\

j X—^ B/W

}__S

'VL-»>

1 S ^ ^

G.

RV

->

—

° " '" — i

OJ

0

-

*-

U

0 G

FAT

2 1

| i-- r- --r

-^ 1

COLOR-* l^^^ro

^ ^\_ ^ _

-TV 5*=

fAIL-

OK;

44444

— + Cursor;

^

background

"

i>-hi>,

O 3 bri OM pS

attribute

'

Blink

merge

;Reverse

circuit

Line

fin

Border

'~) ") *•

-""

4^V^

T *

>-

3-

y-

•>-

V1D2

CSH-

-

40-

MZ3500

46. LSI

1

2

3

4-5

6

7

8

9

10 11

12

13

14

15

16-17

18

19

20

21

22

23

24

25

26

27

28

29

30

31-33

34-35

(CSP-2)

Polarity

Signal

Name

HSY2

BLK2

OWE

AD14-AD15

DBI2

DBI1

BUSG

SOE

SWE

0816

RAS1

RAS2

ASS

NWRO

DSO-DS1

RA40

M40

GND

SL2

RASA

2CM2

LOAD

Vcc

FYD2

2CK1

SL1

CGOE

DB1C-DB1A

RAS-C

RAS-B

SP6012C-003

IN/OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

~

OUT

Signal

Description

Horizontal

dynamic

Erase

1.

2.

3.

4.

WRITE

Input

(Used

Input (Used

Gate data

OUTPUT

WRITE

8-bit/word (8-bit/word

Memory (Used

Address

Chip

Data

The (Used

Clock

0V

Graphic DRAM

Graphic

Double one 8/16

Graphic

+5V

Graphic

Double of one

Character

Timing

Graphic

synchronizing

RAM

mode.

signal

input Horizotal flyback period. Vertical flyback

Period from

command.

Line drawing period.

ENABLE

of the

to

create

from

to

create

from

to

create

signal

from

ENABLE

control

to

create CGOE,

control

to

create SL2,

bus

select (OUT#5X)

bus

signal

for

input

supply

DRAM (A),

character

dot

frequency

DRAM

supply.

DRAM

character clock

half

signal

DRAM

RAS-B;

from

period.

the

execution

output

display

DBIA-DBIC

the

GDC2

RASA-RASC, CAS,

the

GDC1

BUSG, SOE,

of the

bidirection

the

static

ENABLE

input

that

clock

CG

CG CG

CG

for

and

16-bit/word

chosen

with

signal

input

from

goes

frequency selection

from

the

output

clock

wide

frequency

is

output

the one

character wide frequency

output

address.

output

by

which

RAS

RAM(C),

signal

from

GDC2 which

the

GDC2 which

of the

SYNC

for the

graphic dynamic RAM.

output

signals

(AD14,

in the

CSP-2.)

by

which

the

image

PS, OWE in the

by

which

the

image memory

SWE in the

RAM (21

to

bus

14A-1

character

attribute,

LOAD,

the

clock

(B) RAS

supplied

parallel/serial converter

parallel/serial

enable signal.

(ROW ADDRESS

(D)

character

select

LDA.

OOH

RAS

from

SL1 in

CSP-2.)

RAS

from

RASA-RASC, CAS,

the

sub-CPU (ASS = AB3)

of the I/O

sub-CPU (DSO = DBO,

high

level

generator

parallel/serial converter

signal.

output.

is

to

parallel/serial converter

parallel/serial

output

same

the

graphic DRAM output

RAS-C;

buffer

, 61

static

signal.

OUT#5D,

GDC1.

CDC3.

port

(input

in

CSP-2.)

(39.32MHz,

In the

character

supplied.

GDC2.

converter

as

converter

RAM

CSP-2.)

(LS245)

RAM (61

in

from

2CK2.

SELECT)

also

becomes

is

supplied

4T the

following

SET

command

AD1 5)

memory

16P-3).

static

RAM.

and

FS.

CSP-2.

DS1 = DB1 ).

CSP-1)

1C

display

In the

graphic display mode, a single

1C

In the

is

supplied

1C

74LS166 shift

1C

LS166

(E),

(F)

to -be

from GDC2.

output

is

CSP-2.)

output

is

which

is

used

16P-3).

16-bit/word

DBIA-DBIC.

when

the

for

400-raster mode.)

74LS166 shift load

mode, a single

74LS166

74LS166 shift

character

to

GDC1

shift

load

is

sent

on the

signal

the

refresh

tirniny

times:

execution

sent

on the

sent

on the

to

read/write

is

400-raster

load

timing

out

display mode, a single

.

out

signal.

data

chosen

DSP2

phase

clock.

bus.

of the

data bus.

data

with LDA,

in

CSP-2.)

CRT is

signal.

clock

clock.

bus.

attribute,

phase

.ijr.s'i

in the

DISP

START

and

01 H

connected.

of the

half

clock

phase

character,

OUTiSD.)

the

of

clock

-

41

-

M/3r>00

Priority

Signal

Name

36 37

38

39

40

M32

DSP2

CAS

Vcc

FS

2

CSP 2 Block Diagram

IN

OUT

IN

Clock

input

32MHz,

Graphic

DRAM

|ADO AD7] select signal Display

timing

create

this signal

Graphic

D RAM CAS

(Line

address

+

5V

supply

200

address

signal

(In the CSP 2, the

)

selection)

Jl

PR

Hexadecimal

counter

r*

raster

multiplexer

)

(COLUMN

signal

(High

signal

ADDRESS

D

™

£

O

order 8 bits

BLINK

SELECT)

S-RAM

& CG

control

signal

generator

C

i ' '

:

co

i i

3

6

GDC1

&

character display

clock

generator

from

signal

I ADS ADI 5]

GDC2

is

L

delayed

^

/low

by 2

^—

Bl SC,

D-

SOf

O- SHE

3'der

collor

S hi"

intervals

to

VWRO — C

KAS2 — C

Ubl 2

—

C

32MHz 200

Raster

3«32MHz

*M

n~, *

4U(J HasTer

^

-a.

Clock

ClfCU1

^00/41

rasters

1

O

select

,

to

Oh

16

40/80

c

,

F

K

n

•

0 t

T

ft.

CK

I)

F

Q

L>

F

5

Q

O

2

)ECODER

bill 6

8/1

— 3

GOC2& graphic

circuit select

clock generator

Cfi

display

DBI2D

F

'

DRAM

control

signal

generator

' '

' •

O—HB

GDC2

Read ignal generator

1 A

-

42

n

h

P°

L}

\ C K

t f

-

4-7.

GDC

1

2

3

4

5

6

7

8

9

10

11

(Graphic

Polarity

Signal

Name

2XCCLK

DBIN

HSYNC-REF

VSYNC

EX.SY

NC

BLNK

RAS

DRQ

(NO

USE)

DACK

(NO

USE)

RD

WR~

AO

display

IN

OUT

IN/OUT

OUT

IN

controller)

(UPD7220)

Double

character

two

modes:

1.

Character

2.

Graphic

Memory contro

memory

Memory

synchronizing

•

Since

address

•

Refresh

circuit when

Establishes

or the

1.

When

2.

When

level

Erase

1.

Horizontal flyback period.

2.

Vertical flyback period

3.

Period from

command.

Memory

• In the as

DMA

following

1.

DREQE (DMA request write):

2.

DREQR (DMA

It

will

write)

Signal write signal

In the reads

In the

writes

display

disp'ay

output

contro'

the

image drawing

is

output during

is

accomplished

one of

slave.

the

master

the

slave

input.

signal

output

control

dynamic

the

timing

request

output

two

be

continuously

command

supplied

during

external circuit

from

the GDC

external

to the GDC

Normally, connected

signal

clock supplied from

mode1 Single

mode:

Single

signal

supp'ied

data

to be

sent

signal sent

signal.

the

following

is

the

signal

RAM

signal

commands'

request

becomes zero.

from

circuit

to the

process

the

by

HSYC

is at h gh

two

is

operational:

operational

is

issued

at the

execution

sent

to the

mode,

by

which

is

read).

output

the DMA

DMA.

RD is

combined with

either

data

WR is

with

combined

the

either a command

description

the

external

phaseclock

phase

clock

of

to the

image

on the

image memory

is

HSYNC period.

suppressing

lebel

modes,

sends

: The

following

of the

image

it is

used

the

address

connected

CPU

Image memory

until

controller that

or

status

address

memory from

data

bus.

automatically interrupted

the CAS

(Horizontal Synchronous - Refresh depending

out the

synchronizing

times (blanking

SYNC

SET

memory from

as the

signal

(Row Address Strobe)

with

memory

the DMA

(DMA

(DMA Acknowledge)

the

flag

(Read

with

the

or

parameter

(Write

line

and is

dot

timing

generator

at one

half

dots

from

also

signal

on

signal

of the one

that

the

GDC,

be

derived from

whether

generation counter

eight

It can

vertical synchronizing signal.

cycles

the

GDC, which

which

in the

used

as the

the GDC is

character

dynamic

signal):

command

reference

is

the DRQ

to

to CPU

transfer

to the

the

GDC,

signal

latched.

image

of

input

of the DMA

memory. memory.

word/byte number

execution

RAS. When

Request)

is

subsequently decoded

chip

select

signal

and the

strobe)

chip

and the

strobe)

used

signal

select

TO

(CS).

DACK.

signal.

And is

signal DACK.

designate

data

which

has the

followin^

wide

cycle

causes

the

is the

horizontal

RAM

refresh

the RAS

operated

controller

set by the

mode

timing signal.

signal

timing)

by the

is

initialized

of the

DISP START

at

high level, used

is

VECTW

in the

by the GDC as the

And is

used when

the CPU

type.

M

7.3500

image

the

by a

output

read

the CPU

refresh

external

master

high

by the

(vector

or

12~19

20

21

22-34

DBO-DB7

GND

LPEN

ADO-AD12

IN/OUT

IN IN

IN/OUT

Bidirectional

0V

supply.

Light

pen

ectional

data

RAS

strobe

are output

The CPU can

Bidn and the

AO

RD WR

0 0 1

1

0 1

0 1 0

1

1 0

data

bus

connected

nput.

then

read

address/data

sent

on the bus by

in the

(Address

to the

When a input the

display

bus

connected

means

external

circu

function

^Mode^'

READ STATUS FLAG READ DATA

IN #71 IN #61 WRITE PARAMETER WRITE COMMAND

OUT #71 OUT #61

Bus 0)

system

bus.

(Data

Bus

0-7)

light

is

sensed

by the

address

of

t.

via the

between

multiplexer

(Address/Data

light pen,

LPENR

(Light

the

image memory

ALE

(Address

bus

IN #70 IN #60

OUT #70 OUT #60

GDC1 GDC2

it

outputs a high

Pen

Read)

and the GDC on

Latch

Enable)

command.

level

which

is

drived from

0-12)

signal.

address

M Z 3500

No

35-37

38

39

40

Polar,

ty

Signal

Name

AD13ILCO)-

AD15ILC2)

A16

(LC3)

(AT~BTI

NK-CLC)

A17

(CSR)

(CSR-1MAGE)

Vcc

IN/OUT

OUT

IN

Provides

the

character

1.

In the

2.

In the

ROM

• In the

Provides

0.

character

1.

Graphic display

2.

Character

3.

Character

Provides character

1.

Graphic display mode: Image memory address

2.

Character

3.

Character

select

+

5V

following functions

display mode graphic display mode character

or

graphic

character

the

display mode

timing

display mode

graphic

RAM

and

display mode

following

display

mode

mode: display mode display mode

following

display

mode

display mode

signal.

supply.

0,

character display mode

functions

0,

based

character

address.

1 ):

Image memory address

1 : 0:

Attribute/blinking/timing

character display

1 :

0:

Cursor

on the

display mode

and

character display mode

1 :

Line counter

1 :

LCO~LC1.

based

on the

Line

counter

based

on the

Cursor

display

Function

operational mode

1).

output

in

0:

AD13~AD1

(Address

Data

(Line

Count

0-2)

operational mode

output.

(Address (Line (Attribute

operational mode

mode

output.

output,

(Address) (Cursor) (Cursor-image)

signal

16}

Count

3)

Blink — Clear Lire Counter)

1):

output.

character display

of the GDC

0:

Bidirectional

connected

5.

bus 13 ~ 15)

of the GDC

and

external

of the GDC

(graphic display

address/data

to the

character

(graphic display mode.

line counter

(graphic display mode,

area

(graphic)

bus

generator

clear

display

mode,

signal

area

-

-14

-

M

"

4 8 CG

Address

Select

Circuit

When

(only

200

rasters

the

on

high order 8 bytes

ASCII

in use

of 16

bytes

are set to low

level

I

ASCII C.G. Structure

»

I i r r

=^=^

1020

10! 1-

Character

Code

leBytes

lOOh

ifiBytes

1000

01-1^

0020

001

t

a

Bytes

0018 0017

K

Bytes

(Hi

in

001 1

8

Bytes

0

Iftk

OKI

fc Bytes

ii i

01

For

Model 3500

Character Code

00

For

Model 3500

==

Code

01

For

Model

3200

'/

'///'

s/

/////^

'

Code

01 ',

' For x

,.

Model

3500: Character Code

00

For

Model

3200

/

Character

Code

00 ',

' For <l

^Model

3500^

i

in

i

8 b ts

/i

\

M'-O

A3=l

\

M

I

l'= I -

•>

I

f

1-0

*

1

i i

t

8x16

>

Pattern

400

Rasters

8x8 Dot

>

Pattern

200

Rasters

dot

ASCII

character

[Circuit

of the 200

description]

raster

(Purpose) The

character genrerator (CG)

the

200

raster video

video

display

therefore

used

[Operational 1

When

the 400

sets

A12 of the CG to

above 1000

display

unit

of the \X

to

select

description]

raster

is

selected A3 of the CG At the of the

LS240

is

closed

2

When

which address

CPU

the 200

sets

raster

A12 of the CG to low

0000

OFFF

structure

CRT

unit

those

CRT is in

high

Also,

same

every

CRT is in

is

selected

incorporates

of the \X

3500

The CG

modes

use,

RA40

level

at all

gate

(1)

time,

gate

16

bytes

use,

RA40

level

Also,

ASCII character structure

of the 400

opened

gate

raster

all

character

3500

and by the 400

address

is set to

times,

so

that

so

that

(3) is

opened

is set

turned

continuously,

(2) is

opened

CRT

code^

select

high

the CG LC3 is

so

that

to low

cirruit

level

that

so

used

raster

which

address input the

gate

level

the CG

that

the

by

is

to

-

45-

MZ

4-9.

VSYNC

3500

From

1 80

(8255

PB7) CH48

80 Master

digit,

0 40

16bit/word

is

GDC-2

Digit

Digu

40

digit. 16bu/word

80

digit,

8bit/word

Master

is GDC

40

digit, Sbit'word

Master

is GDC 1

SRES

(From

MMR)

[Circuit

description]

When

more than parallel, to the

slave

timing.

The

to the

table below.

compare

""~~~-~^GDC-1

GDC-2

(graphic)"""

Without

8-bit

structure

(48KB,

200

16-bit

structure

(4896KB,

one

master

with

VRAM

raster)

400

two

must

be

in

order

the

table

(character)

^^^

PWB

[0816=0)

[0816=1]

rasters)

The

[Oprational example] If it was set to 80

0

when CH48

tion.

These

B

(weight decoder the

GDC2

signals

2), and G

1C

LS139

is

input

= 1,

to

UPD7220 GDC's

assigned

and the

The

to the

to

mantain synchronous display

slave

above

circuit

description.

CH48

= 0 40

GDC1 (character)

is

the

GDC1

master

GDC

must

digit,

16

bit/word

0816

= 1

when

are

supplied

(gate),

to

"0",

terminal

and set

so

EX

to

that

are to be

master

are

determined

digit

master.

be set as

not in the

mode

operated

and the

shoud

be

CH48

= 1 80

GDC 1

GDC2 (Graphic)

indicated

SRES

reset

according

terminal A (weight

the

SYNC

terminal

YSYNC

of the

Y3 of the

output

GDC2.

other

used

digit

above.

will

condi-

in

to

be

1),

of

-

46-

MZ3500

4-10. Character

BL'SC

VRAM

The

signal

within

address

the

display

select

BLNK

area

data

circuit

is

used

of

from

to

address 0000-07FF the

VRAM

the

ASCII

in

transferring

to the CG.

RAM

Lov

*/

when

0

300^07FF

6 1 1 6(

ASCB

CS

V-RAM

2114(!Kx4)

First

half

attribute

2114(1K*4)

Latter half

attribute

2K*8)

of

#0000

*0000

-07PF

*0000

-03FF

#0400

-07FF

BLNK

Erase

6

I 1 6 >

ASL C

signal

2K»8

V-KAM

8bil

H-SYNC

BLANK

)

TT_

Latter

attribute

First of

attribute

half

of

TTJ

Period

ARIO

AK10

that

and

[Circuit With of the character this

function.

t

= H1

T

= Low

the GDC is

draw graphic data.

description]

respect

to

character VIDEO-ROM

VRAM

*07FF

*0400 #03KF

toooo

enabled

GCD1,

select

to

the

assignment

circuit

read/write

is per the

is

provided.

during read/write

table below.

Jo

The

accomplish

-

47

-

MZ3500

4-12. Read/write

Read/write UPD7220GDC. There

data.

The

of the

method

Model

(1) is

from

are two

used

the

Z-80

3500

V-RAM

methods used

for the

model

Set

GDC

to

V-RAM

is

done

3500.

YES

command

YES

via the

to

read/write

code

NO

(1)

Read/write

(2)

Read/write

intervention

(Outline

of the

Method

to the

GDC.

via the 16

of

V-RAM

of the

read/write data

used

to

give a command

byte FIFO.

in the DMA

FIFO.

via the

FIFO;

mode

without

Set

parameter

Set

parameter

for the

YES

for the

I

Command On

command.

must

page

is the

be

given program

to the GDC in the

of the

above

same

manner.

flowchart.

-

48-

MZ3500

(Subroutine

via

the

FIFO)

lo

send

command

and

parameter

to the GDC

HL reg — B. reg — C

reg - 60H

>

FIFO

;

COMMAND

First

address

Q'ty

of

data.

(graphic GDC),

Empty?

—• GDC

;

Return

of the

if

parameter

command code

70H

(character GDC)

not

sent.

oarametpr

Example

1)

Dot

display

0000

0028

of

0001

graphic

RET

drawing

by GDC

0027

VRAM

structure

f

FIFO

;

PARAMETER — GDC

;

Return when

16-bit

Empty?

all

Example

parameters

CSRW

WRITE

VECTE

were

to

display

a dot on the

C 49H

P1

01H — Low

P2

OOH —

P3

30H - Dot

C 23H -

C 6CH -

sent.

fourth

-COMMAND order

solute

High

order

solute

address

COMMAND

COMMAND CODE

one

address

one

address

(dAD)

bit of the

CODE

byte

CODE

address

of the ab-

of thp ah

-

49-

M23500

[Explanation]

Display

dot, specify

the dot

address.

(set

mode

plus CLEAR, REPLACE,

modes

using "VECTE". following

[Dot

Dot

manner.

display

C-COMMAND p_

PARAMETER

the

display

Set the

"WRITE",

address

program example-1]

LD LD

command

is

HL

(HL)

INC

LD

(HL)

INC

LD

(HL)

INC

LD

(HL)

INC

LD

(HL)

INC

LD

(HL)

CODE

'

address

code

and

specify

structured

.5000H

.

49H

L

,01H

L

,

OOH

L

30H

L

,23H

L

,

6CH

) To A

of the

VRAM

of the SET

and

COMPLEMENT

to

start

on the

screen

and

mode

with

in the

5000

5001

5002 5003 5004 5005

dAD=

— 49 H

— 01 H

— 00 H — 30 H — 23 H } — 6CH }

Address 0001

0 1 2 3 1 5 6 7 8 9 10 11 12 13 14 15

CSRWdata

WRITE

VECTE

data data

LD LD LD

CALL

LD

LD LD

CALL

LD LD LD

CALL

C

B ,4H

HL

GDC

C B

HL

GDC

C

B , 1H

HL

GDC

,60H

,5000H

,60H

, 1H

.5004H

, 60H

.5005H

C — BOH

B - Byte HL

- Top

Command,

B - Byte HL

- Top

Command,

B —

Byte

HL

- Top

;

Command,

(port

address

size CSRW data

address

parameter

size

of the

address

parameter

number

address

parameter

during

of the

of

WRITE data

of the

of

of the

graphic draw)

CSRW data

CSRW - GDC

WRITE data

WRITE

VECTE

- GDC

data

VECTE data

VECTE

- GDC

2)

Straight

line drawing

M

7.

3500

00000

0001

0028

Example

Y)

to

draw a straight

=

(635,

1).

Coordinates must

(3,

1) -

absolute

Dot

address

Displacement between

direction

Y=0

Whereas.

CSRW

is OA (to the

C 49H

PI P2 OOH P3

TEXTW

C

PI P2 FF

VECTW

C

PI

P2

P3 P4 P5 P6 P7 P8

P9

line

be

changed

address = 0028H

= 2H

two

points

right):

28H

20H

HAD I, , H

dAU

78H

FF

Kind

4CH OAH

}

Drawing direction

78H

}

\ 1 AX I

02H 88H

1

f

H>H

1

FBH OOH OOH

2 ! AY 1 - I A x I

OH

1

>

2 1 AY 1 -2 1 AX I

1

2 i AY !

0027

0050

VRAM structure

from

(X, Y) = (3, 1) to (X,

to

absolute

X =

of

when

635-3

line

addresses.

the

= 632

(solid

16 bit

line draw

(=278H),

line)

WRITE

VECTE

[Explanation]

Specify

the

code

and P for direction Y. The to drawing

rest

display

using VECTW

a dot

direction

C 23H

C 6CH

kind

of

line

parameter,

will

be

same

using

by

TEXTW, using

and

specify

and

above

four

the dot

the

X = Y = 0.

display

line drawing method

C for

the

line drawing

values

It is

command

using

X and

also

possible

for any

line

M Z 3500

5-1.

Outline

Floppy

disk

is a

disk

which

surface

is

coated

with

magnetic

device

to

write

and

read

It

will

be

necessary

floppy

disk

unit

recording method

5-2.

Floppy

As

various recording methods

floppy

disk (F.D.)

3)

Components

and

disk

of

to

and

operational description, including

format.

systems

FD's:

is

made

of a

mylar

particles

data

on the

surface

know operating

and

formats

we

will

discuss

5. MFD

sheet

whose

and set on the

of the

pnciple

some

are

of

of the

used them

INTERFACE

1)

disk

2)

for

Single

Floppy disk nomenclature

Floppy

disks

called

by

different

manufacturer

[>-

Floppy media

<•'

Diskette

Floppy disk

Types

of

Four

types

storage

capacity

(>-

Single

sided, double density

[°

Double-sided,

sided

media

Double

media

are

index

sided

Front

(or

used

double

detect

media

side-

simply

at

density

hole

index

as

medn)

present

(floppy

detect

hole

names

dependng

depending

disk-1)

disk-2D)

Feverse

side

on

on the

their

4)

Write protect notch

Different

drive

Example-1:

unit

write

used.

In the

Head

engage

(do

not

protects

light coupler

slit

touch)

are

adopted depending

case

of the

reflection

and

decoded

Write protected

Front

side

o

is

0

CE331

sensed

as

on the

the

presence

by the

write protect

photo

-

No

reflection

of

(Write

enable)

Head

1

Write enabled

Front

side

o

0

Head-0

-

(Reflect"n<!

r«ywing)

Example

2:

CE330S (light

is

sensed

(Double

Front

passing

and

decoded

side,

Double density)

Write

enabled

side

through

as

write

the

notch

protect)

Light

is

interrupted

by the

label

Write

Front

protected

side

-r-

nhibit notch

Two

types

of

write must bepaid cause a wrong result

5)

Media recording methods

Two

recording methode

• FM

This

(C: Waveforms

method

clock,

Write

(WD)

to the

(Single density) is

called

D:

data)

of

data

O

0

protection

presience

if the

are

written

are

used

and

attention

of the

label

because

label

is

used

used:

the

freqency modulation (FM)

1

0 0

it may

improperly.

n n n n

C D C D C D C

or

read

T_J

in the FM

r*-

D

ILJ

1

mode

are

C

I) C D C

n

n n

0

shown

fL_JL_fl

below.

0

or

double

on

the

precede

I

D

ILJ

o

0

frequency

media

the

data.

C

D C D

i n i

which

0

(DF).

Clock

requires

JL

and

data

that a clock

0

are

written

bit

that

Write

current

Residual magnetic flux

on the

Differentiate

waveform

Shaped

waveform

Read

data

Write

current:

is

inverted

direction

each

of

media

y

^

(RD)

The

write

data

time a pulse

writing current.

—

•«—

\

_

fi_i

.—

>

9

US

4

is

L_J

—

*•

^v

/

J

r\

i

—

i

n

i_

k

input

to the

received

to

flipflop

change

r/

n

and

the

^s

l

—

i

»•

.«—

~\

\

vy

i i

fl_J

Read at a change shaped Data

cycle

1

—

»•

+

"^

J

r\

X

y

f-'

rn

n

n_j

waveform:

of

to

obtain

will

be

The

magnetic

read

4/^s.

L

peak

of the

flux.

data identic

J

waveform

The

waveform

it

>.<_•

>

Wrote

•\

tlirf

Read

is

write

detected

is

than

data.

o MFM

The tion

The tion Because possible

6)

Media

Media For (head-1)

MZ3500

method (double density)

MFM

method writes data

metntioned

clock pulse as

there

the

recording is

Double

below,

Input

data

Write

data

(Ci

is no

data preceding

data rate

to

obtain

twice

format

formatted

side media, data

and the

reverse

on the

basis

and it

yields a data density

0 £ 0 £ 0 1 0

\ /\ /\

n n nnn n

C C (C) I) (C) '(_

Data

will

be

eliminated

or

following

is

2/Js

for

this

the

according

side (head-00)

density

to the IBM

is

written

of the FM

of the

condi

two

•'•>

n

X"V

t

\

that follows Data that

in

above illustra

method,

format

on the

the

clock

method

front

/\ /

it is

side

times

the

sary

clock

(Condition) Clock

0111

n

n n

'

VnVn

[ci

|D (ci |u ici ,i> ci

<

i i

precedes

NOTE

Three

data density

pulse

is

eliminated using this method

is

0

n nV

types

are

used

The

to FM

method

of the MFM

written

1 0^0

only

mode (The

when there

n

nnn7 n

(0 ;i> (c) (O

i

of

write data cycl»-

read/write

waveform

is no

/

(2f

~>t"> SA*S) is

unneceb

)

data

identical

Tracks, consists cylinders) Sector.

01-16

Recording density:

of 40

tracks,

256

bytes/sector

00-39.

(May also

be

called

Floppy

disk

Shown

below sequence through

Writing

the

index

is an

starts detect hole

enlarged

as

soon

Sector

view

of

as the

index hole comes

01

data format

Sector

1

Track

02

Firnl

M 7 3500

^p

Start

<[ t

point

INDEX

\M

ID

AM

TT

HH

SS

DL

CRC

DATA

CRC

ID

section

Size

(00)

H — 128

(01)

H — 256

Sector Head

(00)

H -»

(01)

H -*

Hatched

a

recording

CRC

of

data

section

number

Head 0 (side

Head 1 (side

portion

check

bytes bytes

DATA

gap

0)

1)

is

code

IU

DATA

AM

NOTE

'

Data

(or

The

is data

a

new

no

II)

address

delete

written

It is

floppy

valid

51

DATA

Data

address

to

often

data

DA I A

mark

mark)

indicate

written

disk

as

on it

mark

invalid

there

Data CRC

on

CRC

section check

are

CRC

code

7)

Formatting

To

write

the

above

on an

entire

surface formatting Note 1 Formatting word

"initialize"

the

data section difference Note 2 Unless adjusted another

8)

Data write procedure

Described (1)

(2) (3)

(4)

(5)

between

floppy

disk drive

head

is

The

head

is

ID

section

is

reached

When

the

desired

on

that

area

The

data

thus written

written correctly

ID

section

format

of a new

may

is

also used

or to

partition

formatting

disk drive

is the

procedure

moved over

loaded

is

read

and

ID

(DATA

(read

is

read while

•

Track

•

ID

begins

(ID

section, data section, gap)

floppy

disk

also

be

called

initialization.

as a

and

has

unit,

unit

the

repeated

section

AM is

is now

after

the

software data area. Keep

been

an

to

write

track

is

also

write)

media

term

initializing

done

on a

erroe

may

data

to be

until

found,

data

written

checked

The

makes a full

number

address

mark

the ID

is

called

to

clear

in

mind.

properly

occur

on the FD.

written.

the

desired

is

written

)

if it was

respective

section

The

the

on

turn

which

(6)

9)

Data

Described

FD.

(1) (2) The (3) The ID

(4)

The

sector

with

the

capability

data

is

read

The

head

sector

When

that

data section

of the

write

the

quite

low

procedure

is

moved over

is

loaded

section

is

reached

the

identical

data

Because

possibility

procedure

is

read

and

IDsection

is

then

of an

the

track

repeated

read

ID is

to

read

and

of thr pad

error

in the

read data

tu -^ i ead

until

is

found,

dftei

from

the

verified

Ar.'e

written

the

desired

<~i-m

IP

5-3.

MZ3500

MFD

interface

block

diagram

>

MOTOT

ON

-

56

-

FDC

(UPD765)

M 2 3500

RLSt

IQ »•

RDO WRO »• CSO

AOO

DBOo-«

DB1CX DB2O4 DB304

DB4

O< ft-

DB5CX DB6O4 — t- DB7O4 — *• DRQcn

DACKO

TCO

INDEXO

INT04

*0 »•

GNDO

UPD765

»

>

» » K ».

— *

*

>

»•

configuration (top

1

^

2 3 4 5 6 7 8

9 10 11 12

13

14

15 16 17 18 19

20

view)

OVcc

40

39

KDRW/SEEK

38

K3LCT/DIR

37

*O

36 35 34

33 32

31

30 29 28 27 26

25 24 23

22 21

FLTR/STEP

K3HDLD

«

0

READY

4 O

WPRX/2S1DE

4 O

FLT/TRKO

K> PSO K>

PS1

K>

WDATA

>0

USO

K5 US1

K>

SIDE

K> MFM

NDWE

>0

SYNC

•< O RDATA

•«

— o

WINDOW

4 0

WCLK

RD-

WR—K

UPD765

READ/

WRITE/

DUA

CONTROL L.OGIC

A-N.

No/

block

diagram

SER f AL

1

Mf

KFACfc

DR 1 VE

1NTERFACE

CONTMO1

LER

I

SPUT

POKT

- » I KT

- 1 M)t X

- Fl T T

RESET

RD

WR

CS

AO

DBO-7

DRQ

DACK

TC

INDEX

INT

GND

WCLK

WINDOW

RDATA

SYNC

WE

:

Reset

:

Read

:

Write

:

Chip Select

:AO

:

Data

Bus

:

DMA

Request

:

DMA

Acknowledge

:

Terminal Count

:

Index

:

Interrupt

:

Clock

0

:

Ground

:

Write Clock

:

Data

Window

:

Read

Data

:

VFO

Synchronize

:

Write Enable

Request

MFM

SIDE

USO.

WDATA

PSO,

FLT

TRKO

WPRT

2

SIDE

READY

HOLD

FLTR

STEP

LCT

DIR

RW/SEEK

:

MFM

:

Side

Select

:

Unit

1

Select

:

Write Data

:

Pre

Shift

:

Fault

:

Track

:

Write Protected

:

Two

:

Ready

:

Head

:

Fault

:

Step

:

Low

:

Direction

:

Read

Mode

0

Side

Load Reset

Current

Write/Seek

-

57

-

MZ3500

UPD765

No.

40

20

19

1

4

13-6

3

2

18

5

14

15

29,28

26

signal

description

Signal

name

Vcc

GND

0

RESET

CS

DB7

~ DBO

WR

RD

INT

AO

DRQ

DACK

USD,

1

MFM

I/O

Function

-

I

1

' 1

o

1

o

1

+5V

0V i

Single phase,

Set

the FDC (don't into

an

Validates Bidirectional, Control Control

The

signal used

DMA The

signal used

bus. When

FDC The

signal that indicates

care),

input

RD and WR

signal signal

mode,

0, it

to

memory

TTL

level

clock

into

an

idle

state,

are set to low

level

and all

In

state.

signals

tri-state data

to

write

to

read data

to

or

upon

to

selects

bus

data

to the FDC via the

from

the FDC via the

indicate a service

completion

select

the

status

execution

status

register

data transfer request signal

use of the DMA

drive

addition,

request

register

When

cycle

unit

interface

INT and DRW

data

bus

data

from

the FDC It is

of a

command

or

data

register

1. it

selects

in the DMA

During

outputs,

outputs

bus

in the DMA of the FDC for

the

mode

the DMA

except

are set to low

issued

data

register.

cycle,

PSO,

1 , and

level

at

every

byte

in the

mode

access

via the

it

functions identically

WDATA

DB

goes

non-

data

toCS.

0

o

Drive

unit

The

signal used

assigned.

select signal,

to

When

designate

1, the FM

with

mode

which

the

up to

four drive units

operation mode is

assigned

can be

of the VFO

selected.

circuit When

0, the MFM

mode

is

24

39

36

27

38

37

35

34

17

33

16

30

25

21

SYNC

RW/SEEK

HOLD

SIDE

LCT/DIR

FLTR/STEP

READY

WPRT/2

SIDE

INDEX

FLT/TRKO

TC

WDATA

WE

WCLK

o o

0 0

0

o

1 1

'

1

0

o

1

The

signal

operation.

Signal interfacing

Signal used Signal used

it

selects head

When read/write it

works

When When

as

Signal used

When

unit

used

When

used

to

discriminate

signal. When

to

load

to

select head

0.

the

RW/seek signal

head

as DIR

1,

seek

is

the

RW/SEEK signal functions

the

seek

step signal.

to

indicate

the

RW/SEEK signal

or the

floppy

produces 2 SIDE

Signal

to

indicate

When

the

Data

is in a

indicates used

written

to

write

RW/SEEK signal

fault

to

indicate

on the

indicate write

timing

unit which

Signal Data Signal

to

designate

0, it

the

prohibits

the

0, it

indicates

the

read/write head

operation

reading operation

read/write signal

#0 and

When

1, it

selects

is

selecting

which indicate

operating the

cylinder seek

made towards inner

that

the

drive

is

disk

which

the

condition. that

floppy

signal

operating

is

write protected. When

indicates that a double

physical start

is

operating

When

the

read/write head

the

termination

disk

consists

enable

to the

which

is

mode

RW

When

head

#1 for the

head

1.

as RW, the

above direction When side

as RW, it

unit

is

ready

as RW, it

point

of the

as RW. it

the

RW/SEEK

is on

of a

read

of

clock bits

drive

unit

250kHz

in the FM

of the VFO

from

1 , it

the

seek

indicates

circuit

signal

When

that

double-sided floppy disk drive

signal

works

as LCT

43.

When

0.

seek

works

as F LTR

for

operation

function

the

RW/SEEK

sided media

the

RW/SEEK

is

as

is in

which indicates

made towards outer side

which

resets

WPRT which indicates

is

function

use.

track.

works

as FLT

0. operation

data

or

which

as

SEEK,

bits

500kHz

in the MFM

is

operating

cylinder

or

write

and

mode

1, it

used

is

operating

any

as the

indicates

it

works

permits

for

drive

unit.

When

that

as

SEEK,

fault

condition

that

SEEK signal

that

the

as

TRKO

mode

reading

unit

the

drive

0,

-

58-

MZ350C

P,n

No

32. 31

23

22

Signal

PSO.

RDATA

WINDOW

5-5. Data recording

There method

2)

MFM

(1)

Data

(2)

When

the

are two

and MFM

current

ways

recording

recording method

bit is

placed

the

data

bit is

bit

cell. (See Fig.

name

1

method

of

recording data;

method.

in a

middle "0", a clock

I/O

O

1

'

of a bit

1)

Signal to the

Read

Signal

carried

FM

cell.

bit is

to

either

used

obtain

table

rung

tir

ow

be

PSO

data

from

created

in the VFO

out in the FDC for

recording

placed before

advance

adjustment

0

1

the

drive

or

for

PS1

0

1

0

1

unit

consists

circuit

RDATA

1) (1) (2)

delay

the

reading.

Not

changed

which

data

MF

recording Clock Data

FM

-

of

is

Function

write

The

clock

used

bits

bit

bit is

data

in

WDATA

MFM

Not

changed LATE

225~250ns

EARLY

225~250ns

bits

and

to

sample

and

WINDOW.

method

indicates

placed

writi

signal

-

in a

ng

is

data

bits.

RDATA.

a bit

middle

under

the MFM

controlled

Phase

cell.

of a bit

mode,

as

shown

syncroni^i

cell. (See Fig.

in

I.

As

seen

from

the

recording method other words, doubles that

5-6.

I/O

port

data

of the FM

port

used

in the MFD

IOMF#F9-AO

IOMF#F8-AO

JUULJUULJLJlJLJLnJl

—

1

n

i

above

illustration,

is

twice

the FM

density

in the MFD

of the MFM

interface

recording

i

!

n

i

0

| ,

bit

density

recording

interface

is as

D-BUS

recording method

method.

follows.

I/O

OUT

D7 D6

D5

D4

D3

OUT

1)2

1)1

DO

U2 Dl DO

v

i

! !

i i

r-JLJLJ

i !

i i

0

| 0 | 0

of the MFM

method.

IN

In

For the

DACK

ME

SCTRL

TC

TRIG

SEL3

SKI.

SEL1

SELO

M

. ON

I

NDEX

DRQ

2

' '

1

Used INT

FDD

TC

Trigger Selects Selects

Selects

ON/OFF state

INDEX

DRO

•__ —1

n

1

o

Model

3500,

only

written

in the FM

recorded

for

from

select

to

FDC.

from

in the MFM

data transfer between

the FDC is

signal

output

(motor

on) of the FDD 3 FDD 2 FDD 1

FDDO

of the

signal

from

the

FDC.

•

(MFM recording method)

side

0 of

track 0 (128 bytes/sector)

mode

and

rest

mode.

the CPU and the

output

enabled

is

enabled.

on

INTFD.

timer (555)

motor

the

motor

of

other

FDC.

tracks

is

are

-

59-

M

7.3 500

5-7.

Precompensate

Circuit

(Fig.

2)

KKITE

DATA

Set

the

counter

to

(Actually, slightly longer than 200ms.)

200ms.

PS1

PSO

0 0

1 1

WDATA-

8MHz

CLOCK

EARLY-

NOMAL-

LATE-

The

precompensate circuit

shift

before The FDC and the With

PS1 both LS163, When "H", LS163

sends

data

issuance

is set in the

PSO and PS1 are

counted

it

becomes

PS1="L"),

so changed". period

of two

FM

Not

0

changed

1

0

1

writing.

out the

bit

location

of

WDATA.

LS163. (See Table

up by the

"1110,

the

that

the

output

The QB

clock

output,

cycles.

MFM

Not

changed

-

LATE(125»is)

EARLY(125ja)

-

(Table!)

(Fig.3)

is

used

to

compensation rate

is

shifted according

the

value

1.) For

low,

it

will

8MHz

clock,

1111".

value

When

"1110(E)"

is

issued 125ns earier

however,

Value

compensate

to PSO and PS1

to

dependent

instance,

set

"1101 (D)"

and QB is

in

EARLY

will

be set to the

will

be

supplied

of LSI 63

1101 1100 1110

-

the

peak

this

signal.

on PSO and

when

to the

sent

out

(PSO=

than

"not

for a

Media

is

5-9.

Controls

calibrate

Above operations

1)

Control

READ

command

DATA<- DATA-*

2)

Control during

I

(or

FDC FDC

during

WRITE)

to

FDC.

SEEK command

HALT (waits

present.

during

are all

read

and

seek

and

(or

RECALB)

to FDC

I

for

interrupt)

Media

controlled

read,

is not

write,

via the

write

f

I

TC-»FDC.

HALT

(Wait

for

recalibration

Read'result

status

present.

seek,

and re-

FDC.

interrupt) H-">uit

is

from FDC.

read

by

staius

FDC.

5-8. Media detection

Insertion INDEX from

to

INDEX

of a

media

the

MFD.

make a full turn,

does

not

appear

on the MFD is

Since

it

takes

"NO

MEDIA"

within 200ms.

detected

200ms

is

detected signal

via the

for the

signal

media

-

60

tNI)

RtTKY

-

In the

tuation

because (Peak

case

is

further

there

shift).

of the MFM

increased,

are

three

write

Data

read

point

is

moved

method, need

as a

peak

data

cycles.

cycles

fluctuate

forwards

to

trace

shift

is apt to

as the

or

backwards.

cycle

flux

fluc-

occur

change

Polarity

Read

Write

pulse

inversion

waveform

MZ

3500

{VFO

Polarity

Write

When pluse Shown

circuit):

inversion

pulse

Read

the

output

on the

floppy

in (b) is two

Variable frequency oscillator

f~J

J

waveform

6.0

40 20 0 20 40 60

(a)

waveform

disk,

pluses

is

observed after

the

waveform

of

4jis

show

interval.

writing a single

in (a)

appears.

Advanced

Regenerated

Polarity

inversion

Advanced

Deviation intervals 8/^s,

the

before

or

peak

shift

pulse

peak

shift

—-| t— —•) j*-

in the

peak

point of the MFD in largest

shift

takes place

after

4/JS,

as

shown

-

H

j

I I

actual

*—

Delayed

peak

Cb)

Delayed

(c)

is

called

peak

operation

when a pluse appears 8/Js

in

(c).

shift.

are

peak

Since pluse

4ns, 6/JS,

shift

and

5-10.

VFO

1)

Purpose

circuit

String pulses

from

of

data

Data

String separate

the

FDD.

window

of

data

-

61

n

-

Data

from

when

read

is

used.

carses

the

that

take place

change.

the from

In

order

window

clock

or

data

portion

the

FDD.

For

to

increase read to

trace phase

during a floppy

n

must

be

this

purpose a window

tolerance,

changes

disk drive

in the

differentiated

the VFO

read

motor

circuit

speed

pulse

data

MZ3500

2) VFO

circuit configuration

The VFO

(1) (2)

(3)

circuit

Two

modes:

The VFO

SYNC

circuit

field located before

After suspention,

with

the

read

change

in the

that

may be

READ

DATA"

has the

following capabilities.

MFM and FM.

operation

the ID

the VFO

data

(timing

FDD). Fluctuations

seen

(peak

shift

are

—

»

h,

is

suspended

field

circuit

is

affected

ignored.

will

in an

Phase detector

during

and

data synchronize by a

individual

the

field.

speed

bit

VFO

Filter

k.

amplifier

Data

separator

circuit

^

Window

SEPARATED DATA

SEPARATED CLOCK

+5V

RtAD

DATA

-62-

Nomal

STD

AlMHz

_rLTLJT_r

B)QA)

MFM

Mode

1_

Eary

Delay

n

©

J~L

MZ3500

A 4M

B(QA)

FM

mode timing chart

C(QB)

D(QC)

WINDOW

Normal

j 1 [

1

E

F

L

O

P

F

L

1

1 1 1 1

1

1 1

Advanced

Delayed

Does

not

Q

O P

L

K

Q

O P

trace

± I

I

* ~

oinQle

density

~^~^~

~~^~~~

*

~—~^——^—

LJQUOI6

density

*"

0

/

0

H

8

«

/

0

\

/

o

-

t-

Q

-

^_t

u

TT

O

CTJ

a

U3 U

2

,—

^

UJ

s

..

o

5

S3

OS UJ

H

.

c o

(O

^

0

"c —

CO

02-

1 £

CD"

O

0

O

H

h

O

O O

O

cc

ca

U.

o

1

c

o

c

o

o ~ Q

U,

0

I o

-

c-

D

o o

-

Q

U

00

(J

-

W

w

T—

1

U,

CO

Q

-

to Q

10 UJ

U, U-

a.

5

/

* \

"o

ro

"O

(U

£

<u

•£ O

"*"

6

i

ui^

<u

J:

- ^J

2 r~

CL

2

„ ^

•

,

s

u

Q. J2

I

00

of

"S'o

1C

i. "6

O 4J

r

O o

<—

0)

"£

•

>»-

U.

s

u. u.

a)

U

lO

1/5

2

*"

10

U?

w

U

L-i

o

*#-

.2

73

QJ

O

Csl

m

lO

0!

00

O

^"^-^

to

••

Reverse

IN

^—^_^

side

VO

•~"

M/asoo

Track

AA ( 1

i

m

media

0,

sector 1 information

L'

00

/

M

00

HF

(SBACIS)

02c00

(Fig

1)

7

1 1 | 1 i 1 I 'T

0 4 i 0 0 ! 48 '. OO1 4 8 ! 041 02 '< Oo! 01 ! 01 '

i i i ' i > i > * i

I 1 1 1 1 i I . ; , ,

IM

J v

1

No,

of

sectors

1

Start address

' 1 r u U S I IM'

I

SJ"L

—

tor N

I

r ;

10

No

of

sectors

f

0 .

Single

1 .

Double

SIDE

=

No of

data

transfers

0

track 8 sector

* 78 F

Volume

name

0 1

01

Sector

other

side)

01

i

i ,

N No of END

than

front

side,

than

front

02

Track

SIDE

sectors

density,

.

Side 0 (front

1

Side 1 (reverse

INT=[IOCScapacity/1k]

FF

10 11

+

Tr

Track

Error

FI-

3Ck

No 1

Mep

FF|

No 2 m

(Bad

18

t

Diskette

Treck)

BOOT

10 j FF

track

side,

track

+1

FF

Type

SH/DD(M,ni)

<-C

DH/DD(M.m)

0.

IF

20 SC

For

FLOAD

command

SUB

IOCS

3D 7F FF FF

I

Fail name

cc M

A,r,Ar.

FF

No

ALOAD

80

File specification

01

With operand

(8

bytes) Expander

.4 (3

command

only

Channel

A

(<•)

B

( I )

bytes)

Drive

Volume

(8

bytes)

NO

1

'

1 1

name

-

66

-

ALOAD Status (8

bytes)

Contents

of X When used These three

34

35 36

3b>tesfj$!l

00 01 23

When used

34

I)

A

B C

line

No

label

(Sbytes)

register

for the

line

bytes

are in

for a

label (Wight bytes

f

? 7

number

effect

3C

F

All "F"

when

is

not on

(when line

are in

ALOAD

No 1 23)

effect

andreseare)

command

o Map

/ 1

2

/

3

/

information

/- x

22 23 24

75 76 77

0

track 9 sector

/ 1 7H

/ &0H

1

FFH

\ FFH

J

4CH

FFH

1

FFH

iy 7 EH

/ FFH

129 130 131

151 152 153

0

track

10

FFH

I

71!

FFH

sector

128

blocks

by one

sector. OOH-7FH 80H:

End of

FEH:

Links

and

block

are

controlled

link

to

starting

number.

M7

350?

map,

\

\ 126

\ 127

\128

1

^

FEH

FFH FFH

25

00

01

MAPNa

Block

Starting block number (directory)

NO

02

Indicates

the

byte

•

from

the top of

29

30

31

32

FF

01

FF

position

directory.

H

-

67

-

MZ3500

o

Block number allocation

The 1

block

program

= 2K

and

data

bytes

(8

areas sector)

are

located

after

Track

2

Each

track

2

I

38

39

track

1

3 5

3

sector

is

blocked

Front

BO

Bl

B4

B5

B144

6145

B148

B149

1

block

2Kx

in the

(Double side)

Block

No

152 =

304K

following

manner:

2 sec tor ' 4 6

B2

B3

B6

B7

B146

B147

B150

1

Reverse

B151

block

track

2

3

I

38

39

(Single

2KX

sided)

Block

No

Front

BO

Bl

B2

B3

B72

B73

B74

B75

76=152K

o

Track

0

AA

Represents

system

media

SECTO

R

NUM

BER

.

_ 0

Single density

1

Double density (other

0

SIDE Nosof

• Sub less

Side 0 (front)

=

1

Side 1 (reverse)

data

transfers

IOCS

can be

than eight blocks,

13

15

sector

1,

Sector 1 information

14

16

sector

(CP/M)

5

SIDE

SECTOR

t

Drive

specification

the

(•

TRACK

......

unit

20

SECTO

R

TRACK

(front,

= INT

[IOCS capacity/1

divided

into

the

block that follows

Track

0)

than

front.

either blocks

NUM

BER

SUB-IOCS

Track

K] + 1

If

divided

N

BOOT

0)

SECTO

^1

NUM

BER

to

Load

i i

i

address

Start

10

i i i

address

PATAT

*ANSF|

ER

NU

MBER

-TRACK

1KAt

1

*

50

SIDE

51

SECTOR

SECTO|~

R

NUM

BER j j

15

N

I

T?F%!

Indicates

the

end

\

-

68-

6-1. General specification

Input/output No of

format

channels

Code used

Baud

rate Transmission Synchronization

Communication control procedure

Data

LSI

used

system

method

format

RS-232C

1

channel

JIS

110 to Half-duplex Start-stop

Non-procedure Stop

even 8251

(Programmable

6.

R232C

bit

serial

input/output

7-channel/JIS 8 channel

9600

bits/sec

bif

1/1.5/2,

or odd

AC

or8253C-5

with

parity.

interval Timer)

or

MZS500

INTERFACE

without

6-2. Data transmission

7-bit, with

parity

7-bit,

without

8-bit with parity

format

parity

2°

21 22 23 24 25 2

i

\

v

„ _

Start

bit

V

XV X V X '

Start

bit

V

' V ^ ^ _

• w •

Start

bit

Data

bit (7

Data

bits)

bit (8

bits) Parity

6

j

v__^___/

Parity

bit

Stop

bit (1 or 2

bit

Stop

bits)

bit (1 or 2

bits)

8-bit, without

parity

Example:

Stop

v

Tr

y Y

Start

bit

bit of

Data

7-bits,

even

parity, 1 stop

Start

bit

preceding

data

7-bit

-

data

7)

bit

(26H)

-

bit (8

bits)

Stop

Parity

bit (1 or 2 bit

bit

Stop

bit

,

Start

bit of

succeeding

data

MZ3500

6-3. Block diagram

6-4. System switch

of the

interface

functions

Control

signal

Peripheral

ON

Causes

an

SW5

ER

during data Always

SW6

on

Causes

SW7

PO

data

6-5.

8251AC

There

are two

(1)

Mode instruction: Defining

meters,

(2)

Command instruction: Defining

actual

1)

Definition

•

Baud rate

•

Character

•

Even/odd/off parity

••Stop

bit

"Corresponds

error when

signal

is low or

output.

high when power

to the

main

on

error when

signal

is

output.

controls

control

such

as

operation,

of

generation operational parameters

size

to

the

open

unit.

during

words

unit,

stop bit, etc.

such

the

for the

as

send/receive enable, etc.

high

assignment

channel command

is

general

ER

signal

The CD while

data

would

not be set

when

the

function

the

host

Polarity

8251

AC.

operational

status

of

BASIC.

OFF

is

disabled.

signal

is set

output,

echo-back

is

selected

computer.

is

inverted.

words

high

but

high

for

used

para-

for

c

START

8251AC

internal

mode

reset

instruction

-

72

-

2)

Data

output control

SKNU

Command instruction

(KTS,RXEN,TXEN)

»-

8251

AC

Set

counter (200ms)

8251

AC

"L"->KTS

MZ3500

Stop

Output data

8251AC

to

ERROR

The

8251 send

The

8251

CTS

goes

CTS

will

.becomes

101

data

AC

low. Therefore,

be

empty.

when

would

not

checked when

/

CTS

goes

output,

the

unlessv

state

buffer

low.

of \

I

-

73

ERROR

101

-

3)

M/3SOO

Data

input

control

RCV

Command nstruction

(

ER.RX

Read /Clears Vthe

start

8251

one

data

the

data before

of the

DISLN)

AC

receive

N

command

/

8251

/Error \Data

AC

input

reset

\ disable/

Resets

error

DTR

high

Command

( tK >

ERROR

Waits

for NMI by

the

RXRDY signal

by

setin

instruction

8251

AC

Command

instruction

(RXEN,UTR,TXEN)

-

8251

AC

8251

AC

, N

/

Data

input

(

Data

\" L

enabled

output

enabled (echo-back,

"-»DTR

selected)

-

74

ERROR

-

MZ

3500

6-6. 8253

Baud

rate

output

of the

baud

rate

relation

between

8253

input

8253

Mode set: Mode 3(rec'angle waveform

Control

Transmission

Data

set

Carrier

Ready

Equipment

Paper

Controls

of

this

8253.

is

1/16

frequency:

signals

Signal

name

enabled

ready

detect

ready

out

interface

The

of the

the

8253

will

be

8251

is

input

clock

output

2457.6kHz

Symbol

CS

DR

CD

READY

ER

PO

determined

by the

configured such

and has the

clock

and the

rate

IN/OUT

-*

Peripheral

—

Peripheral

—

Peripheral

—

Peripheral

«-

Peripheral

<-

Peripheral

clock

that

its

following

baud

rate:

generator)

When

high,

When

low,

Goes

high when power

(SW6-ON) (SW6-OFF)

Data

output from

(ON)

Data

(OFF)

Waits

NOTE: A maximum

Indicates is

sent

from

off.

(SW7-ON) (SW7-OFF)

Baud

1

2400 4800 9600

data

input from a peripheral

data

input from a peripheral

High

at all

times

high only when data

the

interface

output

from

for

data

output.

of two

the

peripheral

interface.

an

error

an

is

state.

that

Causes

Goes

the

Causes

rale

1

1 0 .t -

300

600

200

is on to the

when power

the

interface.

bytes

is

This

if set

error

if set low

8253

Output

Function

is

enabled.

is

disabled.

interface

is on to the

is on

output.

is

enabled.

are

output

ready.

It

results

signal

will

be

high during data

during

frequency

1760Hz

4800 9600

1

9200 38400 76800

153600

unit.

interface

after

the

signal

in an

error

output.

if low or

invalidated when

data

8253 Parameter

unit.

goes

from high

open when data

the SW5 is

1

3 9 6.3 6

51 2 256

128

64 32 1

6

turned

to low

6-7.

Description

1)

UPD8251AC

The

UPD8251A

of

LSI's

(Programmable

is a

USART (Universal Synchronous/ Asynchronous Receiver/Transmitter ly

designed The converts serial ferred CPU any

,

SYNDETandTXEMPTY.

for

USART

it

into

data

is

to the CPU

can

monitor

time

(data

data

communication.

receives

serial data

received

after converting

the

transfer

parallel data

from

current

,-eatures

•

8080A/8085A

•

Synchronous/asychronous

•

Synchronous operation

5 — 8

bits Clock rate: baud BREAK

Stop

bit: Error start Automatic

•

Baud rate:

•

Full-duplex

Double

•

Error detect

compatible

character

rate

x 1, character 1,

1.5, 2 bits

bit

detection

break

detection

generation

DC - 64K

buffer

type transmitter/receiver

Parity, overrun, framing

•

Input/output

•

N-channel

•

Single

•

Single

•

28-pin,

•

Intel

8251A compatible

MOS +5V phase

plastic

TTL

supply

TTL

DIP

compatible

level

Communication

that

from

before

transmitting.

an

external

it

state

error,

and

operation

x16,

x64

and

operation.

baud

clock

was

the CPU and

circuit

into

parallel.

of the

USART

control

Interface)

specifical-

Also,

and

trans-

The

signal

of

at

1)7-1)004 8 »

RESET

-

75

-

configuration (Top

O »•

Dsko

m

t

rscx — x:

k'l so* c

Internal

Data

bus

buffer

Read/ write control logic

*

MOOhM

controller

data

View)

Block diagram

8

„«.

8

^_

8

^

V

bus^

28

<

»OD1

3?5 PORTS'

422-0

-i-2—XDTXEMPTY 3*12-0

Transmission

1

t *

Transmissic

control

Reception buffer

(

S -• P )

t

Receiver control

>n

_

'

34

OTXC

1

DSR

CT3

SYNDET TXRDY

X>TXE

BD

HI)

M Z 3500

DO~D7

Data

RXD

Receive

WR

Write

RD

Read

C/D

Control/Data

CS

Chip

DSR

Data

DTR

Data

RTS

Request

CTS

Clear TXRDY TXC TXE

RXC

SYNET/BD : SYNC Detect/Break Detect

2)

UPD8253C-5 (Programmable

The fically

It

consists under a maximum counter rate operational modes

range

Features

•

Z-80 compatible

•

Three

•

DC-4MHz

•

Programmable

•

Choice

•

N-channel MOS,

•

Single

•

Intel 8253-5 compatible

configuration

.

Transmitter

.

UPD8253-5

designed

of

three

of

microcomputer system

sets

of of

duration

of

binary

+5V

Bas

(IN)

Select Set Terminal

to

Transmitter

Transmitter Receiver

is a

programmable

for the

sets

are

programmed

16-bit

counters

count

rate

six

operational

counter/BCD

input/output

supply,

24-pin

(Top View)

Data

(IN/OUT)

(IN)

Ready

to

Send (OUT)

Send (IN)

Ready

Clock

Empty

Clock (IN)

Interval

8-bit

microcomputer

of

16-bit

of

timing

DIP

(IN)

(OUT)

(IN)

(OUT)

Timer)

counter/timer

counters

4MHz.

Timer

to be

used

control.

modes

counter

TTL

compatible

(IN/OUT)

speci-

system.

that

operate

and six

for a

and

timer

wide

UO

O

wl —

»<:

AO

1

Al >

c- ^

Block

diagram

VV

Counter

# 0

Data buffer

bus

AA

v-v

_t

Internal

Read/ write logic

£

^

Control word register

— /" '

**w 1

1

D7-DO

Data CLKN Counter Clock Inputs GATEN Counter

OUTN

Counter Outputs

RD

.

WR

Write Command

CS

Chip

A1~AO : Counter Select

Vcc GND

Read

. +5

.

Ground

/«-

-N ,V

\r

A^S

S —

Bus (8

Counter

Select

Volts

Counter

K]

Gate

# 1

t

Counter

# 2

t

bit)

Inputs

•«

t 1 KO

<l

C.MtO

'

*-"n

< C 1 K 1

< OA1 ^ 1

»-()l

*- Cl K2

«

GA1L2

KHT2

or

Data

o

I 1

.VCC

-

76

-

8251

M 2 3500

8253

8251

chip

address[0001/xxxx]

IN

Uix

OUT)

8253 chip

address[0010/xxxx]

IN

#UxH

OUT#|

2XH

CLK

DSK

DTK

CTS

Rl

S

TXD

TXRDY

TXE

TXC

RXD

RXRDY

"RXC

SYN/BD

CLKO GATED OUTO

CLK1

GATE1

OUT1

CLK2

GATE

OUT 2

IN

OUT

1

N

OUT OUT

N.C.

2.45MHz DATA DATA TERMINAL READY CLEAR REQUEST TRANSMITTER

clock

SET

TO

READY

SEND

TO

SEND

DATA

READY

CS

PO

(MPER

CD

RD

SUT),

ER

N.C.

IN

TRANSMITTER

IN

RECEIVE

OUT

2

IN

N.C.

IN IN

OUT

IN

OUT

RECEIVER

RECEIVE

2.45MHz

Vcc

To

TXC,

2.45MHz From OUT2

MUSIC

2.45MHz

Vcc

To

GATE

CLOCK

DATA

READY

CLOCK

RXC of the

1

8251

OUT

SD

To

3iil>CPU

8253

0 of

OUT

8253

of

INTO

INT

TO

MAIN

SOO

fNTR=L(FROM

TO SUB

STK=

FROM

POWER

-SIW(

FROM

(L)

SUB

ON

RESET

IORQ-WR

MAIN)

KEY

of

SUB)

INTO

H

L H

-

77

-

M

7.

3500

7-1. Printer interfacing circuit

AS 4 • AS 5 AS6 • AS 7

AR

Chip

RI)

I

ORQ

Al

Z80 AO SUB

CPU

-J

7.

I

)fi i >de r

rs.

-^jp

3C

r-—

°^

*-!-

cf^ 1

cjX i—

PRINTER INTERFACE

SO3

CS

8255

PA

0

1

PA

2

H^ ©

3

PA

4 5

PA

6

PA

7

PC

5

PC

6

^o^l-X}—^^^

PC

7

PC

0

CP^»

rv_

• ^ —

"N S1W

^

RD

°

WR

Al

A

PA

° PA

H/ ©

C|^»

ts^

i^^ —

(g)

rs_

"v*~i

1 "No

(3)

ol ^^

Op)

ffi\ STRDRF

DA1A2

"A^A3

DAT

16

DATA?

D \TA S

ACK

11 13 15 17

21 23 25 27

'arallel

No.

1 3 5

7

9

19

interfacing

Signal

name STROB DATA

1

DATA

2

DATA

3

DATA

4

DATA

5

DATA

6

DATA

7

DATA

8

ACK

BUSY

PE

PDTR

SYSRES

signals

-

PRINTER

-PRINTER

-

PRINTER

•

PRINTER

-

PRINTER

-

PRINTER

-

PRINTER

IN/OUT

,

DSO

_

DS1

^

DS2

DS3

DS4

^

DS5

DS6

v

^

DS7

Data

Indicates When When When Reset

is

transfered

output

the end of high, high, high, signal,

PC

1

L_

~0<xr

LS244

to

printer when STROB

to the

printer

character

it

enables

to

it

indicates

it

indicates

normally

-

78

high

-

1

PC

2

receive

paper

the

input

data

empty

SELECT

o^l n

I

^J .^ ®

/// ©)

*

Function

or

function

mode

2,4,6,...

*

Ahnwp

is

high.

input

(receive

28areGND.

nin

numbers

enabled!.

are of the

i

EU-

PDTR

model-3

7-3. General description

The

8255

is

used

for the LSI to

face.

The

8255

can be set in the

/PORT

A:

MODE

I

PORTB: MODE

C:

Output

74.

Data

transfer

timing

BUSY

ACK

(

8255

A

v

PC-7

DATA

STROBE

of the

parallel interface

control

following mode.

0

1

J

the

parallel inter-

Because it

uses

ACK

signal

it is not

interrupt

is

possible

for key

latched

to

directly

processing

by

means

sense

the ACK

and

RS232C

of the OBF pin

signal

input,

the

function

as

7-5. General

(M1N)

PRINTER:

330P, 331P, 332P

*

Broken line

CE-330Pand331P.

'For detail

printer.

description

l^s(MIN)

MZ-1P02, MZ-1P03

in the

of

timing,

of

control

above

refer

software

Set

the 20

STROBE

Set the 20

figure

to

second

OUT

second

CE-

represents

Manual

counter.

timing

provided

for the

with

-

79

-

7-6.

M / 3500

I/O

port

8255

ON SUB CPU BUS

map

IN

OUT

8255

chip

address(0011/xxxxj

Group

A: B:

Mode Mode

Group

PA7

PA6

i'A5

I'A4 I'A3

Output

PA2 PA1 PAO

OBF

ACK

output inputi

PC7

1 0

PC6 PCS PC4 PCS

1NTR

PC 2

PCI

PCO

PB7

PB6

O

3

PBS

Output

PB4

PBS

PB2

PB1

PBO

DATA8 DATA" DATA6

I)

AT A 5

DATA4 DATA3 DATA2 DATA1

ACK

STROBE

MUS

NOT USE

ACKC

STC DC

P/M

SRDY

CLK Dm

C2 Cl CO

STRB

T-SET

J

1C ,

sustain

Printer

Keyboard

CG

selection

Sub CPU

Clock

READY

INPUT

PORTC74LS244

74LS244

port

address[0100/xxxx]

OUT

IN

#4X

CDS7D

CDS6D

CDS5D CDS43 CDS33

CDS2D

cosn

CDSOD

HLT KEY

STK -i

DK

J

PUTR

PE

BUSY

Reads

the

8255

output

or

timer output.

Keyboard

Printer

OBF

(PC7)

-

80-

8-1.

Clock

1)

Schematic

circuit

8.

OTHER INTERFACES

M 2 3500

2)

Clock

timing

READ mode

mode [ mode

Cn(CO~C2)

STB

/ \ /

WRITE

mode mode

DIN

Don't

CLK

DOUT

HOLD . READ

0 X 3 Y~l

HOLD

care

X

Tens

digit

^Ones digit

Tens

of

seconds

digit

T;

10 Ii2 u "

HDH

*

l«"-.r

of

seconds

of

seconds

Tens

digit

1

Tens

of

month*

digit

of

month

'

SET i HOLD mode I mode

-

8)

-

MZ3500

3)

^PD1990AC

Block

diagram

OK

O

Command specification

C2 C1 CO

000

0 0 1

0 1 0

0 1 1

Command

Register

hold

Register

shift

Time

set

Time

read

Input/output

Example:

(LSB)

9

«-

Seconds—'

format

In the

4

Holds Data Data

preset Data

is

read

case

L(\/|j

Description

40-bit

S/R input/output of the

40-bit

to the

time counter.

in the

time

to the

40-bit

of 10

o'clock,

5

2

—I

nutes

S/R is

counter

S/R.

25

Ln

minutes,

0

oure

1Hz

[LSB]

ILSB]

[LSB]

1

_)

L_

DOUT

Output

49

seconds,

0

of LSB

—I

Dey

July

3

Data Not

Possible

Not

30th.

Shift

possible

7

Won

!Onth

(MSB)

J

Data

Shifts

with

retention

the

Note

in

synchronization

clock

-

82

-

8-2.

Voice input/output circuit

PD8255

Music

output

•

Tonal signal

•

2SC458

•

»

GETE1

OUT1

Sustain

PC4

emitter

2SC458 collector

Speaker

output

waveform

u

-Tlj

J

mmmil

1

-

83

-

M/3500

83.

Expansion

1)

Options

2)

Expansion

Signal

and

expansion

MZ

1K01

1001 1D02

•1D03

-1S01

-1S02

•1X02

-1P02

-1P03

-1P04

CE-330P

-333P

-33

1M

-330X

MZ-1F02

-1F03

-1R03

-1R05

unit

assignment

interrupt

Options

by

(See

units

not

requiring expansion

JIS

keyboard

14"

medium resolution color

12"

high resolution

1

2"

high resolution color

14" CRT

tilt

stand 12" CRT Light

80-character

Color 80-character

136-character

Optional Plotter

Optional

Graphic

slot

pen

injket

board

tilt

MFD

MFD MFD

stand

pnnte

printer printer

3-(2)-4

printer

drive

for

unit

green

CRT

unit

(single deck)

interrupt)

CRT

MZ-1E01 RS232C

-1E02

GP I/O ©

•1E03

SFD 1/F

-1F05

SFD

-1R06

RAM

1/F (7)

unit

DRAM

BASIC(

SFD

CONTROL

control

32K

mask

8K

mask

Main bus

VOICE

signal

ROM

ROM1

ROM2

ROMS

ROM4

INT1

INT2

I

NTS

INT4

•

CPU

line

SLOT1

SLOT2

SLOTS

SLOT4

L

-84-

8 4

System

SW1

(DIP

SW)

(User

operative

through

the

cabinet

M 7 3500

bottom)

No

is

output

is

outputted

or

open

in an

ER

becomes

as

long

side

cause

output

inverted

in

capital

small

will

be

will

be

Description

CE332P

MZ1P02

IO2824

CRT

(MZ1D02. MZ1D03)

CRT

(MZ1D01, MZ1D06)

for a

decimal point

for a

decimal point

ER

signal

error

during data output

invalid

as

power

is on to the

if the

when

for the

letter,

and in

assigned

data

echo

the PO

above but in

capital letter when

when

high

leter

output

back

function

signal

is

small letter

the 200

main

However,

high

raster

is

#47 pin of MMR

£48 pin of MMR

#51 pin of MMR

#52

pin of MMR

ToCTS,

DSR

of

the

8251

ToCTS

of the

8251

#54

pin of MMR

(FDD

P/M

signal

(To A3 CG)

Signal

name

1

2

3

4

5

6

7

8

9

SW1

SW2

SW3

SW4

SW5

SW6

SW7

FD1

(SW8)

P/M

(SW9)

Function

Printer

select

CRT

select

Choice

of point output format

decimal

RS232C assign

Key

shift mode

setup

Choice

of CG

for

display

Position

ON

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFF

Polarity

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

SW2 SW1

ON ON

OFF

ON

ON OFF

OFF

High

resolution

Medium

resolution

A

period

A

comma

Low

state

will

result

The

signal

CD is

high

unit CD

goes

high only during

it

would

not go

on the

host

An

error

is

during

data

Polarity

is

Normally when

shifted

Normally shifted

3500

CG

CRT is in use

2000

CG

CRT is in use

10

Dip

switches servicing fore

the addition, 330M

or

DIPSW(A)

No

1

2

3

4

DIPSW

No

1

2

^=—

(A) and (B)

the MFD or for

user

is not

these

switch

331M

is

used

located other

supposed

must

be

as the

expansion

machine

to use

used

Signal name

SEC

(SW1A)

FD2

(SW2A)

FD3

(SW3A)

SRQ

(SW4A)

44 pin of MMR

56

pin of MMR

58

pin of MMR

Bus

request

to

sub-CPU

(B) Signal

name

SRES

(SW1B)

SW2B

SUB CPU

reset

signal

SUB CPU BUS

select

signal

on the PWB are

service

these

switches

when

either

MFD

\

used

and

the CE

there

for

In

t

1

OFF

ON

OFF

ON

OFF

ON

OFF

ON

*1 *2

Used three switches sub condition

2

OFF OFF

ON ON

OFF

ON

Test

program

Provided

read/write

for an

CPU

operated

under a normal

=T

3

OFF OFF OFF OFF

ON ON ON ON

for the

test

individual

are

WhenSH When

Use Use Check Check

is

loaded

and

test

of the MFD

is

carried

test

of the CPU PWB

turned

off

independently

situation

in use

DH in use

— —

of the

CE330M

of the

CE331M

mode

*1

mode

*2

executed

out for the

altogether,

To be

as an

expansion

as an

expansion

interface

expansion

When these

it

makes

used

in th ON

NC

unit

The

unit

the

MZ3500

1

OFF

ON

OFF

2

OFF

DIP

SW(A)

OFF

ON

DIPSW(B)

3

4

ON

1

ON

2

Switches single-sided

Switches machines disk drive.

Switches

are set in

that

are set in

this manner before shipment

minifloppy

' '

disk drive.

this manner before shipment

use the

double-sided

this manner when

•

minifloppy

the SH is

of

machines this

of ,

(

used

for the

us the

My-it^n

11/171540'

optional

Pn^41

vv"=/n

MFD

ON

OFF

ON

X

\(f Can be in

OFF

ON

><^

either state

ON

OFF

ON

OFF

ON

OFF

Switches

Test

mode

Test

mode

Individual

are set in

* 1 "2

CPU PWB

this manner when

test

the DH is

used

for the

optional

MFD

-

86

-

1.

BLOCK

9,

DIAGRAM

POWER

CIRCUIT

MZ3500

DESCRIPTION

A.

+5V and

1.

Functions

a.

Supply

b.

•

Nfilter.

c.

Change

d. The

e.

For

2.

a.

Overcutrent protect (control/protect)

voltage

and

sent

current

detector

circuit.

Next,

the

in the

switching regulator

in the

sensed

by the switching regulator after being located

in the

voltage

to a

signal

ing

regulator

switching regulator.

prevention

for

stopping

and

it

makes

shut

off

+12V/+5V

Description

When

an

causes

to

current

detector

increase

the Q3

voltage difference between

+12V

is

first

out to the

provided

voltage

overcurrent

increase

is

switching

control

constant level.

from

the

through

of

overcurrent,

the

oscillator when

the

switching regulator

supply.

of

each

the

resistor

collector current, for, there

supplies

rectified

switching

in the

converted

and

regulator

circuit

circuit,

oscillator

the

control

block

is met in the

voltage

R1,

the

in the

regulator

overcurrent

to the

sent

out to the

output

and is fed

amplified

for

maintaining

is

supplied

circuit

the

protect

an

overcurrent to

circuit

+5V/+12V

at

both

ends

which

in

emitter

rectifier

via the

+5/+12V

voltage

back

in the

the

to the

for

driving

circuit

halt

in

circuit,

of the

turn

causes

arises

and

base

(Block

circuit

over-

protect

output

noise

is

to the

amplifier

output

switch-

the

is

used

is

met,

order

to

it

over-

to

larger

of the

diagram)

b.

transistor tor of SR it GND also activation the + 12V

Oscillation

As the porarily which voltage increases. Then, be activate again. Q2 voltage off the transistor Next, voltage activation. alternately

C5 and C6 are

action

Q3.

increased

level

makes

transistor

the Q1

transistor

charged

emitter

owing

makes

at the

the

of the

supply,

circuit emitter

Q1 is

drops

in

turn

the Q2

through

voltage starts

is

temporarily

transistor

Q1

emitter

as C5 is

increased

In

turned

of the Q1 and Q2, and

Q2.

This

makes

to

activation

the

oscillator

point

"a" to

switching

transistor

Q5

inactive,

voltage

active,

close

to the GND

makes

Q2

base

voltage comes

R6, and the

With

activation

dropped

Ql,

which

voltage.

charged

this manner,

charged

by R5, it

which

puts

on and off to

through

the

gate voltage

of SR.

voltage dropped

stop oscillation,

regulator stopped

Q5

oscillation.

and it

is at

almost

the Q2

inactive

of the

to

drop

by

causes

the

transistors

keep oscillating.

R5 and R6 by

discharged

Witr,

shuts

off the

GND

base

level

by

means

and the Q2

to

rise

as C6

transistor

and the Q1

means

of C5, to

to

makes

transistor

Q1 and O2 are

through

of the

thyns-

jctivation

to the

which

by the de-

This

causes

+5V/

level

whe-

voltage tem-

of C6,

emittei

begins

Q2

starts

to

Q2, the

base

shut

increase

the Q1

Ql

on/off

Ql and

the

base

into

to

M

7,3500

Switching

regulator

Q5

(Switching

voltage

control

regulator

circuit)

« VR is

• D3 is

and

constant

the+5V or+12V adjusting

provided

to

discharge

current from

VR.

Cj

after power off.

+

5V

or

-

88-

c.

Power

switching

As

the

signal

from to Q6 to voltage is form switching operation oscillation supplied produces and the the is transistor create which deactivation

3.

Alarm circuit

(Alarm generation

change

to

appear

cut by

D1),

so

frequency.

to the

emitter

smoothed

coil

L2. The

reference

used

voltage

to

control

Q9. The

Tr3

inactive

supplied from Tr1-R2-VR1-D3.

of

Tr3.

circuit

the

oscillator

current

to the

on the

base

that

the

transistor

in

As Q2 is

side

of the

voltage

the current

by the

circuit)

through

circuit

composed

for the +5 or + 12V

emitter

supplied

delayed

is

amplified

transformer

of Q5

synchronization

switched,

transistor

current

T2. it

(one

of

components

Q5

begins

the

capacitor

of D4 and VR1 is

supply,

flowing

from

Q9 is

C1 and C2

It

goes

through

causes

to

with

current

Q5,

which

to the

used

voltages

high

M23500

Q7

per-

the

is

C1

to

with

When power

and

C2 are

D3, so

that

times

after

Timing chart

SW

+ 5V

PFD

turns

supplied

Tr2 is

power

off,

kept

off.

the

to the

active

voltage

accumulated

base

of Tr2 via Tr1 ... and

and Tr3

inactive

for

in C1

some-

-89

-

MZ3500

10.

MZ1K01

KEYBOARD CONTROLLER CIRCUIT DESCRIPTION

10-1. Specification

1)

Input

Buffer

Capacity:

•

Key-in

•

When

2)

Rollover

• 2 key

•

Simultaneous

3) Key

15msec

(Indicates

signal

finger

4) Key

15msec (allows

5) DEF Key

Twenty the

[

6)

Handling

See

7) Use of the

the DEB

Push

start

8)

Handling

COPY

ESCape

BRK

64

bytes

data

is

supplied

affired sent

(Entry

even

ingnored.

5msec

CTRL key. DFK1-DFK10 DEF1-DFK10

- - -

to the

an

overflow

to the

CPU.

rollover (exemption of the

second

if

more than

depression

bounce

(Key

spec

unstable

does

not

turn

from

the

key.)

(norma),

definable keys

(DEFIB-DEF10B)-

the

code table.

for key

of

functional

CTRL

20msec

in

key.

the DEB in

running.

of

special

command: CTRL

CTRL

key-in data already sent, before being

key to

of

keyboard

written

to the

CPU, byte

is

detected,

key

one key is

is

5-10msec)

state

as

off

immediately after

bounce)

are

(DEF1A-DEF10A)

conjunction

(DEF1B-DBF10B)

symbols

discriminate

conjunction

codes

| 1 J

control

input

buffer

by

byte.

the

in the

CTRL mode)

depression

pressed

of

more than three

shown

in

Fig.

(max),

available

in

combination

with

the

and

RUN and

with

the

(ten key)

first,

overflow

can be

at

same

3-2

releasing

CTRL

graphic symbols

CTRL

and is

code

accepted

time.)

keys

that

key

of

with

key

CONT

of

key to

is

11)

One-step

12)

Mode

13) REP

Key more than during

the

accepted.

depression

commands

LMU

/

LML)

o

UMU

4

pft/in

"7 .

PMH

n .

PMn A

PMH

n -

CMU K.

PMH

i

r*Mn

r\ -

PMH

c

indication

Acrn

repetition

0.64

key

same

time,

This

of

uior

rnlNI

INrU USING

(jU

pr\ci

Kb 1 UnN

Lib 1

At

ULUbt

n

nrUnMA K.hY

i

OAH

nhAU

CA\/C

on

LED

i

nr^w

will

take place when

second.

repetition.

an

rule does

more

than

T

I U

ID

rrn

ATA

IN

Entry

When

alternate

not

three keys.

1 fF

of

two

key

apply

a key

other

keys

entry

depressed

keys

is

permitted

are

depresssd

will

to

simultaneous

for

at

not be

9)

PRO/OP

Sent

to the CPU

changed.

10)

HOME

CTRL [ HOME]

key

after power

[HOME]

on and

Returns

display screen.

Only

the

when

PRO/OP

home after clearing

cursor returns home.

is

the

-

90

-

10-2.

Single

Key

key

Key

/

search

entry

MZS500

timing

Bounding

STROBE

RETURN

DATA

Two key

Key

STROBE

RET

OUT

entry

1

2

n n n n n n n

1

Strobe

*~5.5ms

M 5ms -»

cvcle

n n n n n

/A"

n

n n n n

-5.5ms—M—•6.5ms —M—5ms

n

n n n

—W

15ms

n n n

M

15ms

n

15ms

n

10-3.

Key

1)

DATA

(1)

OUT

DATA

(2)

OUT

-

serial

Data format

Key

transmission

-» CPU

Key

procedure

2s 2

s

DATA

Parity

22 21 2°

Command

Parity

All

AM 4 bits

nine

bits

-

91

-

MZ

3500

•

Command flag:

data.

"1"

data.

•

Data: Positive logic (negative logic

•

Parity:

2)

•

D(K):

•

ST(K): D(K) strobe signal. Also

•

ACK(C): Acknowledge

•

D(C):

•

ST(C):

3)

Key

•

Keyboard

• As the

• If the ACK (C)

Odd

Interfacing

Output

interrupt

Output D(C)

Protocol

to sub CPU

interrupt

sub-CPU detects a next strobe (STK) after going

into

the

final

parity

the

keyboard side when

keyboard

was

detected,

transmission

"0"

when

it is a

parity

up to 27 bit

signals

CPU

data from

to the

CPU.

Also

transfer

interrupt

signal.

data

strobe signal. Also

interrupt

to the

sub-CPU data transfer tapes place

applied

at

routine,

bit,

and the ACK (C)

signal returns

controller

the

error.

same

when

succeedeing 8 bits

command

the

signal

use for the

from

the

keyboard side.

every

signal

it

read data

the

check-sum

accepts

it.

data

keyboard.

CPU. Positive

are a key

or a

graphic control

on the

cable)

from

the

correction flag.

Positive

use for

form

disable

use for

word

with

Unless

is

sent again assuming

Active

the

Active

data

Active

(STK).

(K) as far as the

signal

is

sent back

is

correct.

normal

timing,

the ACK

level

H

L

signal

logic

H

logic

with

to

the

•

Case

when

the

error data

receive

data

properly)

1)

When

parity

error

2)

When

the

sub-CPU

or

when

NMI is

applied

3)

When

an

error

is

(STK(K)) When sent

again

this

periode buffer buffer.

•

When

code transmission key

SUB

CPU TO

•

Basically

•

Data

•

Return acknowledge pluse:

• KEY TO

a

one of

until

are

overflow,

a key

is

inserted

buffer

KEYBOARD

the

is 3

bits

CPU

due to

above

received strobe

key

buffer

in the

of one

contents.

same

as the

plus

parity

(80C49,

link

is

established.

is

found

is in

execution

during

detected

noise.

conditions

correctly.

in the key

entry

will

overflow

area

key-in data,

above

bit.

Parity

Z-80)

(sub-CPU

after

data

in the

is

detected, data

buffer.

not be

is

detected a KBOF error

vacant

cases.

OK . .. STK + DK

Parity

NO ... STK

CPU

not

the

check-sum test.

of the NMI

tranJ.jj,

couting

Key

entries

Should

stored

immediately

without

enable

routine

of

strobe

will

during

the key

in the key

clean

'~ "

only

level

to

be

after

D(K)

ST(K)

ACK(C)

CPU ->• KEY

D(C)

ST(C)

ST(K)

n__TL_n

12.5

32.5

SUB CPU I

INT

17.5

50

,«s

~ir~Ln_rrr~Lr

.

132.5

7.5 *s AS /<s

(mm)

17.5ys

60

1

(mm)

(min)

50-90^5

Ji

60~

22.5/-s

300ns

D(K)

n

10-4.

Keyboard

Power

controller

ON

basic

M?3500

flow

Timer START

(5mS)

-

93

-

MZ3500

10-5. keyboard

No

10 11 12

19 20

21

22 23

24 25 26 27

30 31 32

34 35 36

38 39 40

1 2 3

4

5

6

7 8 9

Porality

signal

name

TO

XTAL1 XTAL2 RESET

SS

INT

EA

RD

PSEN

WR

ALE

DBO DB7

GND

P20 P21 P22

P23

PROG

VDO

P10 P13

P14 P15

P17 P24 P25

P27

T1

Vcc

controller

IN/OUT

IN IN IN IN IN IN IN

-

IN

OUT OUT

IN

-

IN

OUT

-

OUT

IN

IN IN

signal description

Output

data signal Internal clock oscillator Internal

clock oscillator crystal

Processor

initialize

+

5V

Strove

of

D(C) that also

GND

NC NC

NC

RETURN

0V Output Strobe

Not

NC +

Strobe to

NC

Pins

Not Keyboard

an

Acknowledge +

signal

supply

data

signal

of

D(K)

used

5V

to the

terminals XOX15ofthe4515

used

to

activate

#32 pin

Alphabets

#33 and #34 are not

used

type

KUS2.

whether

5V

supply

from

the

from

which

also

keyboard

the

identifier

it is GND or NC

input

from

the sub CPU crystal

input

is

used

for

keyboard

key

(D(K))

is

used

for

unit

by

which a hexadecimal

decorder

keytop

embeded

and

symbols

used

Keyboard

the CPU

(D(O)

interrupt

is

input

interrupt

LED

(LOCK)

type

(ACK(O)

Function

to the

when

to the CPU

during

is

Sent

keyboard

a key is

code

key

search

identified

only

pushed

side

is

by

when

side

(ST(O)

during

(ST(K))

sent

out for

mears

the CPU

key

search

generation

of

KSO, KS1,

receives a correct

shift

KS2 of

pulses

KUC1

data

The

-3500

performs self-check test during

loading

of the

Test

regarding

1) MFD

I/F.

machine)

checks

[Procedure]

1.

Turn

on all dip

the

middle

all

dip

switches

board.

2.

Insert a floppy

unit)

3.

Turn

the

power

4. The LED starts

During

stays

unlit

mdicsted

(DISPLAY) (1) LED

(2) The ed and

LED

kind

flickered

comes flickers after

of

error

11.

SELF

ROM. 11-1.

the

main

CPU

128KB

switches

of the

of the 2 bit

disk

RAM. 16KB

of the 4 bit

front

side

of the

unit

into

drive

ROM

on the

unit

on

flickers

execution

About

for a

moment then

four

of the

seconds

test program,

activated after normal ending

abnormal

can be

ending

known

by how the LED is

CHECK

initial

(for

ROM

switch (located

board)

and

front

side

No 2

(the

third

the

test

the LED

later

the

result

of the

test

program

based

in

turn

on

of the

drive

program

is

test

activat

FUNCTIONS

LED

(fof id«niific«Tion

of

GO/NO

GO)

Type

of

error

0) MDF 1/F

ON OFF

1sec.

(2.1

SDO

read/write

(3)

SDO

bank

® AD2

CD

©

/s~.

NOTES:

1. The MFD I/F connected slot

2. ROM

2)

Loacing

The

sector

bank alternation

bank alternation error

ROM

sum-check

Option

based

test program

RAM

(Indicated

RAM

or

of the

drive

test

will

machine.

check program

to

start

error

4sec.

error

alternation

error

read/write

even

when

bank alternation

will

not be

when

the

unit

No.2.

not be

is

loaded

executing

error

the

tested,

diskette

performed,

from

the

test.

option

error

if

was not

the

RAM is not in

there

is no MFD I/F

inserted

unless

it is a ROM

specified track

use)

in the

and

[Procedure] (1)

Set dip

of the

POSITION

,2) Set dip

front

(3)

Insert

(4)

Turn

the

(5)

Load

the

to

start [Conditions (1)

Use the

(2)

Program

that

it is

track.

(Max.

256

(3)

Data

descrived

Sector

(4)

Program

switches

front

No.

switches

side

of the

the

media

power

program

execution

required

FD-55B

may

written

bytes

x 16

1 of

Track

loading

on of the 4 bit

side

of the

OFF

on of the 2 bit

board.

into a slot

on

from

of the

for the

exist

in any

in

continuous sector

sectors

next should

0.

address

unit

board

as

illustrated

1

the

drive

diskette drive

must

of any

specified

test

sector

= 4K

2

ON

program.

unit

of any

bytes)

have

be

4800H

located

3

ON

unit

located

diskette

track

and

media]

unit.

track, provided

within a same

been

and

in

middle

at the

right.

ON

on the

drive

unit.

and

sector,

written

higher

4

on

MZ

3500

Sector

1,

Track 0 information

Represent system

NO. OF

SECTOR

SIDE

0

AAH

-i!

1CH

\

the

Drive

media

specification

Single

Double SIDE 0 (front SIDE 1 (reverse

TRACK

unit

dencity

density

SIDE

(Track

(other

side)

SECTOR

20

0) than

N

Test

program

NO. OF

SECTOR

SUB-IOCS

Track

NO. OF

SECTOR

0)

I i i

Load

address Start address

No

of

data

•

Sub-IOCS

less

than

block

transfers

can be

eight

mut be

i

t

i 1

traced

10

TRACK

= INT

divided

blocks,

by

SIDE

[IOCS

into

the

block

"FFH".

SECTOR

50

capacity/1

eight

blocks.

following

SECTOR

NO. OF

SECTOR

-H the end

K] + 1

If

divided

to the

15

N

to

final

11-2. Sub-CPU side

[Test items] Memory, interface, GO/NO screen. HALT

(3)

VRAM,

light

GO of the

Moving

key.

Turn

power

the

test program.

to

each

Result

except

GDC

pen.

and

test must

from

on

while pushing

test

phase.

of

GO/NO

for the CRT

peripheral,

RS232C interface.

be

confirmed

test

to

test

is

No.

POSITION

the

Then,

push

the

GO

will

appears

interface

and

clock,

speaker,

on the

done

by

depressing

1

OFF

HALT

siwtch

HALT

switch

on the

speaker tests.

printer

video

the

2

ON

to

start

to

step

video screen,

3

ON4ON

[Procedure]

(1)

Turn

OFF all dip

the

middle

all

dip

(2)

Set the

the

reverse

5

ON

of the

switches

system

side

6

OFF7OFF

switch

front of the 2 dip

switch

of the

of the 4

side

bits

board

8

ON

of the

unit.

levers

to the

ON10ON

(10

9

bits

board

bits)

foil

unit

and

owing

located

turn

OFF

located

positions.

in

on

-96-

1)

Memory

Sub-IOCS Shared Shared Above

test

RAM RAM RAM

are

tested. [Display] (1)

Normal test ending

RA

OK:

RA

OK

RA

OK

Above

information

lines.

(2)

Abnormal

RA ER

3)

CRT

inter

face test Performance phase,

of the CRT is

push

the

400-raster CRT,

CRT.

'Procedure

and (TestNo.1) Confirm 20

lines.

all

patterns

(4000H-5FFF)

(2003H-23FFH)

(2440H-27FFH)

SUB-IOCS

Shared

RAM

are

test

ending

tested.

HALT

switch.

and

test

No.9-No.16

display]

on the

display screen

displayed

To

move

Test

No.1-No.8 test

on

three display

into

the 200

of 40

digits

each

test

rasters

test the

and

2)

VRAM

Proceed

[Display] During (1)

Display

(2)

Display blinking

(3)

Display entire

Test

1.

Normal

2.

Abnormal

20

check

to

test

for

ASCI!

and

test penode, display

reviced

"U" for

"I''

screen

with under!

by

end

VR OK

VR ER

1

234567890

2 3 4 5

i

(All

I

5

6

ASCII

patterns)

00-FF

7

8

9

0

atnbute

shows

under following.

entire

screen

space.

VRAM

ne for

C

*7 '

O

/ I

Irom

entire

top

screen.

side.

(Test

No.2) Confirm 25

lines.

(Test

No.3)

(1)

Confirm

(2)

Confirm

all

patterns

that that

on the

an

entire

attributes

display

screen

are

shown

screen

is

Filled

of 80

with

as

illustrated.

digits

"H".

and

2 3

4

5

25

1234567890-

(All

patterns)

Vertical line

Horizontal line

Highlight

Blink

-567890

-

97

-

(

Check

MZ3500

(

Check

No. 6 )

No. 4 )

Backroung

in red

L "H" in

[•

"H" in

Border

!•

"H" in whi

blue

green

white

in

black

(

Check

No. 7 )

Back

(

Check

ground

"H" in

"H" in red

"H" in

L-

in

green

No. 5 )

blue

white

(

Check

No. 8 )

"H" in red

"H" in

green

"H" in

white

Back

Kff

ground

}

in

black

in

blue

H'

in red

H'

in

green

H'

•

H'

' in

white

4)

Speaker Performance tested. mulfunction.

ing

5)

Printer interface test Performance

of the [Dispaly] (1)

Normal test ending

(2)

Abnormal test ending

6)

Light

Performance

action

[Display] On the and (1)

Normal test ending

(2)

test

of the

Listen

carefully

Adjust

level.

of the

8255

are

PR

OK

PR

ER

pen

interface

of

of the GDC are

upper

left

line.

LP

OK

Abnormal

tested.

light

corner

test

LP ER

7)

RS232C

Performance action

[Display]

(1)

Normal

(2)

Abnormal

of the

RS

OK

interface test

of

RS232C

8251

test

ending

test

RS ER

speaker

to

the

printer

test

pen tested.

ending

are

tested.

ending

and the

detect

volume

interface signal lines

interface

of the

interface

any

control

screen

volume

abnormal sound

to a

signal

is

displayed character

signal

control

suitable

and

lines

are

or

listen-

action

and the

It

will

need

in

order

interface

manner:

c

R S

2

3 2

C

PO

N

C/

Ready

wiring connection

to

test

the

RS232C

edge

connector must

^n

*^

CD

DR

1

_

O

_

5

O

"

2 7

.

O

9

10

M

O

8

.

O

6

.

O

4

.

H

O

3

O

M

rt

as

interface.

be

Front

side

/

*

7531

illustrated

Pins

wired

in the

of the

figure

RS232C

following

-

98

-

8)

ROM-IPL

MAIN

CPU

CHECKER FLOW CHART

MAIN

CUP

CHECKERSTAHT

(

Write

"66"

»nd~Of~

on

Tracki

0.20.»^3

A

]

1/2

NOTE

lnclud«

NOTE

tr»c1i>d« SEEK

c

SEEK etroi

and

RECALIBRANTE

and

RECALIBRATE

MZ3500

error

-

99-

MZ3500

MAIN

CPU

CHECKER FLOW CHART

M?

Option

HAM

read/write

Change the

option

check

bank

of

RAM

C

Error on

display

HALT

-

100

-

SUB CPU

CHECKER FLOW CHART

SUB

CPU

CHECKER

(

^

START

1/3

I

M

7*500

CRTm

t*f

face

t«t

SeiGDCto«00<amr.

-

101

-

MZ3500

SUB CPU

CHECKER

Sei

th»

timer

to 23

59

minuiei.

58

Oc

*mb«r 3 III

FLOW

hourt.

**corxii

CHART

2/3

SUB

CPU

CHECKER

FLOW CHART

3/3

Printer

M»c*

tt»t

int

11-3.

Keyboard

1)

Keyboard

(1)

After power

out the ROM If the

alpha/symbol (LOCK) indicates a failure Key

self

unit

controller

on in a

self-test.

check

test

functions

ROM

test

normal

in

KBC.

condition,

LED

If

not,

it

were

KBC is

starts

to

functional specification

to

carry

turn

on, it

satisfactory.

(simplified

t

check)

2)

Keyboard

(1)

As the

sion,

(2)

Depress

a

failure

(3)

It

(4)

Observe

i)

Turn

ii)

Turn iii) Turn iv)

Push

test

power

is

turned

it

goes

into

the

key in a

correct sequence,

LED

activated

If the key was

each

pushed

is met in the

returns

testing

all

the on the

the

power

to the

keys.

With

following

OP/PRO

while pushing

PO/PRO

a key one at a

on

with

the

keyboard

given

it

makes

time

key,

self-test

sequence.

the

a key is

in a

wrong

it

makes

If key is

alpha/symbol (LOCK)

pushed.

sequence

the LED

normal mode upon

this,

key-in

siwtch

which

time

the LED

to the OP

to the PRO

in

goes

sequence

the

"DEB" key.

accordance

"DEB"

mode.

depressed

completion

out.

to

test.

side.

with

in

depres-

or

when

blinked.-

the

in

a

of

given

sequence.

-

102

-

MZ3500

12-1.

MAIN

CPU IPL

(

FLOW CHART

MAIN

CPU

START

the

location

IPL

Check Index

^

J

program

test S**ect START

MFD

itgnal

(PL

Transfer m

1000E-J0400E-.

ROM/RAM memory

SUM

12. IPL

1/2

Jump

B

FLOW

to

400EH

CHART

Contents

1.

Kind

Single-side dencity.

2.

Track

and Number Note'

of

parameter

of MFD

and

Truch

of

The sub

sector

double-dene

sector

where IOCS

sectors

loader

is

ity or

contained

double

is

stored, Loadi

m the

side

double

vj '.

leading sector.

-

103

-

MZ3500

MAIN

CPU IPL

FLOW

CHART

I

Check

if

IOCS program

area

is

smaller than

RAM

volume.

YES

LOAD

IOCS

SEEK& READ

Transfer

the

to

IOCS

shared

program

8000H~-»-F800H~

2/2

RAM

NO

I/O

SYSTEM

LOAD

ERROR

transfer

HALT

CPU

•SEEK,

READ

ERROR

-

c

STOP

LOAD

\^

tran:

I/O-SYSTEM

ERROR

isfer

LOAD BOOT

LOAD

BOOT

SSEK&

READ

ret

rys

^

BOOT ADDRESS

JUMP

^\

)

—

BOOT:

Program used

Position

of

Sector 2 thru

ERROR

boostrap

5 of

to

start

program

Track

0.

C

(

the

system.

on the

media:

1

BOOTERROR

on

disp.

1

HALT

CPU

STOP

*

C

CPU

HALT

STOP

-

104

-

122.

SUB CPU IPL

(

FLOW CHART

POWER

ON A

SUB

CPU

IPL

T,m«,

1

In

t,alize8255

A

Mode

0.8

C

SUB CPU

Mode

OUT

1

READY

1

Rest

GDC

1

Check

ROM sum

Initialize

GDC and

check G VRAM

OFF

J

1.

IPL ROM is

broke u indicated

on

display

MZ-3500

Set

the

custom

CSP2

control

Initialize GDCagatr

C-GDC, G-GDC

command

LSI

boards

transfer

CSPI

and

CUP

HALT

STOP

\

I

-

105

-

Mz-roo

13-18.

VU « H j A *N B f A 'i

m

LJ

CONFIGURATION

74

LS 00

R R R R R F1

LJ U U U LJ U

IA

IB \\ A H ^> ( M

m

LJ LiJ LiJ LJ LL! LiJ LJ

1

Y IA IB 2Y 2A 2B C^D

Vet

+B 4A 4Y 3B 3A 3Y

LJ LJ LJ LJ LJ LJ LJ

IA IB 1Y 2A 2B 2Y GND

74 LS 03

74

6A 6Y SA^ 5Y 4A 4Y^

tS 04

m

OF 1C & LSI

74LS126

rn

irn rn

firi

V

LU

LLI

LiJTiMU

74 LS 1 38

DATA

(H

TPLTb

Yl

V Vt Y4 Y5 Y6

1

i

M Y]

A

1

[r

LJ

U LJ

A

h C

i f LT

E

\.AHI

C

H

U IA IB 1

fcAABLt

*

Jl

<

t\

J,

U

( A

tNAHI

74 LS 139

SELECT

DATA

t ,

C

A 1 1 J>

C A B YO

A

B YO Yl

1

i Y Y

YO

' * '

SELECT DATA

IYI 1 Y2 1 Y3 GND

IT

i

Yd

J,

LJ

OUTPUTS

LU LU

-

I

Y*

( 1

,1,

LJ

LJ LJ

i i

t

OUTPtTS

j],

Yl

Y2

Y

[

Y6

Y7

r

Y7

CSD

A

Y2

Y3

Y

Y3

GNI)

H

^

PARAI

IH if

sim i/

INIVT

airuT

Va I

OAJ

H UH (,

1

SHIf

I H QH < F

I

OAD

[j

SFRIA1

CLfcAH

INPUT

Jr

A

R C U

[

1 1

LJ

LLTLJ

SERIAL

A B L D

INPUT N "

PARALLEL

1C

1AI 2Y4 IA° 'V3 IA3 'Y' IA4 2Y] CM

NtC

K 1Y1

JjuJTU

1C IA1 2Y4 1A2 2Y3 1A3 2Y2 lAi ZY] GND

L«J I sITTTT'

^~

J

ej

>T

LH

J

(MI>

T»I

CLOCK

INHIBIT

LiJ LJ LJ LlJ LJ

INPUTS

CLOCK CLOCK

INHIBIT

I I

LJ

LJ LJ LJ

IA IY 2A 2Y 1A 1Y CM>

\tc 4B 4A 4Y 3B 3A IY

LJ

LJTJLJ

IA IB I Y 2A 2B 2Y

Vg 1C IY 3C 3B 3A 3Y

M

R R R R R m

jTj UTJ LJ LJ LJ

IA IB 2A JB ^C 2Y CM>

LJLJ

74

IS 08

LJ LJ LJ

LJ

GN1>

m

I

H I r1 I r

LJ LJ LJ LJ LJ LJ LJ

IA 1Y 2A 2Y 3A SY

1NPLTS

INPUTS

/

A

OUTPUT

, y

J

(

s

—

J

L

J L

L

SI-1

tO I A !B IN 2A B 2Y ( M)

1

Sf

B 4

4

A 4

J L

I I ^ IM I fS

J L

Y S

J L

A 3

J L

C.ND

B

Y

J

1

OUTPUT

J

3Y

LJ

LULU

LD

LJ LU LU LU LJ LU Lll

LJLJLJLiJLJLJLJLJLJLJ

CLEAW

1Q ID 2V 2Q 3Q 3D 4Lt *Q GND

16

M

7. - 3500

LJLJLJliJLJULJ

IA IK II A I 1 1 Ml

74 LS 367

VU ("- bA FY ^A SY «A 1Y

LJ LiJ LJ bJ LJ

-

bJ LJ LU U LiJ LiJ

OLTPbT

JQ JD 2D 2y 3Q 3D *D 40

CONTROL

UUU LJ U U LT

1

ID ICK 1PR .Q

CIR

LUTJ

.,-.

TZT

CND

'O

ENABLE

f

74L593

O\ OD Oil

liiiiilv

(...iml.r

OL

II HO!

I.I

Lu

LLI

INI

I r KOI KO; t-L B

LLTLu

ID

Vc(_

IA 5Y (A 1Y

1

TLTLzJ

NL NX

m

q>Jq>J

LLlQJ

HTLLlliJ

1A

1Y 2A 2Y »A 3Y GND

INPUTS

STROBE

4A 4B 4Y 2A

C 4A 4B 4Y 2A 2B

S

2Y

IA IB IY 2A 2B 2Y

LUUJlJJLiJLLjlJJLlJLLl

SELECT

1 A IB 1 Y 2A. 2B 2Y CND

«B *A 4Y SB JA >Y

171

m nyi

UJ U

S4S1S7

IN

ryirTi

n

Ll

/^PDI

99OC

\l \-' 111 I ! IK H I I ! l\

m

M M

LU

L^J

<.

2 l~l LO S 1 )t (_S

HI L±J 111 LlJ LJ

TA7313

LH008O

A!

1C

A12C A13C A14C

AI5C

CLKC

D4C

D3C

D5C

10

D6C

+

m£

12 13

D7C

14

DOC

15

DlC

TVTT:

16 17

NMlC

18

HALTC

19

MK1-.OC

20

TOKOC

><PD8256

1

2

3

4 5

6

Z-80

7

8 9

r^n

(2V

W

R m

|)|N

DAIO

DA8

DA4 DA3 DA2

DAI

JBUSKO

DBIISAK

IAD

19

IQ

LU

,s ID 2D

/<J --Q I . O

y t:

6

LU

V

U U U

I

ENABLE

C

U LJ LlJ LJ U U

ENABLb

vLt 30 tD 4y

.V, t<\ I1! H JA

u

m

rn n n

'K

IK l> -A h "i < M

LJ

LA

U U U

LU

LiJ LiJ LiJ UJ Ly bJ

TC40498P

C.ND

PA3C

PAOQT

_c?C

AlC

I-C7C

Fx.eC

PC5C

IX.]

C

1X2 I

12

40

JJ'A4

39

JI-A5

37

Jl"A7

36

35

34

DDO

33

3

32pD2

31 30

Hl>5

28

DDT

22 21

Jl

Sharp MZ-3500 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual