Sharp MZ-3500 User Manual

MZ-3500

SERVICE

PERSONAL COMPUTER

MODEL

CONTENTS

MANUAL

CODE:

OOZMZ

3500SM/E

Z-350

1.

Specifications

2.

Software (Memory) Configuration

3. CPU and

4. CRT

display

5. MFD

interface

6.

R232C interface

7.

Printer interface

8.

Other interface

9.

Power

10.

Keyboard controller

11.

Self check functions

12. IPL

flow

13.

Circuit diagram & P.W.B

Parts

1

memory

circuit

chart

list & Guide

12

25

52

72 yg

81

description

103

gy

circuit

94

7

discription

90

SHARP

CORPORATION

1-1.

Specification

Outline

of the

1)

High

speed

2)

Built

in

3)

4)

5) Model 3530

disk Model MZ3540

64 KB

LSI

DISPLAY

MFD

Other

Other functions

Software

Accessories

mini

Built

in

printer interface

Connection

monitor

Permits

units)

the use of

and 64 KB

RAM.

I/F

main

unit (Model

processing

floppy disk

of up to two

standard CP/M

incluse a single

RAM.

has two

double-side,

CPU

MEMORY

I/O

MZ353X

MZ354X

Light

pen Keyboard Printer RS232C

Speaker

(500mW) Battery backup clock HALT

FDOS

CP/M

Intstruction master

floppy

power

cord

1.

SPECIFICATIONS

35XX)

using multi-CPL'

and

RS232C

video displa,

double-side, double

density

Multi-CPU

ROM

RAM

Custom

GDC FDC PIO SIO

TIMER CLOCK Screen Elements Attribute Colors

I/F

One double floppy

Two double floppy

Dedicated keyboard

Centronics interface

No

BASIC

Utilities

Basic Expanded CP/M

Manual

disk

processing

LSI

structure

double-side,

density

disk

double-side,

density

disks

protocol,

CP/M

Aerial

interface

mitt

(separate

density

mini

floppy

IPL

C, G

For

For Shared VIDEO

RAM

Memory mapper Screen CRT

Floppy disk controller Parallel Serial Counter Clock 80 8 x

Reverse, 8

colors

2

channels (applicable

256

Built-in

asynchronus

High control commands

Expanded BACKUP,

graphic

mini

floppy

disks

and

main

CPU

sub-CPU

RAM

controller

I/O

port

I/O

port

characters

16,8x8

blink,

on

each character

bytes/sector,

interface

mode,

110 to

class

compatible

RS232C, GPIB, INIT,

display

or

overlaid display

Model double Model 3541 density

Z80A 8K 8K 64K Bit

16K Bit 16K Bit 16K B't

MPD7220 pPD765 8255

8251

8253 /iPD1990AC

x 25

lines.

80 x 20, 40 x 25. or 40 x 20

line

(horizontal, vertical)

and

CRT 640 x

16

sectors/track,

for

optional

9600

bps, half-duplex

SW

with

COPY, DEBUG,

possible

on two

3531 includes a single

density

mini

floppy double

disks,

x 2

chips chips chip chip

chips

200,

disk

side,

and 128 KB

or 8

B/W or

has two

mini

floppy

microprocessor

Byte

ROM

Byte

ROM

DRAM

x 16

SRAM

x 4

SRAM

x 1

SRAM SRAM

x 2

400,

640 x

80

tracks/disk

KILLALL

x 1

volume control

4K Bit

TH

SP6102R001

CSP-1

SP6102C002

CSP 2 SP6102C003

background color

MFD

Speaker

PC3200 BASIC, supplemented

and

GPIO

individual

double

and 128 KB

double

chips

color)

and

M 7 3500

color

side,

graphic

MZ3500

1-2. MZ-1K01 (Keyboard)

Outline

Specification

Keyboard

MZ1K02 U.S. keyboard MZ1K04

German

LSI,

1C

Keys

(98)

Interfacing

Other

Cabinet

cables

layout

specification

(ASCII)

keyboard

MZ1K05:

Keyboard CMOSIC Sculpture

Alphanumeric

For Use

Repeat

Indicators Molded Size

controller

key

Mode switch data transfer of

coiled

function

(4

(W x H

MZ1K03: U.K. keyboard (ISO).

keys

cable

LED's)

Color

xU

with

61

1

the CPU

8-pin

Automatic continuous

POWER,

French keyboard

80C49

or

8749 4049x2,4514 Mechanical contact key,

Ten key

(serial)

and

power

DIN

plug

repeat occurs 0.64 seconds after

....

depression

Alphanumeric

Office gray

467

x 35 x 190

with

15

Function

supply

. 2

of the

same key.

keys

Weight | About 1 .5kg

(transmission under

life

of

10,000,000

keys

6

operations.

Definable

15,000

Two-key rollover

(3.3

keys

baud)

Ib)

10

1-3. MZ-1U02

Outline

Specifications

Expansion Optional The

expansion

Number

of

Slot

connector.

Area

of the

Slot

for

option

Refer

unit

for the

boards

are

box

slots: 4 slots

60-pin

slot

inserting

and

to the

MZ-3500

plugged

will

accomodate

edge

option

slot

number

page

series

in to the

expansion

up to

connector

board:

(expansion RAM)

Expansion RS232C

TIN

"CIRCUIT

CPU, which

four

option

x 4

140.5

x 140

MZ-1R06

SFDI/F

GPIO GPIB

(IEEE

I/F)

can be

box.

DIAGRAM"

attached

boards.

Slot

o

o o o

1

to the

rear side

Slot2

o o o

0

of the

main

Slot

unit.

Slot

3

O

o o

4

O

0

o o

-2-

MZ3500

1-4. MZ-IR03

Outline

Specifications

Optional board It is

inserted

The

MZ-1U02

LSI

Graphic

functions

(Color

must

specified

for

dot. when

video

the

unit

is in

Software

used

through

expansion

be

each

color

use)

Screw

graphic display

the

slot

on the

box is not

GDC

Graphic

vinrn

HAM

~~~~~

—

BASIC

graphic

(1)

functions

front

required.

controller

Basic Expansion

(optional)

____WDEO

640 x 200

green

monitor

640 x 200

color

monitor

640

x 400

green

monitor

640 x 400

color

monitor

control

with

panel

(buit-in)

statements

the

Model-3500

of the PU.

RAM

series

MPD7220 16KDRAM

16KORAM

640 x 200

_____

640 x 400

^______-

SDISP ODISP CHANGE DISP GCOLOR

CLS

PSET PRESET

LINE GTABLE

CIRCLE

PAINT GINPUT GDISP GPRINT GREAD CENTER GCURSOR GSCROL SYMBOL SCALE

Expansion

CPU.

x 16

(32KB)

x 32

(64KB)

32KB

(basic)

Two

screens

One

screen

— ~"

unit

It

includes 32KB

dots

Screen

Designation Mode designation Graphic

Cleared

Dot set

Dot

reset

Line

creation Table creation Circle creation Paint over

Input

of

Display

Output

Read

of

Input

of Graphic Graphic Graphic Scren

scle-down

of

RAM.

(maximum

640 x 200

640 x 400

designation

pattern

by the

graphic pattern

of

coordinates

pattern cursor position screen symbol displaying

for two

of

output

designation

color specified.

graphic pattern graphic pattern

within

scrolling

designation

96KB

expansion)

640 x 200

Six

screens

Two

screens

Three

screens

One

screen

video units.

screen.

on

printer

the

specified

designation

dots

area

-3-

MZ3500

1-6.

MZ-1R06

Outline

Specifications

Optional board up to a

maximum

This

option

plug

LSI

Memory

and

area

user

for

memory expantion

of 256 KB.

into

the

expantion Basic Expansion

Total capacity

the

BASIC

(RAM

BASE

main

of the

box in

64KDRAM 64KDRAM

CPU RAM

SYSTEM

:

AREA

USER

'

AREA

MZ-3500

slot

1 or 3.

of

x8

(64KBI

x8

(128KB)

Main

• 57 KB

sries

CPU. with this option

CPU

only

Use

128 KB

80 KB

of

MZ-1R06

192 KB

«-

128 KB

the

main memory (RAM)

Using

eight

64K

on

theMZ-1R06

256KB

*-

208 KB

RAM's

can be

expanded

- 4 -

MZ3500

1-7.

MZ-1D07

High

Outline

Specifications

resolution

Video

Display

Input

signals

Power

Cabinet

Adjusting knobs Accessories

tube

capacity

size

supply

MZ

3500

series

Type

Fluorescent

Total

number

display

characters

220 x 145

Method Horizontal 29W

power consumpt Molded Size

(W x H x U

3

CPU

connection

12

green

monitor

Non

glare

green

color

P39

(green,

long

of

Separate

20

Color

Vertical synchronization,

2,000 (80

input,

86kHz

ion

324x310x356

cable

and

characters

TTL

Office

power

PERSISTANCE)

x 25

level

gray

contrast,

cord

and

lines)

Tilt

Size

Display capacity

Vertical

Weight

brightness

stand

12",

90"

640

horizontal

400

vertical lines

47

8 Hz

7.2kg

deflection

dots,

r

- 5-

MZ3500

1-8.

System

configuration

of

Model 3500

Keyboard

MZ-1K02 MZ-1K03 MZ-1K04 MZ-1K05

Printer

IO2824E

I I

Option

I

CE-331M

I I

'

I

MFDI

|

"Model-3541 = Model-3531 + MZ-1F03

6

Memory depending In the

paragraphs

those

four

will

on the

states.

be

operated under

hardware

to

follow,

MAIN

2.

SOFTWARE (MEMORY) CONFIGURATION

four

states

of

and

software configurations.

description

CPU

will

SDO ~ SD3,

be

made

for

2-1.

SDO

can

system

for

SD1, SD2.

(INITIALIZE

only

exist executes thus loaded

IPL

and

immediately after power

under this

will

automatically

SD3.

SUB

CPU

STATE)

condition

assign

MZ3500

on, and the

and

that

the

memory

area

MAS MA2

MAI MAO

FFFF

cooo

BFFF

8000

7FFF

0

0 0

RAMA

0 0 0

1

V

RAMA

1

1 1

FFFF

T

?

IRAM(COM^

1

jOO1——

reoo

^\

MS1

= ° (D

MSO

= 0 (L)

\\

u

\\

N

v

V

\

ROM

(SPAPE)

4000 3FFF

2000

OFFF

0000

i

|

ROME

[

I

I '

ROM

JPL

4000

(COM)

IPL

27FF 2000

1

FFF

0000

RAM

ROM

*7

M 7.

3500

Operational

(1)

Upon

reset contents starting applied

TIMING

description

after

of the

at

address

to the

OF

Vtc-

SYSKES-

SKES-

jJSUB

pr)WF PO*E

MAIN

START

Memory

1.

2. The

3.

Map

Data:

ROM-B

is

tested

ROM-IPL functions under

at

first,

but

later

the IPL

program

RAM-COM

is

shared

CPU.

INITIALIZE

power

initial

program

4000H,

sub-CPU.

RESET

SIGNAL

CPU

^

START

CPU

to

determine

it

functions under

has

been

by

both

FLOW

«T

on, the

main

loader

(IPL)

during which time

if

ROM's

control

are

of the

the

loaded

in

RAM.

the

main

CPU and the

ABT

CPU

loads

the

into

RAM

reset

present.

main

CPU

sub-CPU after

sub-

is

POWER

OFF

(2)

The

main

and

starts

IPL is

assigned

(3)

The

main

to

SD1,

and

disk.

Signal

generated

CR

network

Output

a.

Main

CPU

b.

Main

CPU IPL

4.

Memories

under

5.

Bank

other

the SDO

select, MAO~MA3,

ofCOOOH-FFFFH.

CPU the

CPU

starts

signal

reset

then

sub-CPU.

to the

then

to

from

and

power supply

from

time

load time

than

described

state.

terminates

At the

sub-CPU.

send

the

load

DOS

the

main

is

used

resetting same

memory

from

CPU

port

above

within

time,

allocation

the

system

cannot

the

address

the sub CPU

the ROM

(state) floppy

be

accessed

range

MZ3500

ROM-IPL

1. An 8KB ROM for the

ROM-IPL.

2.

When

the

system

state

after

power

this

stage,

the

3. The CPU

4. The high mapper the

5.

Address

The be program

2-2.

SD1

determines system processors)

main

state

ROM-IPL

memory

used

SD1

is

loaded

starts

CPU as it

and the

0000

by the

has

(SYSTEM

mode.

(2764

or

mask

reset

signal

on, the

ROM-IPL

from

sets

goes

sub-CPU

is

addressed

of the

area

sub-CPU

been loaded

main

is

address

the

sub-CPU

out of its

starts

sub-CPU

above

there.

addressed.

OOOOIROM

by the

ROM

because

LOADING & CP/M)

which

operating

in the

CP/M

(Control

ROM

equivalent)

turns from CPU

starts

reset

initial

state

to

operate.

sub-CPU.

is ROM

address

the mam CPU

system

Program

low to

to

operate

address

signal from

via the

At

this

address

(1000)

ts in

use.

for

is

used

high

At

10000) low to

memory

point,

(0000)

cannot

initial

The

Micro-

Mam

CPU

OfFF

0800

0000

MS1

= 0( L)

MSO=l(Hj

logical

Logical

address

1

FFF

1

800

1

7FF

1

OOP

OFFF

0800 07FF

0000

address

(during

of the

ROM

physical

1

FFF

1

800

I

7FF

1

OOP

OFFF

0800 07FF

0000

IPL

operation)

sub-CPU

address

ROM IPL

r r

F?'

MAIN

r

^

CPU

RAMicnu:

\

>

\

x

\

V

4

\

^ \

3

\ \

\

\ \

\

\ \ \

\ \

RAM sn

RAM SA

KAM«.(IH) 2000

1FFF

\

\ \ \

i

f. ft f

n

- 9 -

MZ3500

Operational

(1)

As

soon

port

and main CPU. is

the

(2)

As the

Communication

description

as the

sub-CPU

waits

for

program transfer (IOCS)

This

IOCS

program resident

main

CPU

loads

is

started,

(Input at

address

the

between

it

initializes

Output

Control

4000H-5FFFH.

information

Main

and SUB CPU

from

the I/O

the

System)

sector

(3) (4)

"1" of

track

"0" of the

and

bootstrap routine

The

bootstrap program

The

bootstrap program determines

BUSRQ

to the

H

OUTPUT

|

(ISOLATION

floppy

sub-CPU.

is

loaded next.

disk,

rnemory

OF COM

it

loads

the

IOCS

allocation.

RAM)

2:3.

SD2

SD2 is

MA2

BANK SELECT

(ROM based BASIC)

active when

MAS

MAI 0 0

MAO

FFFF

Sffi

"SHARP

00

0000

° °

00.1 1100

01

0101

1

III

R\MA KAMB

i

4

1

1, 2, 3| 4

3

i

\

IFF? IFF?

0000

(MO2

MO1 MOO

2

ROME

ROMC ROMU ROM!

J

ROMA

0

0001

00110

01010

BASIC"

is

executed

ROM 2

via

MAIN

ROM.

CPU

0

1

I

0

1 1

0 1 1

1

0 0 I 0 0 1

0 1

1 1

1

K

\M L

2| 3, 4

MS]

= I (H)

MSO

= 0 Li

1 I 1

0 0 1

1 I 0

0 1 0

1

1 1

KAMI!

2,

3 |

1 1

SUB CPU

4

1.

Bank

select, MAO~MA3.

2.

Bank

select, MOO~MA2,

is

effective

is

effective

for

memory

for

memory

area

COOOH-FFF

area

2000H-3FFFH

-

10

FH.

-

2-4.

SD3 is "SHARP

RAM

BANK

SELECT

SD3

(RAM based BASIC)

active

when "SHARP BASIC"

BASIC"

MAS MA2 MAI

MAO

Ffft

gFFF

is

loaded

0000 0000

0011 001) 0011 0101 0101 0101

III III III

\

1

2,3,4

-

, \ ,

RAMA

1FFF

ROM

0000

]L

in RAM

from

MAIN

0000 III! 1111

RAMB

RANC

1,2,3,4 1,2,3,4

ROM!

ROM2

is

ececuted

the

CPU

via

RAM.

floppy

disk.

MSO

0000

lRwnuf

KAMI)

KOM3

K(IM4

\\ ROM BAS

MSI

= 1< H)

= HH) SUB CPU

1

r

%

\\

v

\\

\

\v

\\

N\

v

x

\\

RAN.

\\

RAN

RAM

MZ3500

1

SP

SC

SB

k

' SUB CPU

1 PI

KU

"°

M02

ROM

BANK

SELECT

000 0 ) i ]

[NOI

0

0 1 " 1 0 0 1

MOO

010

1.

Bank select, MAO-MA3.

2.

Bank select, MOO-MO2,

Operational description

The

state

of the

system

program

before

the

load

10 1 0

is

effective

for for

by the

memory memory

bootstrap

is

determined

of the

is

system

effective

program.

area

COOOH-FFFFH.

area

2000H-3FFFH.

3-1.

Block

1)

Relation between

main

diagram

memory.

MMR

(Main Memory Mapper)

I

JK» 2K*

and

, RAM

I

(II'TION

1

RAN

4-

'

64KBV2)

J

3. CPU AND

||

'7220

MPXR

i

(,

,APM,C

{)

MEMORY

I

RECEI

VFR

VI

°l

1

OPTION

1

.

Ml

DM1 I MO*J

OK

II K U MO* 400

kl Mil I 1 ION

si v i

(.us

1

SI CSI -2

SEMI

CUSTOM

IS!

CSI'-I

TOM

R

It

L

VIIIK1

RAM

32KB

V

1 HI O RAM

32KB

VIDH)

RAM

32KH

RS-232C

l/f

3-2.

Main

M A

I

N

C

P

u

CPU and I/O

r^

IX

—££-1

port

A6

A

M

P

A2 A3 A4

IORQ

M

i

v~\

r

C

j^

Y 1

(jtA.

Y3

G2

B

Ol Y6

Y4

Y5

74LSI38

v

"" ~s

f^-r-^r-. — r

~~>

\J>

iZ

J

\J I

-)

f\

J -\J

^

0

5 O

Connector

|~^T

1 is

I

PC

2 The

Port

select

Table

-•>

r DL

Obr

MFUC

•

\J

lUMr

IOABCMEMORY

This

paragraph select

address

decoded

signal.

below

signal

functions.

MAPPER)

discusses

and

addressing.

output

in the

describes

main

from

74LS138

address

MZ3500

CPU I/O

the

main

to

create

map and

CPU

the

ADDRESS

A7 A6 A5 A4 A3 A2 A1 AO

00000000 00000001

11011110 11011111

^^^Qooxx

^^^QO•^xx

iiiotoxx

11101

1111QOXX

1 1 1 1 0 1 X X

1 1 1 1 1 0 X X

1

1 1 1 1 1 X X

1 X. X

HEX

00 01

DE DF EO

E3 E4

E

E8

EB EC

EF FO

F3 F4

F

F8

F

FC

F

7

B

F

NOT USE

SFDC

(UPD765)

IOSF

INTR

NOT USE

MFDC (UPD765)

IOMF

IOAB

(MEMORY

MAPPER)

SFD

interface

AO

used

A1 is

"don't

SFD

interface

Interrupt

Flipflop

MFD

interface

MFD

interface

AO

used

AT

is

"don't

I/O

port

AO

and A1

FDC

chip

for RD and WR.

care".

I/O

port

signal

from

the

resetting signal.

FDC

chip

I/O

port.

for RD and WR.

care".

select

in the

memory mapper.

used

during

select.

and

DMAC chip select.

sub-CPU

select.

~W5.

to the

WR.

main

CPU.

MZ3500

3-3.

Sub CPU and I/O

SUB

CPU

port

AS6 5

ASS

2

AS4

i

AST 4_

"MT

6

*""

5

Gl

Yl

74LS138

4G

s07

J

~9

S06

Y6

_JQ

SOS ^

J

r

.Jl

Y4

SO4

12

S03 ,. -^

0

15

S°2

D

14

"SOT

D15 '*°° r MAIN

YO

*.

CKP

^ . .

HEC3

-^

1 .

CSP

......

-C*

CPU

2

\m

Shown

at the the CPU to put

address

by the

74LS138to

Shown

below select

signals.

left

is the

select

the I/O

from

the sub CPU is

create

is the

circuit

ports

the

select

address

used

by

The out

decoded

signal.

map and

AS

7654 M£X\

0000

0001

0010

0011

0100

0101

0110

0111

1000 1001

1010 1011

1100

1101 1110 1111

8

1

23456789ABCDEF

8

soo

S01

8251

S02

8253

S03

8255

S04

input port

805

S06

S07

select

NOT USE

Output

signal

to set the

main CPU.

8251

ASO

AS1, 8253

ASO

AS2 and ASS are 8255 ASO AS2 8-bit Used

AS3

CRT AS1, ASO

UPD7220

ASO

AS1,

UPD7220 ASO AS1, AS2,

Enables

SIO

chip

is

used

for

AS2,

and ASS are

counter

chip

and AS1 are

PIO

chip

and AS1 are

and ASS are

input port.

for

read.

are

"don't

control

I/O

AS2,

and ASS are

is

"don't care".

(graphic)

is

used

for

AS2,

and AS3 are

(character)

is

used

for

and AS3 are

Signal

description

flipflop

to

communication between

select.

data

control

selection.

"don't

care".

select.

used

for

programming during write.

"don't care".

select.

used

for

port/control

"don't care".

care".

port

chip

select.

used

for

write.

chip

select.

read

and

write.

"don't

care"

chip

select.

read

and

write.

"don't

care"

apply

interrupt

CPU's.

selection.

(INTO)

to the

-

18-

MZ3500

3-4. Memory mapper

1)

Block

diagram

ADDRESS

CONTROL

AO

. i. is.

DATA

DO-D7

BUS

COAB

BUS

MERQ

RFSH

RD

"WR

BUS I — \

(MMR)

A15 A14 AI3

A] AO

COAB

MKEQB

RFSH

RB

OAB

V

SP6102R-001

~L

I/O

PORT LOGIC

—

L

n

Memory

mapping

A 15

AU

logic

-

INTB

WAITB

SYSR

WAIT TIMING GENERATOR

CLK

->TO

RESET

-

19

INTERRUPT PRIORITY ENCORDER

1NTFI)

-

MZ3500

2)

Memory

mapper

Polarity

Signal

Name

(MMR)

SP6102R-001

signal

description

1

2

9

10

12

13

14

15

16

18

ST

DO

D7

A15

A13

A1

SRES

SRQ

AR13

AR15

IN

IN/OUT

IN

OUT

Main

CPU

DRAM

output

buffer

(LS244)

switching

Bidirectional main

Main

CPU

Used

in the

shared

RAM. (Address

Main

CPU

Used

in the I/O

Sub-CPU

•

After power

•

After write command (LDA-80H: OUT#FD)

This

signal

Sub-CPU

bus

•

After power

•

After write command (LDA-02H1 OUT#FC) This signal parameter

Address

signal

The

main

AR13-AR15. This

and

MSO.

CPU

data

address

bus.

memory mapping logic

address

bus.

port

select

logic

bus

request

signal.

on:

Halts

the

is

issued after transfer

request

signal.

on:

Resets

bus

is

issued

to bus of the

to the

CPU

sub-CPU

to the

address

main

signals, A 13-A

is

means

or

CPU

by

bus.

of the MMR for

of the MMR to

sub-CPU.

of the

request

sub-CPU, after

reads

the

dynamic RAM.

15,

which

the 4

main

to

sub-CPU.

message

merged

basic

CPU

strap.

(Data

bus 0 ~ 7)

address

output

for the

bus 13 ~ 15)

assign

device

number.

by the

main

CPU-

Starts

program contained

(Sub

CPU

Reset)

by the

main CPU'

the

main

CPU

status

from

(Sub

CPU

in the

memory mapping logic circuit

and

CP/M memory

writes

the

sub-CPU.

Request)

Place

maps

in the

to the

DRAM,

the

sub-CPU.

ROM-IPL.

bus

request

shared

are

made,

ROM,

to the

RAM a

to

produce

along

and

sub-CPU

command

with

MS1

BASIC

interpreter 32KB

19

20

21

R32

IOAB

SRDY

OUT

IN

Valid

Internal

Goes

low by the

Input

when

MMR I/O

of

ready

SD2 is

signal from

Chip select signal

22

23

26

27

~

30

31

ROPB

ROAB

RODS

RSAB

~

RSDB

SACK

OUT

IN

Valid

with

SDO

Chip select Valid

with

signal

SD2

"R32B (alternate choice

Row

address

select

RAS

(ROW

ADDRESS

Input

of bus

acknowledge

command

is

written

At the end of the

mask

active (Sharp

port

select

command

IN/OUT

the

issued

from

active

(initialize

for

four

chip

active (Sharp

with

signal

for the

SELECT; LINE

signal

in the

shared

command

ROM

chip

select

ROM

based

logic

signal.

#FC-#FF.

sub-CPU.

the

main

CPU to the 8KB

state).

BASIC interpreter

ROM

based

BASIC).

the

32KB

mask

main

CPU

ADDRESS

from

the

sub-CPU.

RAM

after

cycle

bus

request

signal.

BASIC). Command (LDA

(ROM

32K

select)

(Input/Output

(Sub

CPU

mask

(ROM

8KB

EPROM

ROM

chip select signal). (ROM

dynamic

RAM

SELECT)

(Row

acknowledgement

is

released

and the sub CPU

Address)

Ready) ROM.

ipl)

(A. B. C, D).

A~D

Buffer)

(block A-block

SIGNAL

address

Select)

from

02H OUT

D).

the

sub-CPU

executes

3FD)

1

the

command

/

-

20-

M 7,

3500

32

33

34

35

36

37

38

39

40

No.

Polarity

Signal

WATB

RCMB

MRQB

Name

RF1B

RF2B

ITFB

ITOB

IT1B

TT2B

IN/OUT

OUT

IN

Main

CPU

128KB

dynamic

Signal

identical

to R F 1 B For

Wait

signal

to the mam CPU

(One

wait

cycle

period)

Chip

select

the

sub-CPU

Interrupt

Memory

15

(WA|T)

signal

issued

input

from

input

from

input

from slot

request signal

RAM

applied during

from

the mam CPU to

the

UPD765

the

sub-CPU.

1 or 2.

from

the

output

option

RAM

the

memory fetch cycle

FDC

(Floppy

main

CPU.

buffer

Function

(LS244)

(RAM

select

(RAM

Disk

(Interrupt

(Memory

output

buffer

of the

the RAM

Controller).

shared

Common)

from

Request)

enable signal.

1)

2)

main CPU.

by the

Floppy)

No. 0)

No. 1, 2)

It

consists

main

of one

CPU and

clock

41

42

43

44

45

46

47

48

49

50

51

52

Write

WRB

IT3B

IN

IT4B

SEC

GND

Vcc

IN

SW1

IN

SW2

AO

RFSH

IN

SW3

IN

SW4

53

GND

IN

signal from

Interrupt

Input

from

'See

the dip

Ground

5V

supply

Input from "See

the dip

Mam CPU

Used

rn the I/O

Refresh

signal from

Input

from

•See

the dip

Ground

input

the FDD

switch

The

switch

address

the

switch

the

main CPU.

from slot

svstem

port

system

3 or 4.

(Floppy Disk Drive) assignment

description,

assignment

description,

bus

select

the

assignment

description,

provided

logic

in the MMR to

main CPU.

provided

dip

switch,

switch.

separately.

designate device

separately.

(Write)

(Interrupt

dip

switch

(Section)

(Refresh)

from

(A),

number.

No. 3, 4)

No. 1.

54

56

Input

from

the

system

FD1

55

Vcc

FD2

IN

'See

5V

supply.

Input *See

the dip

from

the dip

switch

the FDD

swi'ch

assignment

description,

assignment

description, provided

dip

switch.

provided

dip

switch (A),

separately.

No. 2.

separately.

MX

3500

60

61

62

63 64

65

66

57

58

59

No

Polarity

Signal

SYSR

COAB

RO1B

RO2B R03B

Name

FD3

GND

Vcc

RDB

CLK

IN/OUT

IN

OUT

IN

OUT

IN

System

reset

signal.

Used

to

reset

I/O

port

Input

from

the

sytem

"See

the dip

switch description, provided

Shared

RAM

select

signal.

Address

of the

shared

Select

signal

for 8KB

Valid

when

SD2 is

active (ROM

Ground

5V

supply

Select

signal

for 8KB

Valid

when

SD2 is

active (ROM

Read

signal

from

the

EAIT signal generation

in the

MMR.

assignment

RAM is

area

allocated

area

allocated

main CPU.

clock.

dip

switch.

separately.

*F800-#FFFF

to

slot

1.

based

BASIC)

to

slot

2 or 3

based

BASIC)

Function

(System

for the

(Common

and SD3

(ROM

and SD3

(ROM2,

(Read)

(Clock)

main

(RAM

Reset)

CPU

1)

3)

RAM

based

Address)

BASIC)

BASIC).

Select

signal

for 8KB

area

allocated

67

68

R04B

MPX

OUT

Valid

when

RAS/CAS High:

Row

SD2 or SD3

address

(RAM based BASIC)

switching

address Low: Column

signal

to

slot

for the

4.

main

are

active.

CPU

address

(ROM

DRAM.

4)

(Multiplex)

69

70

71

72

73

GND

CASB

GND

INTB

IN

OUT

IN

OUT

Ground

CAS

(Column

•Refresh

Ground

Not

used

Address) signal

for the RAM

only.

for the

main

CPU 64K

DRAM.

(Column

(Interrupt)

Address

Select

Buffer)

-

22

-

MAIN

CPU

I/O

PORT

IN

MEMORY

ADDKKSS

A7

A6

A5|A4|A3|A2|Al|AO

1

1 1 1 1 1 0 1

11111110

11111111

MAPPER

HEX

KI)

FE

FF

UHUS

01 DO D7

Dl

DO

1)7 D6 D5 D4 D2 Dl DO D4 D3 D2 Dl DO D7 D6 D5

1)4 D3 D2 Dl DO D7

D6

1

O

r\i IT

OUT

INI

IN

SKQB

1 1

SKI

S

MS] MSO

M<\3

MA2

MAI MAO

MO2 MOI MOO

SW4 b«3

M\2

Sttl

she

FD3 FD2

H>1

SKDY

SACK

1NP2

I

MM

IN'1'0

MF2

Mhl

SRQ

Bus

request from

Sub-CPU

Memory

Bank

reset signal

system

select

signal

define

to

memory

_J

Bank

select signal

System

FD

assign

•f>

Sub-CPU READY

•p

Sub-CPU acknowledge

Interrupt

assign

status

to

memory

switch

the mam CPU to the

area

of

COOO-FFFF.

area

of

2000-3FFF.

(SW8)

signal

M

7.3500

sob-CPU

1. All

output

signals

except

for

SRBQ

2.

Noted

with a star

rest

of

others

are

#1 I/O

port

output

the

addresses.

(

ME2->8000~BFFF

I

ME1->-4000~7FFF

When

ME1 and ME2 are in

inhibited correspond This

during memory

to

is not

true during

are

reset

to low

that

goes

high.

mark

"£" are

processed

in the

of ME1 and ME2

high state.

addresses

overlayed

addresses

SD1

mode.

level

upon

input/output

signals,

LSI.

uses

the

memory

RSAB

in

RAM-A

for MET and ME2

power

on,

and

(RASA)

that

at

is

i i -^.

"fJ~

11

" I "

H

Wait WAIT

Its

outut

Mm

t

1 H

j H

i

timing

is

issued once

M II TO t

n (i H j 1 I 1 H M 2 h

,

<|

TvfT J i\=TjTNT7

1

j X X

H 1 H | 1 H j H j H H

j H j H | H

l

FKOM

M" l

""•»

generator

is tri

state

MOI«m

"

per

01

Tisn

JM3

SI

main

in

iri T

1

T4h

IM 2

IM 1

1

X 1 1

H L

H H

I ' 1 H

L

TO

CPU

fetch

cycle.

hkoM

"-

L

1 H |

fMont

|M It

T"

H I H

1

h

HA

MZ3500

3-5.

Memory

(ROMIPL,

RAMCOM,

To

main

CPU

S-RAM) select circuit

1)

ROM-IPL

As bus (LS245) is 2Y of the the the connected address operation times.

2)

RAM-COM select

When select so put 4Y is low and low

3)

ROM-IPL

Normally, to Vcc

If A13 of the of the level. output

to low

can

ly, it

select

ROM IPL

buffers

are

set to a low

outputs

IPL-ROM input

that

level,

of the

ROM-IPL

to

1000

test

RAM COM is input

input

so as to

select

the level thru

LS139 LS147

Should

2Y of the

lebel

access

an

would

by the

turns

to low

(LS244,

enabled.

of the

S of the

1A-4A

that A15

SRD, SMRQ

to

be

S of the

level

to

LS157

are

from

are

then

(^16)

of the

Vcc,

IPL for the

IPL-ROM.

dip

switch

by the

low, SRES

selector

becomes

either

enable

by

sub-CPU

select

signal

inputs

were becomes or CE of the

LS157

read

the

address

range

from

0000

main

CPU

level after

LS367)

enable

read

to be at low

low

and

data selector

input

then

go low so

main

CPU.

by the

address

main

Switch

which

main

CPU

high,

1C

(LS157)

effective.

1Y

(WE)

to

read

or

S of the

1B-4B

are

level

so

ROM-IPL

be at low

or OE of the

ROM-IPL.

of

0000

to

OFFF, actually.

power

on

data

bus

1C

1A-4A.

main

should

or 2Y write

selector

enabled

level,

Though

to

The 3Y and

that

CE and OE

The

contents

CPU. Because

buffer

(LS367)

CPU

will

SW2BA

be ON at all

and

SACK low,

is in low

That

is, the

(OE) becomes

RAM-COM.

is

by sub

the

output

that

the

output

should

be at low

lebel

as

ROM-IPL

the

1FFF theoretical-

address

buffer

(LS157)

be at is the

the

state

out-

pulled

up

CPU.

YO

3Y

well,

the

turnde

sub-CPU

of

is

4)

RAM-COM

Y1 of the and

AS14 4B of the Y4 to low signal

If

SMRQ, point, however,

5) RAM SMRQ, to

select following these

RAMSA

RAMSB

RAMSC

RAMSD

select

by

sub-CPU

LS139

changes

and

AS15

LS157

is at low

level,

so

should

become

SRD or

it

enables

(SA,

SRD

conditions:

..

read

is

2000

to

SB, SC, SD)

(Of)

the

sub-CPU dedicated RAM, SA-SD.

chip

select

ASVi,

(address

AS11,

(address

AS11, AS12, AS13, AS14, AS15

(address

AS11, AS12, AS13, ASK,

(address

to low

are

low.

In

level

which

that

CS of the

effective.

SMRQ,

3FFF

or

AST2,

SWR is in low

(OE)

or

write (WE). Address range,

select

by

SMRQ,

signal, then becomes valid under

AS12, AS13, AS14, AST!

4000^17FF)

4800-4FFF)

5000-57FF)

5800-5FFF)

SWR

AST3,

level

when AS13

other words,

brings

RAM-COM

sub-CPU

(WE)

is at low

AS14, AS15

ASHi

the

chip

level

is

high

input

output

select

at

this

level Tne

-

24

-

4-1. Specification

Display

memory

3KB

(characit>-s!

96KB.

max

4. CRT

Ust

of

high

(graphic

DISPLAY

resolution

Option

i

CRT

Use

of

medium resolution (,RT

Character

Graphic display (option)

Merge

display

of

chracters

and

Screen

structure

Colors

32KB

96KB

Screen

graphics

structure

Programmable

Character

Attributes

type

merge

80

chrs

x 25

lines.

40

chrs

x 25

lines,

8x16

dots

With

lower

case

descenders

255

characters Alphanumencs 26

small

97

graphic

Revers, Programmable

8

colors, programmable

640 x 400

Color

designation

640 x 400

Color

designation

Color

(one frame)

Merge

any

Merge a character

and 69

characters

patterns

vertical

line,

for

dots,

B/W

dots.

B/W

graphic screen

each

for

possible

screen

80

chrs

x 20

40

chrs

x 20

symbols

blink,

horizontal line

character

for

each

(one frame) each

character

(three frames)

for

(1 to 3

with a graphic

lines lines

character

each

frames)

character

screen

8x8

dots

Blink,

revers

Programmable

640 x 200

Color designation possible

640 x 200

Color designation possible Color

(Two

for

dots,

dots.

frame)

B/W

each character.

(Two frames)

(six frames)

for

each

character

for

each character

Background color

Control

of two

independent

Control channel number

Light

pen

input

(option)

screens

Choice

of 8

Possible

to d

Separate

graphic

Possible

to

affix

Selection

of

Incorporation

Scans

coordinates

colors

aplay

on

separate

two

screens

can be

merged into

attributes

character/non-character

of two

(CRT2 only)

independent video

and

character

code

screens

screen

outut

ongind1 graphic

one

display

channels

screen

and

character

screen

Summary

Character

Screen (Characters x ines)

Color designation

Small Line Display

Frames

Screen overlay

of

video

^""~-\^

Function

^^\^^

Elements

structure

tetter

descenders

creation

memory

display

specification

Type

of

monitor

Basic Option 1 (48KB) Option

II

(96KB)

Basic Option 1 (48KB) Option

II

(96KB)

Basic

Option 1 (48KB)

Option

II

(96KB)

Characters

ASCII

8x16

8 x 20

5x14

80 x 25 80 x 20 40 x 25 40 x 20

1

One

character

one

graphic

One

character

three

graphic

mode mode

mode

O O

3KB

frame

t t

Green

Not

possible

screen

srrpens

High

resolution

monitor

Graphics

640 x 400 dot

No

Against

igain-,t

B/W

32KB

frame

1

frame

3

frames

CRT

(option)

(640

x 400

dots

Characters ASCII

8x 16 8x 20

5x14

80 x 25 80 x 20 40 x 25 40 x 20

By

character

t

O X

3KB

1

frame

t t

One

character screen against

one

graphic screen

One B/W

character

three

graphic

One

color

one

character

graphic

Table

mode)

Color

screens

screen

1

monitor

Graphics

By

32KB

*-

screen

(option)

Color

640 x 400

character

By

dot

II),96KB(II)

No

frame

1

frame

1

frame

against

Characters ASCII

8x8

8x10

5x7

80 x 25

80x20

40 x 25 40 x 20

1

frame

One

character

three

graphic

X X

3KB

(1

t t

Green

page)

screens

Medium

monitor

«-

screen

'

resolution

Graphics

640 x 200

No

3

frames

6

frames

against

(option)

B/W

16KB

frame

CRT

(640

1

frame

One B/W

three One one

x 200

dots

mode)

Color

monitor

Characters

ASCI:

8x8

8x10

5x7

80 x 25 80 x 20 40 x 25 40 x 20

By

character

t t

X X

3KB

(1

page)

t

character screen agamst

graphic

screens

color

character

graphic

screen

Graphics (option)

Color

640 x 200

By

dot

t

48KB

No

frame

1

frame

2

frames

-

screen

against

•

I

NOTE

Graphics option

1)

Character

1.1.

Screen

CRT

Character

ASCIL

Dip

switch

high

resolution/medium resolution CRT.

Display

1-2.

Character

ASCII

Graphic symbol

NOTE:

structure

used

in the mam

mode

In the

vertically together As or 7 x 7,

display

High

resolution

(640

fH = 20

(New)fV

80 x 25 80 x 25 40 x 25

40 x 20

must

structure

Elements

8x 16

8 x 20

1

Small

letter

and

line creating

functions

case

x 400

be

640 x 400

CRT

dot)

9KHz

= 47 3Hz

lines lines lines lines

unit

is

used

chosen

by

and

picture elements

Structure

5 x 14

8 x 16

descenders

are

available.

of 8 x 8 and

programming.

adjoining graphic symbols

in the

25-line mode.

for

character

structure

decision must

Medium

resolution

(640

x 200

dot)

fH = 15

7KHz

fV =

60Hz

-

to

select assignment

640 x 200

creating

are not

Structure

5x7

8x8

Elements

8x8

8x10

I

Small letter descenders and

line functions available.

8x16 picture elements,

will

of 6 x 14, 7 x 14,

be

given

on an

actual

pattern.

2)

Graphic display

(option)

(High resolution CRT) (Medium resolution CRT)

640 dot 640 dot

400 dot

Dot

pitch

Horizontal

vertical

= 1

Dot

pitch

Horizontal

vertical

= 1 : 2

CRT

joint

6x7,

dot

200

of

dot

4)

Attribute

AT1

Horizontal

AT2 AT3 AT4

5}

Screen

It

will

be of one graphic Table

1.)

In the screen screen the

character — both

to

produce image.

00

o

Three

basic

colors

B/W

Vertical

Reverse

Blink

line

Color

line

Blink

overlay

possible

to

have

character (screen

screens.

color and element

(For

mode,

other

— the one

detail

if

there

designated

colors

o

O

o

Designated

cter.

B

R

Line

G

exist

(Line played ters

an

overlaid

and a

of

overlay

are two

for a dot on the

designated

will

(Red)

color designated

character

(Blue)

O Dot

graphic

(Violet)

Q Dot

two

M7

W

Whne

for

and

character r,,uy

in the

same

may

also

on the 80

x 25

lines

screen.)

screen

that

maximum

screen,

colors

for a

character

be

merged sltorjpther

attribute

color

designated

dot.

composed color

of

Jj>i"jrn*ion:.

3500

each

element

be

consists

of

refer

in the

graphic

more

chaia-

dis-

charac

three

to

same

on

by

than

3)

Color

designation

Eight

colors

are violet, red, blue, black) Color

designation

ASCII

48K

Graph

Background

8

colors

|

96 K

for

byte

color

designation

usable

640 x 400 dot

By

(white,

character character

dot

yellow,

cyan, green,

640 x 200 dot

By

character

By

dot

By

dot

MZ

3500

6)

Screen overlay

CRT's As

there

are two

sible

to

display

video

display

and

video

two

unit

displaying

output

independent

Overlay

is

on two

channels

screens

possible

independent

it

will

be pos

on

separate

on

either

of

screens selection

(See

is

needed

preceding

for

screen

item

5) ) The

overlay

following

bit

Address

AS AS AS AS

Hex

3210

50

0000

;p

i

51

52

53

54

55

(50)

000

0010

0011

0100

0101

Data

DS

DS DS

2 1 0

1

Internal

S

gnat

of CSP

ECH1 ECH2 EAT2

SR1 SR2 SR3 SR4 SR5 SR6

BGC

B

BGC R

BGCG COLOR BODER

08/16 40/80

name

Choice

of Cho ce of Choice

of on

CRT2

Displays

on

Displays

on

Displays

on

Displays

on

Displays

on

Displays

on

[

Choice

Color mode Border

color mode

Defines

the

Defines

display digits

(0

40

digits

outputting outputting whether

(0 No 1

CRT1 CRT1 CRT1 CRT2 CRT2 CRT2

of

data

the

character

the

character

attribute

or

Yes)

the

blue elements contained

the red

elements contained

the

green elements contained

the

blue elements contained

the red

elements

the

green elements contained

background color display

in

effect

size

for the

graphic

for the

character screen

1 80

digits)

Function

screen screen

cursor

contained

RAM (0 8

on

CRT1

on

CRT2

be put on the

in the

m the

bits,

0 No 1 Yes 0 No 1 Yes frame that displayed

VRAM

1 16

bits)

;P2

56

0110

57

0111

5D

1101

NOTE Both CRT1

Output

to

CRT1

CH

( AT )

C.KA7

)

CH AI

)+(,!

Output

each

^ AT)

1

and

CRT2 must

to

each

CRT may be

CH(

(,f-

AT)

CH(Ar)+(,!

CH

(.1-

CH+GI

1

CRT2

AT)

1

possible

RA-400 V

RAM2

V

RAM1

25/20

08/16 40/80

be

high resolution CRT's (640 x 400)

possible

in the

Connection

Connection Connection 25

Defines Defines (0

in the

following

40

M

of a 400 of the 96K of

graphio

lines/20 lines switching

data

size

display digits

digits,

1 80

combination

CH

ASCII

GF

Graphic

screens

(AT)

Attached

raster

for the

digits)

screen,

bytes

GDC

graphic

with

CRT

VRAM

(0 25

RAM (0 8

character

or

medium

.

including

attribute

lines,

1 20

bits

screen

resolution CRT's

overlay

lines)

1 16

bits)

of two

'RO x

graphics

7)

ASCII

Uses 640 x 400 dots)

CG

an 8KB

MROM

dots (8x16 dots)

#OFFF

#0000

#1 FFF

contains

8x8 dot

(2K

byte)

! x 8 dot

(2K

byte)

two

patterns'

and 640 x 200

pattern

dots

For

Model

Without letter

descenders

(8x8

3200

lower-case,

series

With two

Refer

code

8 x 8 dot

kinds

of

to ROM

on

separate

format

patterns

address

information

coexist

and

data

MZ3500

#1 000

Address

and

(Example

8)

Element structure,

1)

25

of 5 x 12

line

8 x 16 dot

pattern

character

display

(4K

in

picture

dots

pattern

Element

640

mode

pattern

byte)

element

for 1 x 16

structure,

x 200 dot

With letter

elements)

and

line

character

lower-case,

(h i j)

D7| |

12

structure,

descenders

O

o

O

0

o o

ooooo ooooo

o o

0 0

o o

0 0

and

line

1)

25

line

DO

(Address)

/—

Character

\—

Line

area

X—

Area

where

640 x 400 dot

display

mode

Model 3500

.

#1000

#1001

#1002 #1003

#1004 #1005 #1006 #1007

#1008

#1009 #100A #1006 #100C #100D

#100E

.-

#100F

pattern

area

and

line

are

(Data)

#00

10

28 28 44 44

7C

44 44 44

44 00 00 00

overload

15 2

IASCD/JIS]

8

[Graphic

symbol

Without

line

12

'With

line

HL On

16th

ot the

element

case

display

HL and

to the

line

of

graphic VLare

right

of

pattern

VL

Line

In the

symbol

Both

overlaid

-

29

-

MZ3500

2)

10

20

line display mode

Graphic

Without

symbol

line

2)

20

line

20

\\NS\\\\Mi

20

display

8

ASCII

mode

With

HL On

VL

Line

e

VL

a In the

symbol display,

overlaid

j I Graphic symbol

line

18th

to the

element

does

case

to the

raster

not

of

right

join

graphic

VL is

pattern

of

9)

Cursor

Sharp

Reverse

10)

Light

Incorporates face. Accuracy:

Function:

11)

Difference

(1)

(2)

of the

pen

The

and

input

light

By

blink)

the

each

cursor:

light

Same

pen

input

pen, however,

character

as

connector

is an

seen

in

option.

Coordinates/character code

in

specification

There

are two mode (6x9 elements) ments).

In the

the

PC-3200, vertically adjacent graphic symbols

not

joint.

But, they

Model-3200

No

line

will

be

CRT

(640x200 dot).

It is

possible CRT, the

Model 3200

to

compatible

with

modes

for the

and

normal mode

will

joint

displayed

for the

display line

to

line

the

that

of

Model

graphic mode (6x8 ele-

of

25-line displaying

with

the

Model

3500

medium resolution

on the

high resolution

utilizing program

Model 3200

and its

inter-

3200

3200;

normal

of

do

Model

3500.

of

4-2.

1)

Structure

GDC1 (for

*07FF

#0000

DO-

VRAM Basic

3KB

Bit

structure

— — ______

Character

Graphic ! 48KB VRAM [ 96KB

Video

character)

2Kbit (

S-RA.M)

(ASCI

capacity

(including

VRAM

RAM

of

VRAM

#BFFF

Attribute

I

> 8

2Kbit

x4

ts-

L

of

RAM)

'

0000

-D7

1)8—Oil

Solid

line

48KB

Broken

line.

To be

the

Graphic

attibutes)

VRAM

CRT

j

640 x 400 dot

' 16 bit ,'

16

8

bu /

bit /

Graphic

word

GDC2 (for graphic)

16Kbit

xg

(G)

(D-RAM)

16Kh,t

(B)

DO-

-D7

D8-

option

added

to

comprise

96KB

option.

option

1:

option 2 96KB

640

x 200

8 bit / 8 bit /

16

bit /

16Kbit

(R)

-D15

48KB

do

i

word word

wo-d

i i t 1 1

j

i 1 1 1 1 i i

-

30-

2)

Read/write

(1)

Timing

V-RAM

from

Z 80 to

period

for

Read/write.

VRAM

display

and

H •

SYNC-

BLNK-

M 7 3500

//><-'

Range

wh°r?

GDC can

Fly

back

period

J

draw.

(2)

Timing

3)

Structure

(1)

When read/write

The buffer

that

Z-80

is

of

either

#07FF

#0000

(2)

During display

#07FF

the

Z-80

can

read/write VRAM

can

read/write VRAM when

empty

or

Full,

character VRAM

from

GDC

2KX8

ASC I I

8bi t

DO

"D7 V&

4bit

2KX8

and can be

(A)

2KX4

GDC

accessed

«-Dll

(B)

FIFO

by

refreshing characters any

during that

mode.

(A)

ASCI

I(8bit)

(

12bit

)

DO

Dl D2 D3 D4 D5 1)6 D7

the

can be

DO

display

read/write

(B)

Dl

D2

period.

within

D3

Number

one

raster

•

Blink

Reverse

(G)

Vertical

line

.

Horizontal line

of

in

(R)

(B)

#0000

12bi

t

MZ3500

4)

Graphic

1.

read/write Mode

The RAS,

The

(1)

VRAM

•

Block

Diagram

select signal

A14 and A1 5

address

640 x 200

memory

RASA, RASB

which

is

allocated

is

to

each area selected

Read/write

dots display mode

(MZIR03)

and

of

by

RASC

GDC-2.

Z-80

signal

are

generate

by

above

via the GDC

from

signal.

R

ASA ^ RAS • A14 • A15

RASB~

RAS • A14 • AlS ...

RASC

=• RAS • A14 • A15

2.

Display

mode A14 and A15 are not together.

By the

ated

by

CSP-2.

The

signal

output

signal

to VB and VR.

select:

of

08 for 200

During

RAMB the (08/16

0000 ~ 3FFF

8000 ~ BFFF

valid

DBIN

08/16 select,

signal then

and

signal

output

rasters.

displaying

4000-7FFF

RASA, RASB, RASC

from

GDC-2. 08/16 signal

after

P-5

conversion

to VB by

16 for 400

serial

rasters)

are

for

signal,

selected is

gener-

RAMA,

or

sprit

Option I #BFFF

(48K byte)

8bit

structure

+

8000

#4000

#0000

Option

II (96K 16bit

#BFFF

byte)

structure

#8000

#4000

*0000

Low

byte

G

B

8bit

High byte

R

8bit

B/W: 3 frames

1

Color: 1 frame

#3FFF

16K

A

16K

i

#0000

8bit

8bit 31,L

B/W: 6 frames Color: 2 frames

#3FFF

16K

#0000

16K

I

1

ifit.it

16bit

-

32-

(2)

640 x 400

Option

(48Kbyte) 16

Option

(96K byte)

dots display mode

I

#4000

bits

structure

II

16

bits

structure

# 3 KKK

*0000

(

BFFF

#8000

16K

#3FFF

#0000

B/W: 1 frame Color: 1 frame

i

16K

B/W: 3 frames Color: 1 frame

Color

can be

designated

sach

character.

M Z 3500

for

5)

Synchronize signal timing

(1)

For 640 x 200

Dot

2XCCLK

Horizontal display

HFP

HS

HBP

Vertical

VFP

VS

dots

fH =

15.87kHz

fV

= 60 Hz

clock (OD)

display

time

#4000

#0000

display

time

mode

16bit

GDC-1

Character

16K

(80

display

(16MHz) (

8MHz)

(4MHz) <2MHz>

40MS

?A«

6>js

10/js

1

2.6ms

1.2ms

1 ms

digits)

(40

digits)

#0000

16bit

8

bits

16MHz

4MHz

-

•^(14 Chr.)

(1?Chr

(tREF-0.8ms)

-

(20

Chr.)

-

16K

16bit

X

: Y - 1 : 2

graphic)

GDC-2

)

16

bits

16MHz

2MHz

-

10MS

5^s

(tREF = 1.6ms)

8ns

-

j

VBP

Total

rasters:

Display

raster:

261

200

rasters

1.8ms

—-1 r~-

•—n.

-