Sharp LH5P864N-80 Datasheet
LH5P864
CMOS 512K (64K × 8) Pseudo-Static RAM
FEATURES
•• 65,536 × 8 bit organ ization
•• Access time: 80 ns (MAX.)
•• Cycle ti me: 140 ns (MIN.)
•• Single +5 V p owe r su ppl y
•• Powe r consu mption :
Operating : 44 0 mW (MAX.)
Standb y (TTL level): 22 mW (MAX.)
Standb y (CMOS level): 2.75 mW (MAX.)
•• Operatin g temperature: 0 to 70°C
•• TTL compatible I/O
•• 512 refresh cycles /8 ms (MAX.)
•• Available for auto-refresh and
self-refresh modes
•• Package: 32-pin, 525 -mil SOP
DESCRIPTION
The LH5P864 is a 512K-bit P seudo-Static RA M organized as 65,536 × 8 bits. It is fabricated using silicon-gate CMOS process technology. With its built-in
oscillator, it is easy to refresh memories without an
external clock.
PIN CONNECTIONS
5P864-1
TOP VIEW
5
6
7
8
11
12
A
0
A
3
26
25
24
23
22
21
18
A
5
A
4
9
10
A
1
A
2
20
19
A
6
A
9
A
11
A
10
13
14
15
28
27
I/O
0
A
13
16
17
I/O
2
OE/RFSH
CE
1
A
7
GND
I/O
4
I/O
3
I/O
5
A
8
32-PIN SOP
3
4
A
12
30
29
CE
2
A
14
R/W
1
2
NC
32
31
V
CC
TEST
NC
I/O
1
I/O
6
I/O
7
Figure 1. Pin Connections for SOP Package
1
I/O
1
CLOCK
GENERATOR
CE
1
R/W
A
12
A
13
A
14
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
11
A
10
A
2
A
1
A
0
COLUMN
ADDRESS
BUFFER
ROW
ADDRESS
BUFFER
REFRESH
ADDRESS
COUNTER
DATA
IN
BUFFER
DATA
OUT
BUFFER
I/O
SELECTOR
COLUMN
DECODER
SENSE
AMPS
ROW
DECODER
EXT/INT
ADDRESS
MUX
REFRESH
CONTROLLER
REFRESH
TIMER
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
V
BB
GENERATOR
GND
V
CC
5P864-2
I/O
0
RFSH
OE/
12
11
10
9
8
7
6
5
27
26
23
25
4
28
3
22
24
29
16
32
13
14
15
17
18
19
20
21
30
CE
2
MEMORY
ARRAY
256K
MEMORY
ARRAY
256K
A8 - A
14
A0 - A
7
1
TEST
1
Figure 2. LH5P864 Block Diagram
PIN DESCRIPTION
SIGNA L PIN N AME
A0 - A
14
Addre ss input
R/W Read/ Write En ab le i npu t
OE/RFSH
Outpu t E nab le inp ut/R efr esh
input
CE1, CE
2
Chip Ena ble in put
I/O0 - I/O
7
Data inp ut/out put
SIGNAL PIN NAME
V
CC
Power Sup ply
GND Ground
Test Test In put
NC No Connec tion
LH5P864 CMOS 512K (64K × 8) Pseudo-Static RAM
2
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT NOTE
Appli ed v ol tage on an y p in V
T
-1.0 to +7.0 V 1
Output sh ort ci rcu it c urr ent I
O
50 mA
Power dis sipati on P
D
600 mW
Operating temperature Topr 0 to +70
°C
Storage temperature Tstg -65 to +150
°C
NOTE:
1. The maximum applicable voltage on any pin with respect to GND.
RECOMMENDED OPERATING CON DITIONS (TA = 0 to +70°C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Suppl y v olt age V
CC
4.5 5.0 5.5 V
Input vol tage
V
IH
2.4 VCC + 0.3 V
V
IL
-1.0 0.8 V
CAPACITANCE (TA = 0 to +70°C, f = 1MHz, VCC = 5.0 V ±10%)
PARAMETER CONDITIONS SYMBOL MIN. MAX. UNIT
Input cap acitan ce
A
0
- A
14
C
IN1
8pF
R/W,
OE/RF SH C
IN2
8pF
CE1, CE
2
C
IN3
8pF
TEST
1
C
IN4
10 pF
Input/ Out put ca pac ita nce I/O
0
- I/O
7
C
OUT1
10 pF
DC CHARACTERISTICS (TA = 0 to +70°C, VCC = 5.0 V ±10%)
PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE
Operat ing cu rre nt I
CC1
tRC = tRC (MIN.) 80 mA 1, 2
Standb y c urr ent I
CC2
TTL inpu t
4.0 mA 1, 3, 5
CMOS i npu t
0.5 mA 1, 3, 6
Self r efr esh av era ge c urr ent I
CC3
TTL inpu t
4.0 mA 1, 4, 5
CMOS input 0.5 mA 1, 4, 6
Input lea kag e c urr ent I
LI
0 V ≤ VIN ≤ 6 .5 V,
0 V ex cep t o n t est pin s
-10 10
µA
Output le aka ge cur ren t
I
LO
0 V ≤ V
OUT
≤ VCC + 0.3 V,
Output s i n H igh -Z s tat e
-10 10 µA
Output HI GH vol tag e V
OH
I
OUT
= -1 .0 m A 2.4 V
Output LO W v olt age V
OL
I
OUT
= 4. 0 mA 0.4 V
NOTES:
1. Specified values are w ith outputs open.
2. I
CC1
depends on the cycle time.
3.
CE1 = CE2 = VIH, OE/RFSH = V
IH
4. CE1 = CE2 = VIH, OE/RFSH = V
IL
5. CE1 = CE2 = VCC – 0. 2 V, OE/RFSH = V
CC
– 0.2 V
6.
CE1 = CE2 = VCC – 0. 2 V, OE/R FSH = 0.2 V
CMOS 512K (64K × 8) Pseudo-Stat ic R AM LH5P 864
3
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