Sharp LH5332600T, LH5332600N Datasheet
LH5332600
CMOS 32M (4M × 8/2M × 16) MROM
FEATURES
•• 4,194,304 × 8 bi t organ izatio n
(Byte mode: BYTE = VIL)
2,097,1 52 × 16 bit organi zation
(Word mode: BYTE = VIH)
•• Access time: 100 ns (MAX.)
•• Supply curre nt :
– Operating: 100 mA (MAX.)
– Standby: 100 µA (MAX.)
•• TTL compatible I/O
•• Three-state output
•• Singl e +5 V p owe r su ppl y
•• Static operation
•• Packages:
44-pi n , 600 -mil S OP
48-pi n , 1 2 mm × 18 mm
2
TSOP (Type I)
•• Others :
– Non programmab le
– Not de sign ed o r rate d as rad iatio n
hardene d
– CMOS process (P typ e sil icon
substrate)
DESCRIPTION
The LH5332600 is a 32M-bit mask-programmable
ROM organized a s 4 ,194,304 × 8 bits (Byte mode) or
2,097,152 × 16 bits (Word mode) that can be selected
by a BYTE input pin. It is fabricated using silicon-gate
CMOS process technology.
PIN CONNECTIONS
5332600N-1
TOP VIEW
5
6
7
8
11
12
34
33
32
31
30
29
26
9
10
28
27
A
15
A
16
BYTE
13
14
15
36
35
A
13
16
25
D15/A
-1
(NOTE)
D
13
D
5
D
6
A
14
44-PIN SOP
3
4
38
37
1
2
40
39
A
10
D
14
D
7
24
23
V
CC
D
4
D
12
17
18
19
20
A
9
A
11
A
12
41
A
8
A
19
A
20
42
21
OE
A
1
A
0
GND
CE
A
2
D
8
D
9
A
3
A
4
A
5
A
6
D
1
A
7
D
2
D
3
D
10
A
17
A
18
D
0
GND
D1122
NC
43
44
NOTE: The D15/A-1 pin becomes LSB address input (A-1)
when the BYTE pin is set to be LOW in byte mode and
data output (D
15
) when set to be HIGH in word mode.
Figure 1. SOP Pin Connections
1
5332600T-1
TOP VIEW
2
3
4
5
8
9
A
10
A
13
45
44
43
42
41
40
37
34
A
15
A
14
6
7
A
11
A
12
39
38
D
7
D
3
10
11
12
47
46
D
15/A-1
(NOTE)
A
9
13
36
35
A
8
48-PIN TSOP (Type I)
14
15
16
17
18
19
20
21
31
28
33
32
30
29
D
2
D
9
D
1
D
8
OE
D
10
GND
48
1
A
16
BYTE
22
27
D
0
GND
23
26
V
CC
24
25
GND
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
CE
GND
D
14
D
13
D
5
D
12
D
4
D
6
V
CC
GND
D
11
GND
A
19
A
20
A
18
A
17
NOTE: The D15/A-1 pin becomes LSB address input (A-1)
when the BYTE pin is set to be LOW in byte mode and
data output (D
15
) when set to be HIGH in word mode.
Figure 2. TSOP Pin Connections
LH5332600 CMOS 32 M (4M x 8/2M x 16) MROM
2
5332600N-2
A
4
A
3
A
13
A
12
A
11
A
10
A
9
37
38
39
40
4
7
8
A
8
A
7
A
5
MEMORY
MATRIX
(4,194,304 x 8)
(2,097,152 x 16)
SENSE AMPLIFIER
42
33
6
A
1
A
0
10
11
A
2
9
41
A
6
5
A
14
36
ADDRESS BUFFER
CE
ADDRESS DECODER
COLUMN SELECTOR
CE
BUFFER
OE
BUFFER
A
15
35
A
16
34
12
TIMING
GENERATOR
A
17
3
BYTE
A
18
2
A
19
43
A
20
44
ADDRESS
BUFFER
BYTE/WORD
SWITCHOVER
CIRCUIT
14
OE
DATA SELECTOR/OUTPUT BUFFER
D
3
D
2
D
1
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
4
D
5
D
13
D
0
D
14
D
15
22
20
18
16
26
19
17
15
21
30
24
25
27
29
31
28
31
A
-1
V
CC
23
GND
13 32
Figure 3. LH5332600 Block Diagram
PIN DESCRIPTION
SIGNA L PIN NAME
A
-1
- A
20
Addr ess in put
D
0
- D
15
Data ou tput
BYTE
×8bit / ×16 bi t
(byt e/wo rd) mo de
sele ct input
CE Chip en abl e in pu t
SIGNAL PIN NAME
OE Outpu t e nab le i np ut
V
CC
Power su ppl y
GND Groun d
NC
No co nne cti on
(Non wire bonding)
CMOS 32M (4M x 8/2M x 16) MROM LH5332600
3
Loading...