Sharp LH532600T, LH532600N, LH532600D, LH532600TR Datasheet
LH532600
FEATURES
•• 262,144 w ords × 8 b it organ izatio n
(Byte mode)
131,072 words × 16 bit orga niza tion
(Word mode)
•• Access time: 100 ns (MAX.)
•• Static operation
•• TTL compatib le I/O
•• Three-state outputs
•• Singl e +5 V po we r su ppl y
•• Powe r consu mption :
Operating : 412.5 mW (MAX.)
Standby: 550 µW (MAX.)
•• Mask-programmable control pin:
Pin 1 = OE
1
/OE1/DC
•• Packa ges:
40-pi n , 600 - mil D IP
40-pi n , 525 - mil S OP
48-pi n , 1 0 × 20 mm
2
TSOP (Type I)
DESCRIPTION
The LH532600 is a 2M-bit mask-programmable ROM
organized as 262,144 × 8 bits (Byte mode) or 131,072
× 16 bits (Word mode) that can be selected by BYTE
input pin. It is fabricated using silicon- gate CMOS process technology.
PIN CONNECTIONS
CMOS 2M (256K × 8 /128K × 16) MROM
532600-1
TOP VIEW
2
3
4
5
8
9
A
1
A
4
37
36
35
34
33
32
29
26
A
6
A
5
6
7
A
2
A
3
31
30
A
12
A
14
A
16
D15/A
-1
(LSB)
D
6
10
11
12
39
38
13
28
D
7
27
D
14
CE
GND
A
13
40-PIN DIP
40-PIN SOP
14
15
16
17
18
19
20
23
25
24
22
21
V
CC
D
10
D
3
D
2
OE
D
1
D
9
D
8
D
11
A
15
BYTE
D
13
40
1
A
7
OE1/OE1/DC
A
8
GND
D
0
A
0
A
9
A
10
A
11
D
5
D
12
D
4
Figure 1. Pin Connections for DIP and
SOP Packages
1
532600-2
TOP VIEW
2
3
4
5
8
9
A
10
A
13
45
44
43
42
41
40
37
34
A
15
A
14
6
7
A
11
A
12
39
38
D
7
D
3
10
11
12
47
46
D
15/A-1
A
9
13
36
35
A
8
48 PIN TSOP (Type I)
14
15
16
17
18
19
20
21
31
28
33
32
30
29
D
2
D
9
D
1
D
8
OE
D
10
GND
48
1
A
16
BYTE
22
27
D
0
GND
23
26
V
CC
24
25
GND
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
CE
GND
D
14
D
13
D
5
D
12
D
4
D
6
V
CC
GND
D
11
GND
NC
NC
NC
OE
1
/OE1/DC
NOTE: Reverse bend available on request.
Figure 2. Pin Connections for TS OP Packag e
LH532600 CMOS 2M MROM
2
532600-3
A
3
A
2
A
12
A
11
A
10
A
9
A
8
36
37
38
39
3
6
7
A
7
A
6
A
4
MEMORY
MATRIX
(262,144 x 8)
(131,072 x 16)
SENSE AMPLIFIER
2
31
5
40
A
5
4
A
13
35
ADDRESS BUFFER
CE
ADDRESS DECODER
COLUMN SELECTOR
CE
BUFFER
OE
BUFFER
A
14
34
A
15
33
10
TIMING
GENERATOR
A
16
32
BYTE
ADDRESS
BUFFER
BYTE/WORD
SWITCHOVER
CIRCUIT
1
OE1/OE1/
DC
DATA SELECTOR/OUTPUT BUFFER
D
3
D
2
D
1
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
4
D
5
D
13
D
0
D
14
D
15
20
18
16
14
24
17
15
13
19
28
22
23
25
27
29
26
29
A
-1
V
CC
21
GND
11 30
A
1
8
A
0
9
12
OE
NOTE: Pin numbers apply to the 40-pin DIP or SOP.
Figure 3. LH532600 Block Diag ram
PIN DESCRIPTION
SIGNAL PIN NAME NOTE
A–1 – A
16
Addres s i npu t 1
D
0
– D
15
Data o utp ut 1
BYTE Byte/w ord mo de swi tch 1
CE Chip e nab le inp ut
SIGNAL PIN NAME NOTE
OE Output en abl e i npu t
OE
1
/OE1/DC Output en abl e i npu t 2, 3
V
CC
Power su ppl y (+ 5 V)
GND Ground
NOTES:
1. The D15/A–1 pin becomes LSB address input (A–1) when the B YTE pin is set to be LOW in byte mode, and data output (D15) when set to
be HIGH in word mode.
2. Active levels of OE
1
/OE1/DC are mask-progr ammable. When DC is selected out of OE1/OE1/DC, it is fixed to an active level. Then it is
recommended to apply either V
IH
or VIL to the DC p in.
3. DC = Don’t care.
CMOS 2M MROM LH532600
3
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