Sharp LH28F016SUT-70, LH28F016SUT-10 Datasheet
LH28F016SU
1
16M (1M × 16, 2M × 8) Flash Memory
Figure 1. TSOP Configuration
FEATURES
• User-Configurable x8 or x16 Operation
• User-Selectable 3.3 V or 5 V V
CC
• 70 ns Maximum Access Time
• 0.32 MB/sec Write Transf er Rate
• 100,000 Erase Cycles per Block
• 32 Independently Lockable Blocks
• 5 V Write/Erase Operation (5 V V
PP
)
– No Requirement for DC/DC Converter
to Write/Erase
• Minimum 2.7 V Read capability
– 160 ns Maximum Access Time
(V
CC
= 2.7 V)
• Revolutionary Architecture
– Pipelined Command Execution
– Write During Erase
– Command Superset of
Sharp LH28F008SA
• 5 µA (Typ.) I
CC
in CMOS Standby
• 1 µA (Typ.) Deep Power-Down
• State-of-the-Art 0.55 µm ETOX™
Flash Technology
• 56-Pin, 1.2 mm × 14 mm × 20 mm
TSOP (Type I) Package
28F016SUT-1
TOP VIEW56-PIN TSOP
2
3
4
5
8
9
A
16
A
19
A
20
53
52
51
50
49
48
45
42
NC
6
7A
17
A
18
47
46
RY/BY
DQ
15
DQ
14
GND
GND
10
11
12
55
54 OE
V
CC
13 44 DQ
4
43 V
CC
A
15
DQ
7
14
15
16
17
18
19
20
39
36
41
40
38
37
DQ
3
DQ
10
DQ
2
V
CC
A
10
A
9
A
11
V
PP
RP
CE
0
A
8
DQ
9
WE
DQ
6
DQ
13
DQ
11
56
1
CE
1
3/5
WP
21
22
23
24
25
26
27
28
A
4
A
3
A
5
A
7
A
6
GND
A
2
A
1
34 DQ
8
35 DQ
1
31
33
32
30
29
A
0
BYTE
NC
NC
DQ
0
A
14
A
13
A
12
DQ
5
DQ
12
LH28F016SU 16M (1M × 16, 2M × 8) Flash Memory
2
Figure 2. TSOP Reverse Bend Configuration
INTRODUCTION
Sharp’s LH28F016SU 16M Flash Memory is a revolutionary architecture which enables the design of truly
mobile, high performance, personal computing and communication products. With innovative capabilities, 5 V
single voltage operation and very high read/write performance, the LH28F016SU is also the ideal choice for
designing embedded mass storage memory systems.
The LH28F016SU is a very high density , highest performance non-volatile read/write solution for solid-state
storage applications. Its symmetrically blocked architecture (100% compatible with the LH28F008SA 8M
Flash memory), extended cycling, low power 3.3 V
operation, very fast write and read performance and
selective bloc k locking provide a highly fle xible memory
component suitable for high density memory cards,
Resident Flash Arrays and PCMCIA-ATA Flash Drives.
The LH28F016SU’s dual read voltage enables the
design of memory cards which can interchangeably be
read/written in 3.3 V and 5.0 V systems. Its x8/x16
architecture allows the optimization of memory to processor interface. The flexible block locking option
enables bundling of executable application software in
a Resident Flash Array or memory card. Manuf actured
on Sharp’s 0.55 µm ETOX™ process technology, the
LH28F016SU is the most cost-effective, high-density
3.3 V flash memory.
DESCRIPTION
The LH28F016SU is a high performance 16M
(16,777,216 bit) block erasable non-volatile random
access memory organized as either 1M × 16 or 2M × 8.
The LH28F016SU includes thirty-two 64K (65,536)
blocks or thirty-two 32-KW (32,768) blocks. A chip
memory map is shown in Figure 4.
The implementation of a new architecture, with many
enhanced features, will improve the device operating
characteristics and results in greater product reliability
and ease of use.
Among the significant enhancements of the
LH28F016SU:
• 5 V Write/Erase Operation (5 V V
PP
)
• 3.3 V Low Power Capability (2.7 V V
CC
Read)
• Improved Write P erformance
• Dedicated Block Write/Erase Protection
A 3/5» input pin reconfigures the device internally for
optimized 3.3 V or 5.0 V read/write operation.
The LH28F016SU will be available in a 56-pin,
1.2 mm thick × 14 mm × 20 mm TSOP (Type I) package. This f orm factor and pinout allow for v ery high board
layout densities.
28F016SUT-17
TOP VIEW56-PIN TSOP
2
3
4
5
89A
16
A
19
A
20
53
52
51
50
49
48
45
42
NC
6
7A
17
A
18
47
46
DQ
15
DQ
14
GND
GND
10
11
12
55
54OE
V
CC
1344DQ
4
43V
CC
A
15
DQ
7
14
15
16
17
18
19
20
39
36
41
40
38
37
DQ
3
DQ
10
DQ
2
V
CC
A
10
A
9
A
11
V
PP
RP
CE
0
A
8
DQ
9
WE
DQ
6
DQ
13
DQ
11
56
1
CE
1
3/5
WP
21
22
23
24
25
26
27
28
A
4
A
3
A
5
A
7
A
6
GND
A
2
A
1
34DQ
8
35DQ
1
31
33
32
30
29
A
0
BYTE
NC
NC
DQ
0
A
14
A
13
A
12
DQ
5
DQ
12
RY/BY
16M (1M × 16, 2M × 8) Flash Memory LH28F016SU
3
Figure 3. LH28F016SU Block Diagram (Architectural Evolution Includes Page Buffers,
Queue Registers and Extended Status Registers)
OUTPUT
BUFFER
OUTPUT
BUFFER
INPUT
BUFFER
INPUT
BUFFER
DQ8 - DQ
15
DQ0 - DQ
7
ID
REGISTER
OUTPUT
MULTIPLEXER
CSR
ESRs
DATA
COMPARATOR
DATA
QUEUE
REGISTERS
PAGE
BUFFERS
I/O
LOGIC
CUI
WSM
64KB BLOCK 0
64KB BLOCK 1
64KB BLOCK 30
64KB BLOCK 31
. . .
. . .
Y GATING/SENSING
Y-DECODER
X-DECODER
CE
0
CE
1
OE
WE
WP
RP
PROGRAM/
ERASE
VOLTAGE
SWITCH
3/5
BYTE
V
PP
3/5
V
CC
GND
RY/BY
ADDRESS
COUNTER
ADDRESS
QUEUE
LATCHES
INPUT
BUFFER
A0 - A
20
. . .
28F016SUT-2
LH28F016SU 16M (1M × 16, 2M × 8) Flash Memory
4
PIN DESCRIPTION
SYMBOL TYPE NAME AND FUNCTION
A
0
INPUT
BYTE-SELECT ADDRESS: Selects between high and low byte when device is in x8
mode. This address is latched in x8 Data Writes. Not used in x16 mode (i.e., the A
0
input buffer is turned off when BYTE is high).
A
1
- A
15
INPUT
WORD-SELECT ADDRESSES: Select a word within one 64K block. A
6
- A
15
selects
1 of 1024 rows, and A1 - A5 selects 16 of 512 columns. These addresses are
latched during Data Writes.
A
16
- A
20
INPUT
BLOCK-SELECT ADDRESSES: Select 1 of 32 Erase blocks. These addresses are
latched during Data Writes, Erase and Lock-Block operations.
DQ
0
- DQ7INPUT/OUTPUT
LOW-BYTE DATA BUS: Inputs data and commands during CUI write cycles.
Outputs array, buffer, identifier or status data in the appropriate Read mode. Floated
when the chip is de-selected or the outputs are disabled.
DQ
8
- DQ15INPUT/OUTPUT
HIGH-BYTE DATA BUS: Inputs data during x16 Data-Write operations. Outputs
array, buffer or identifier data in the appropriate Read mode; not used for Status
register reads. Floated when the chip is de-selected or the outputs are disabled.
CE
»
0
, CE
»
1
INPUT
CHIP ENABLE INPUTS: Activate the device’s control logic, input buffers, decoders and
sense amplifiers. With either CE
»
0
or CE
»
1
high, the device is de-selected and power
consumption reduces to Standby levels upon completion of any current Data-Write or
Erase operations. Both CE
»
0
, CE
»
1
must be low to select the device. All timing
specifications are the same for both signals. Device Selection
occ
urs with the latter
falling edge of CE
»
0
or CE
»
1
. The first rising edge of CE
»
0
or CE
»
1
disables the device.
RP
»
INPUT
RESET/POWER-DOWN: With RP
»
low, the device is reset, any current operation is
aborted and device is put into the deep power down mode. When the power is
turned on, RP
»
pin is turned to low in order to return the device to default con-
figuration. When the 3/5
»
pin is switched, or when the power transition is occurred, or
at the power on/off, RP
»
is required to stay low in order to pr otect data from noise.
When returning from Deep Power-Down, a recovery time of 400
ns
(V
CC
+5.0 V ±0.5 V) is required to allow these circuits to power-up. When RP
» goes
low, any current or pending WSM operation(s) are terminated, and the device is
reset. All Status registers return to ready (with all status flags cleared). After
returning, the device is in read array mode.
OE
» INPUT
OUTPUT ENABLE: Gates device data through the output buffers when low. The
outputs float to tri-state off when OE
» is high.
NOTE:
CE
»
X
overrides OE
»
, and OE
»
overrides WE.
WE INPUT
WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Queue Registers
and Address Queue Latches. WE is active low, and latches both address and data
(command or array) on its rising edge.
RY
»/BY
»
OPEN DRAIN
OUTPUT
READY/BUSY: Indicates status of the internal WSM. When low, it ind icates that the
WSM is busy performing an operation. RY/BY# high indicates that the WSM is ready
for new operations (or WSM has completed all pending operations), or Erase is
Suspended, or the device is in deep power-down mode. This output is always active
(i.e., not floated to tri-state off when OE
»
or CE
»
0
, CE
»
1
are high), except if a RY
»
/BY
»
Pin Disable command is issued.
16M (1M × 16, 2M × 8) Flash Memory LH28F016SU
5
PIN DESCRIPTION (Continued)
SYMBOL TYPE NAME AND FUNCTION
WP INPUT
WRITE PROTECT: Erase blocks can be locked by writing a non-volatile lock-bit for
each block. When WP is low, those locke d blocks as reflected by the B lock-Lock Status
bits (BSR.6), are protected from inadvertent Data Writes or Erases. When WP is high,
all blocks can be Written or Erased regardless of the state of the lock-bits. The WP
input buffer is disabled when RP
» transitions low (deep power-down mode).
BYTE INPUT
BYTE ENABLE: BYTE low places device x8 mode. All data is then input or output
on DQ
0
- DQ7, and DQ
8
- DQ15 float. Address A0 selects between the high and low
byte. BYTE high places the device in x16 mode, and turns off the A0 input buffer.
Address A1, then becomes the lowest order address.
3/5
» INPUT
3.3/5.0 V OLT SELECT: 3/5
» high configures internal circuit s for 3.3 V operation. 3/5
»
low configures internal circuits f or 5.0 V operation.
NOTES:
Reading the array with 3/5
» high in a 5.0 V system could damage the
device. There is a significant delay from 3/5
» switching to valid data.
V
PP
SUPPLY
ERASE/WRITE POWER SUPPLY: For erasing memory array blocks or writing
words/bytes/pages into the flash array.
V
CC
SUPPLY
DEVICE POWER SUPPLY (3.3 V ±0.3 V, 5.0 V ±0.5 V) (2.7 V ~ 3.6 V at Read
Operation)
: Do not leave any power pins floating.
GND SUPPLY
GROUND FOR ALL INTERNAL CIRCUITRY: Do not leave any ground pins floating.
NC
NO CONNECT: No internal connection to die, lead may be driven or left floating.
The LH28F016SU incorporates two Page Buffers of
256 Bytes (128 W ords) each to allow page data writes.
This feature can improve a system write performance
over pre vious flash memory devices.
All operations are started by a sequence of Wr ite
commands to the device. Three Status Registers
(described in detail later) and a RY»/BY» output pin
provide information on the progress of the requested
operation.
While the LH28F008SA requires an operation to complete before the next operation can be requested, the
LH28F016SU allows queuing of the next operation while
the memory executes the current operation. This eliminates system overhead when writing sev eral b ytes in a
row to the array or erasing several blocks at the same
time. The LH2F016SUR-10 can also perform write operations to one block of memory while performing erase
of another block.
The LH28F016SU provides user-selectable block
locking to protect code or data such as Device Driv ers,
PCMCIA card information, ROM-Executable O/S or
Application Code. Each block has an associated nonvolatile lock-bit which determines the lock status of the
block. In addition, the LH28F016SU has a master Write
Protect pin (WP
»
) which prevents any modifications to
memory blocks whose lock-bits are set.
A Command User Interface (CUI) serves as the system interface between the microprocessor or
microcontroller and the internal memory operation.
Internal Algorithm Automation allows Byte/Word
Writes and Block Erase operations to be executed
using a Two-Write command sequence to the CUI in
the same way as the LH28F008SA 8M Flash memory.
A Superset of commands have been added to the
basic LH28F008SA command-set to achieve higher
write performance and provide additional capabilities.
These new commands and features include:
• Page Buffer Writes to Flash
• Command Queuing Capability
• Automatic Data Writes During Erase
• Software Locking of Memory Blocks
• T w o-Byte Successive Writes in 8-bit Systems
• Erase All Unlocked Blocks
Writing of memory data is performed in either byte or
word increments typically within 8 µs, a 25% improvement over the LH28F008SA. A Block Erase operation
erases one of the 32 blocks in typically 0.7 seconds,
independent of the other blocks, which is about 55%
improvement ov er the LH28F008SA.
LH28F016SU 16M (1M × 16, 2M × 8) Flash Memory
6
OPERATING
TEMPERATURE
V
CC
SUPPLY
MAX. ACCESS
(T
ACC
)
0 - 70°C 4.75 - 5.25 V 70 ns
0 - 70°C 4.5 - 5.5 V 80 ns
0 - 70°C 3.0 - 3.6 V 120 ns
0 - 70°C 2.7 - 3.6 V 160 ns
The LH28F016SU contains three types of Status
Registers to accomplish various functions:
• A Compatible Status Register (CSR) which is 100%
compatible with the LH28F008SA Flash memory’s
Status Register. This register , when used alone, pro-
vides a straightforward upgrade capability to the
LH28F016SU from a LH28F008SA based design.
• A Global Status Register (GSR) which informs the
system of command Queue status, Page Buff er sta-
tus, and over all Write State Machine (WSM) status.
• 32 Block Status Registers (BSRs) which provide
block-specific status inf ormation such as the bloc k
lock-bit status.
The GSR and BSR memory maps for Byte-Wide and
Word-Wide modes are shown in Figures 5 and 6.
The LH28F016SU incorporates an open drain
RY»/BY» output pin. This feature allows the user to ORtie many RY »/BY» pins together in a multiple memory configuration such as a Resident Flash Array.
The LH28F016SU also incorporates a dual chipenable function with two input pins, CE »0 and CE»1. These
pins have exactly the same functionality as the regular
chip-enable pin CE» on the LH28F008SA. F or minimum
chip designs, CE»1 may be tied to ground and use CE»
0
as the chip enable input. The LH28F016SU uses the
logical combination of these two signals to enable or
disable the entire chip. Both CE»0 and CE»1 must be active low to enable the de vice and if either one becomes
inactive, the chip will be disabled. This feature, along
with the open drain RY »/BY» pin, allows the 0system designer to reduce the number of control pins used in a
large array of 16M de vices .
The BY»TE» pin allo ws either x8 or x16 read/writes to
the LH28F016SU. BY»TE» at logic low selects 8-bit mode
with address A0 selecting between low byte and high
byte. On the other hand, BY»TE» at logic high enables
16-bit operation with address A1 becoming the lowest
order address and address A0 is not used (don’t care).
A block diagram is shown in Figure 3.
The LH28F016SU is specified for a maximum
access time of each version, as follows:
The LH28F016SU incorporates an Automatic Pow er
Saving (APS) feature which substantially reduces the
active current when the device is in static mode of
operation (addresses not switching).
In APS mode, the typical I
CC
current is 2 mA at 5.0 V
(1 mA at 3.3 V).
A Deep Power-Down mode of operation is invoked
when the RP» (called PWD on the LH28F008SA) pin
transitions low , any current operation is aborted and the
device is put into the deep power-do wn mode. This mode
brings the device power consumption to less than 5 µA
typically, and provides additional write protection by
acting as a device reset pin during power transitions.
When the power is turned on, RP» pin turned to low order to return the device to default configuration. When
the 3/5» pin is switched, or when the pow er transition is
occured, or at the power on/off, RP» is required to stay
low in order to protect data from noise. A recov ery time
of 550 ns (V
CC
= 5.0 V ± 0.5 V ) is required from RP»
switching high until outputs are again valid. In the Deep
Power-Down state, the WSM is reset (any current
operation will abort) and the CSR, GSR and BSR registers are cleared.
A CMOS Standby mode of operation is enabled when
either CE»0 or CE»1 transitions high and RP» stays high
with all input control pins at CMOS levels . In this mode ,
the device typically draws an I
CC
standby current of
10 µA.
16M (1M × 16, 2M × 8) Flash Memory LH28F016SU
7
Figure 4. LH28F016SU Memory Map
(Byte-Wide Mode)
MEMORY MAP
Figure 5. Extended Status Register
Memory Map (Byte-Wide Mode)
Figure 6. Extended Status Register
Memory Map (Word-Wide Mode)
Extended Status Registers Memory Map
RESERVED
GSR
RESERVED
BSR31
RESERVED
RESERVED
F8003H
F8002H
F8001H
F8000H
A[20:1] (NOTE)
x16 MODE
.
.
.
RESERVED
GSR
RESERVED
BSR0
RESERVED
RESERVED
00003H
00002H
00001H
00000H
RESERVED
08001H
28F016SUT-5
NOTE: In word-wide mode A0 don't care, address values
are ignored A0.
15
1F0000H
1FFFFFH
1EFFFFH
1E0000H
1DFFFFH
1D0000H
1CFFFFH
1C0000H
1BFFFFH
1B0000H
1AFFFFH
1A0000H
19FFFFH
190000H
18FFFFH
180000H
17FFFFH
170000H
16FFFFH
160000H
15FFFFH
150000H
14FFFFH
140000H
13FFFFH
130000H
12FFFFH
120000H
11FFFFH
110000H
10FFFFH
100000H
0FFFFFH
0F0000H
0EFFFFH
0E0000H
0DFFFFH
0D0000H
0CFFFFH
0C0000H
0BFFFFH
0B0000H
0AFFFFH
0A0000H
09FFFFH
090000H
08FFFFH
080000H
07FFFFH
070000H
06FFFFH
060000H
05FFFFH
050000H
04FFFFH
040000H
03FFFFH
030000H
02FFFFH
020000H
01FFFFH
010000H
00FFFFH
000000H
14
13
12
11
10
9
8
7
6
5
4
3
2
0
64KB BLOCK
16 64KB BLOCK
17 64KB BLOCK
18 64KB BLOCK
19 64KB BLOCK
20 64KB BLOCK
21 64KB BLOCK
22 64KB BLOCK
23 64KB BLOCK
24 64KB BLOCK
25 64KB BLOCK
26 64KB BLOCK
27 64KB BLOCK
28 64KB BLOCK
29 64KB BLOCK
30
64KB BLOCK
31 64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
1
64KB BLOCK
64KB BLOCK
28F016SUT-3
RESERVED
GSR
RESERVED
BSR31
RESERVED
RESERVED
1F0006H
1F0005H
1F0004H
1F0003H
1F0002H
1F0001H
1F0000H
A[20:0]
x8 MODE
.
.
.
RESERVED
GSR
RESERVED
BSR0
RESERVED
RESERVED
000006H
000005H
000004H
000003H
000002H
000001H
000000H
RESERVED
010002H
28F016SUT-4
LH28F016SU 16M (1M × 16, 2M × 8) Flash Memory
8
BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS
Bus Operations for Word-Wide Mode (BY»TE» = VIH)
MODE RP
» CE »
1
CE
»
0
OE
» WE A
1
DQ0 - DQ
15
RY
»/BY » NOTE
Read V
IH
V
IL
V
IL
V
IL
V
IH
XD
OUT
X1, 2, 7
Output Disable V
IH
V
IL
V
IL
V
IH
V
IH
X High-Z X 1, 6, 7
Standby V
IH
V
IL
V
IH
V
IH
V
IH
V
IL
V
IH
X X X High-Z X 1, 6, 7
Deep Powe r-Down V
IL
XXXXX High-Z VOH1, 3
Manufacturer ID V
IH
V
IL
V
IL
V
IL
V
IH
V
IL
00B0H V
OH
4
Device ID V
IH
V
IL
V
IL
V
IL
V
IH
V
IH
6688H V
OH
4
Writ e V
IH
V
IL
V
IL
V
IH
V
IL
XDINX1, 5, 6
NOTES:
1. X can be VIH or VIL for address or control pins except for RY»/BY», which is either VOL or VOH.
2. RY»/BY» output is open drain. When the WSM is ready, Erase is suspended or the device is in deep power-down mode,
RY»/BY» will be at VOH if it is tied to VCC through a resistor. When the RY»/BY» at VOH is independent of OE
»
while a WSM
operation is in progress.
3. RP» at GND ± 0.2 V ensures the lowest deep power-down current.
4. A0 and A1 at VIL provide manufacturer ID codes in x8 and x16 modes respectively. A0 and A1, at VIH provide device ID
codes in x8 and x16 modes respectively. All other addresses are set to zero.
5. Commands for different Erase operations, Data Write operations of Lock-Block operations can only be successfully
completed when VPP = V
PPH
.
6. While the WSM is running, RY»/BY» in Level-Mode (default) stays at VOL until all operations are complete. RY»/BY» goes to
VOH when the WSM is not busy or in erase suspend mode.
7. RY»/BY» may be at VOL while the WSM is busy performing various operations. For example, a status register read during a
write operations.
Bus Operations For Byte-Wide Mode (BY»TE» = VIL)
MODE RP
» CE »
1
CE
»
0
OE
» WE A
0
DQ0 - DQ
7
RY
»/BY » NOTE
Read V
IH
V
IL
V
IL
V
IL
V
IH
XD
OUT
X1, 2, 7
Output Disable V
IH
V
IL
V
IL
V
IH
V
IH
X High-Z X 1, 6, 7
Standby V
IH
V
IL
V
IH
V
IH
V
IH
V
IL
V
IH
X X X High-Z X 1, 6, 7
Deep Powe r-Down V
IL
XXXXX High-Z VOH1, 3
Manufacturer ID V
IH
V
IL
V
IL
V
IL
V
IH
V
IL
B0H V
OH
4
Device ID V
IH
V
IL
V
IL
V
IL
V
IH
V
IH
88H V
OH
4
Writ e V
IH
V
IL
V
IL
V
IH
V
IL
XDINX1, 5, 6
16M (1M × 16, 2M × 8) Flash Memory LH28F016SU
9
COMMAND
FIRST BUS CYCLE SECOND BUS CYCLE
NOTE
OPER. ADDRESS DATA OPER. ADDRESS DATA
Read Array Write X FFH Read AA AD
Intelligent Identifier Write X 90H Read IA ID 1
Read Compatible Status Register Write X 70H Read X CSRD 2
Clear Status Register Write X 50H 3
Word Write Write X 4 0H Wr ite WA WD
Alternate Word/Byte Write Write X 10H Write WA WD
Block Erase/Confirm Write X 20H Write BA D0H
Erase Suspend/Resume Write X B0H Write X D0H
ADDRESS DATA
AA = Array Address AD = Array Data
BA = Block Address CSRD = CSR Data
IA = Identifier Address ID = Identifier Data
WA = Write Address WD = Write Data
X = Don’t Care
NOTES:
1. Following the intelligent identifier command, two Read operations access the manufacturer and device signature codes.
2. The CSR is automatically available after device enters Data Write, Erase or Suspend operations.
3. Clears CSR.3, CSR.4, and CSR.5. Also clears GSR.5 an all BSR.5 and BSR.2 bits. See Status register definitions.
LH28F008SA-Compatible Mode Command Bus Definitions
LH28F016SU 16M (1M × 16, 2M × 8) Flash Memory
10
LH28F016SU Performance Enhancement Command Bus Definitions
COMMAND MODE
FIRST BUS CYCLE SECOND BUS CYCLE THIRD BUS CYCLE
NOTE
OPER. ADDR. DAT A OPE R. ADDR. DAT A OPE R. ADDR. DATA
Read Extended
Status Register
Write X 71H Read RA
GSRD
BSRD
1
Page Buffer Swap Write X 72H 7
Read Page Buffer Write X 75H Read PA PD
Single Load to
Page Buffer
Writ e X 74H Wri te PA PD
Sequential Load to
Page Buffer
x8 Wr ite X E0 H Writ e X BCL Writ e X BCH 4 , 6, 1 0
x16 Writ e X E 0H Wri te X WCL Write X WCH
4, 5,
6, 10
Page Buffer Write
to Flash
x8 Write X 0CH Write A0
BC
(L, H)
Write WA BC (H, L)
3, 4,
9, 10
x16 Writ e X 0 CH Writ e X WCL Write WA WCH 4, 5, 10
Two-Byte Wri te x8 Write X FBH Write A0
WD
(L, H)
Write WA WD (H , L) 3
Block
Erase/Confirm
Write X 20H Write BA D0H
Lock Block/Confirm Write X 77H Write BA D0H
Upload Status
Bits/Confirm
Writ e X 9 7 H Wr i te X D0H 2
Uploa d Devic e
Information
Writ e X 9 9H Wr i te X D0 H
Erase All Unlocked
Blocks/Confirm
Writ e X A7H Wr i t e X D0 H
RY
»/BY » Enable to
Level-Mode
Write X 96H Write X 01H 8
RY
»/BY » Pulse-On-
Writ e
Write X 96H Write X 02H 8
RY
»
/BY
»
Pulse-On-
Erase
Write X 96H Write X 03H 8
RY
»/BY » Disable Write X 96H Write X 04H 8
Sleep Write X F0H
Abort Write X 80H
ADDRESS DATA
BA = Block Address AD = Array Data
PA = Page Buffer Address PD = Page Buffer Data
RA = Extended Register Address BSRD = BSR Data
WA = Write Address GSRD = GSR Data
X = Don’t Care WC (L, H) = Word Count (Low, High)
BC (L, H) = Byte Count (Low, High)
WD (L, H) = Write Data (Low, High)
16M (1M × 16, 2M × 8) Flash Memory LH28F016SU
11
NOTES:
1. RA can be the GSR address or any BSR address. See Figure 5 and 6 for Extended Status Register Memory Maps.
2. Upon device power-up, all BSR lock-bits come up locked. The Uploaded Status Bits command must be written to reflect the
actual lock-bit status.
3. A0 is automatically complemented to load second byte of data. BY» TE» must be at VIL. A0 value determines which WD/BC is supplied
first: A0 = 0 looks at the WDL/BCL, A0 = 1 looks at the WDH/BCH.
4. BCH/WCH must be at 00H for this product because of the 256-Byte (128 Word) Page Buffer size and to avoid writing the Page Buffer
contents into more than one 256-Byte segment within an array block. They are simply shown for future Page Buffer expandability.
5. In x16 mode, only the lower byte DQ0 - DQ7 is used for WCL and WCH. The upper byte DQ8 - DQ15 is a don’t care.
6. PA and PD (Whose count is given in cycles 2 and 3) are supplied starting in the 4th cycle which is not shown.
7. This command allows the user to swap between available Page Buffers (0 or 1).
8. These commands reconfigure RY»/BY» output to one of two pulse-modes or enable and disable the RY »/BY» function.
9. Write address, WA, is the Destination address in the flash array which must match the Source address in the Page Buffer. Refer to the
LH28F016SU User’s Manual.
10. BCL = 00H corresponds to a Byte count of 1. Similarly, WCL = 00H corresponds to a Word count of 1.
WSMS ESS ES DWS VPPS R R R
76543210
CSR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
CSR.6 = ERASE-SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase in Progress/Completed
CSR.5 = ERASE STATUS (ES)
1 = Error in Block Erasure
0 = Successful Block Erase
CSR.4 = DATA-WRITE STATUS (DWS)
1 = Error in Data Write
0 = Data Write Successful
CSR.3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
NOTES:
1. RY»/BY» output or WSMS bit must be checked to determine
completion of an operation (Erase Suspend, Erase or Data
Write) before the appropriate Status bit (ESS, ES or DWS)
is checked for success.
2. If DWS and ES are set to ‘1’ during an erase attempt, an
improper command sequence was entered. Clear the CSR
and attempt the operation again.
3. The VPPS bit, unlike an A/D converter, does not provide
continuous indication of VPP level. The WSM interrogates
VPP’s level only after the Data-Write or Erase command
sequences have been entered, and informs the system if
VPP has not been switched on. VPPS is not guaranteed to
report accurate feedback between V
PPL
and V
PPH
.
4. CSR.2 - CSR.0 = Reserved for future enhancements.
These bits are reserved for future use and should be
masked out when polling the CSR.
Compatible Status Register
LH28F016SU 16M (1M × 16, 2M × 8) Flash Memory
12
WSMS OSS DOS DSS QS PBAS PBS PBSS
76543210
GSR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
GSR.6 = OPERATION SUSPEND STATUS (OSS)
1 = Operation Suspended
0 = Operation in Progress/Completed
GSR.5 = DEVICE OPERATION STATUS (DOS)
1 = Operation Unsuccessful
0 = Operation Successful or Currently Running
GSR.4 = DEVICE SLEEP STATUS(DSS)
1 = Device in Sleep
0 = Device Not in Sleep
MATRIX 5/4
00 = Operation Successful or currently Running
01 = Device in Sleep Mode or Pending Sleep
10 = Operation Unsuccesful
11 = Operation Unsuccessful or Aborted
GSR.3 = QUEUE STATUS (QS)
1 = Queue Full
0 = Queue Available
GSR.2 = PAGE BUFFER AVAILABLE STATUS (PBAS)
1 = One or Two Page Buffers Available
0 = No Page Buffer Available
GSR.1 = PAGE BUFFER STATUS (PBS)
1 = Selected Page Buffer Ready
0 = Selected Page Buffer Busy
GSR.0 = PAGE BUFFER SELECT STATUS (PBSS)
1 = Page Buffer 1 Selected
0 = Page buffer 0 Selected
NOTES:
1. RY»/BY» output or WSMS bit must be checked to determine
completion of an operation (Block Lock, Suspend, any
RY»/BY» reconfiguration, Upload Status Bits, Erase or Data
Write) before the appropriate Status bit (OSS or DOS) is
checked for success.
2. If operation currently running, then GSR.7 = 0.
3. If device pending sleep, then GSR.7 = 0.
4. Operation aborted: Unsucccessful due to Abort command.
5. The device contains two Page Buffers.
6. Selected Page Buffer is currently busy with WSM operation.
7. When multiple operations are queued, checking BSR.7
only provides indication of completion for that particular
block. GSR.7 provides indication when all queuedf operations are completed.
GLOBAL STATUS REGISTER
Loading...