Sharp LH28F016SCR-L12, LH28F016SCN-L95, LH28F016SCN-L12, LH28F016SCT-L12, LH28F016SCB-L12 Datasheet

- 1 -

In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books,
etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.

DESCRIPTION

The LH28F016SC-L/SCH-L flash memories with
SmartVoltage technology are high-density, low-cost,
nonvolatile, read/write storage solution for a wide
range of applications. Their symmetrically-blocked
architecture, flexible voltage and enhanced cycling
capability provide for highly flexible component
suitable for resident flash arrays, SIMMs and
memory cards. Their enhanced suspend
capabilities provide for an ideal solution for code +
data storage applications. For secure code storage
applications, such as networking, where code is
either directly executed out of flash or downloaded
to DRAM, the LH28F016SC-L/SCH-L offer three
levels of protection : absolute protection with Vpp at
GND, selective hardware block locking, or flexible
software block locking. These alternatives give
designers ultimate control of their code security
needs.

FEATURES

• SmartVoltage technology
– 2.7 V (Read-only), 3.3 V or 5 V V

CC

– 3.3 V, 5 V or 12 V VPP

• High performance read access time
LH28F016SC-L95/SCH-L95
– 95 ns (5.0±0.25 V)/100 ns (5.0±0.5 V)/

120 ns (3.3±0.3 V)/150 ns (2.7 to 3.6 V)
LH28F016SC-L12/SCH-L12
– 120 ns (5.0±0.5 V)/150 ns (3.3±0.3 V)/

170 ns (2.7 to 3.6 V)

• Enhanced automated suspend options
– Byte write suspend to read
– Block erase suspend to byte write
– Block erase suspend to read

• Enhanced data protection features
– Absolute protection with V

PP = GND

– Flexible block locking
– Block erase/byte write lockout during power

transitions

• SRAM-compatible write interface

• High-density symmetrically-blocked architecture
– Thirty-two 64 k-byte erasable blocks

• Enhanced cycling capability
– 100 000 block erase cycles
– 3.2 million block erase cycles/chip

• Low power management
– Deep power-down mode
– Automatic power saving mode decreases I

CC

in static mode

• Automated byte write and block erase
– Command user interface
– Status register

• ETOX

TM

∗

V nonvolatile flash technology

• Packages
– 40-pin TSOP Type I (TSOP040-P-1020)

Normal bend/Reverse bend

– 44-pin SOP (SOP044-P-0600)

[LH28F016SC-L]

– 48-ball CSP (FBGA048-P-0810)

∗

ETOX is a trademark of Intel Corporation.

LH28F016SC-L/SCH-L

16 M-bit (2 MB x 8) SmartVoltage

Flash Memories

LH28F016SC-L/SCH-L

COMPARISON TABLE

VERSIONS

OPERATING

DC CHARACTERISTICS

PACKAGE

TEMPERATURE

VCCdeep power-down current (MAX.)

LH28F016SC-L 0 to +70˚C 10 µA

40-pin TSOP (I), 44-pin SOP,
48-ball CSP

LH28F016SCH-L –40 to +85˚C 20

µA 40-pin TSOP (I), 48-ball CSP

LH28F016SC-L/SCH-L

- 2 -

PIN CONNECTIONS

44-PIN SOP [LH28F016SC-L]

(SOP044-P-0600)

VPP

RP#

A

11

A10

A9
A8
A7
A6
A5

A4
NC
NC

A

3

A2

A1

A0

DQ0
DQ1
DQ2

DQ3
GND
GND

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

VCC
CE#
A

12

A13
A14
A15
A16
A17
A18
A19
NC
NC
A

20

NC
WE#
OE#
RY/BY#
DQ

7

DQ6
DQ5
DQ4
VCC

40-PIN TSOP (Type I)

(TSOP040-P-1020)

A19
A18
A17
A16
A15
A14
A13
A12

CE#

V

CC

VPP

RP#

A

11

A10

A9
A8
A7
A6
A5
A4

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

A20
NC
WE#
OE#
RY/BY#
DQ

7

DQ6
DQ5
DQ4
VCC
GND
GND
DQ

3

DQ2
DQ1
DQ0
A0
A1
A2
A3

A5

H

1

A

6 2

A

4 3

A

3 4

A

1 5

A

2

A8

G

A

9

A7

A0

DQ1

DQ0

A11

VPP VCC

F

A10

DQ2

GND

DQ3

E

NC

NC

NC

GND

D

NC

NC

NC

NC

VCC

A12

C

CE#

A13

DQ6

DQ4

DQ5

A15

B

A14

A16

RY/BY#

DQ7

NC

A

18

A

A

17

A19

A20

OE#

WE#

6

NC

RP#

(FBGA048-P-0810)

48-BALL CSP

A

1

TOP VIEW

NOTE :

Reverse bend available on request.

LH28F016SC-L/SCH-L

- 3 -

BLOCK DIAGRAM

Y GATING

Y DECODER

INPUT

BUFFER

OUTPUT
BUFFER

DQ0-DQ7

VCC

CE#
WE#
OE#
RP#

ADDRESS

LATCH

DATA

COMPARATOR

PROGRAM/ERASE
VOLTAGE SWITCH

STATUS

REGISTER

COMMAND

USER

INTERFACE

WRITE
STATE

MACHINE

DATA

REGISTER

OUTPUT

MULTIPLEXER

IDENTIFIER

REGISTER

ADDRESS
COUNTER

A0-A20

X DECODER

32

64 k-BYTE

BLOCKS

RY/BY#

VCC
GND

V

PP

INPUT

BUFFER

I/O

LOGIC

LH28F016SC-L/SCH-L

- 4 -

PIN DESCRIPTION

SYMBOL TYPE NAME AND FUNCTION

A

0-A20 INPUT

ADDRESS INPUTS : Inputs for addresses during read and write operations. Addresses
are internally latched during a write cycle.

INPUT/

DATA INPUT/OUTPUTS : Inputs data and commands during CUI write cycles; outputs
data during memory array, status register, and identifier code read cycles. Data pins
float to high-impedance when the chip is deselected or outputs are disabled. Data is
internally latched during a write cycle.

CE# INPUT

CHIP ENABLE : Activates the device's control logic, input buffers, decoders, and sense
amplifiers. CE#-high deselects the device and reduces power consumption to standby
levels.
RESET/DEEP POWER-DOWN : Puts the device in deep power-down mode and resets
internal automation. RP#-high enables normal operation. When driven low, RP# inhibits
write operations which provide data protection during power transitions. Exit from deep
power-down sets the device to read array mode. RP# at V

HH enables setting of the

master lock-bit and enables configuration of block lock-bits when the master lock-bit is
set. RP# = V

HH overrides block lock-bits thereby enabling block erase and byte write

operations to locked memory blocks. Block erase, byte write, or lock-bit configuration
with VIH < RP# < VHH produce spurious results and should not be attempted.

OE# INPUT OUTPUT ENABLE : Gates the device's outputs during a read cycle.
WE# INPUT

WRITE ENABLE : Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE# pulse.
READY/BUSY : Indicates the status of the internal WSM. When low, the WSM is
performing an internal operation (block erase, byte write, or lock-bit configuration).
RY/BY#-high indicates that the WSM is ready for new commands, block erase is
suspended, and byte write is inactive, byte write is suspended, or the device is in deep
power-down mode. RY/BY# is always active and does not float when the chip is
deselected or data outputs are disabled.
BLOCK ERASE, BYTE WRITE, LOCK-BIT CONFIGURATION POWER SUPPLY : For
erasing array blocks, writing bytes, or configuring lock-bits. With V

PP ≤ VPPLK, memory

contents cannot be altered. Block erase, byte write, and lock-bit configuration with an
invalid V

PP (see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results

and should not be attempted.
DEVICE POWER SUPPLY : Internal detection configures the device for 2.7 V , 3.3 V or
5 V operation. To switch from one voltage to another, ramp V

CC down to GND and then

ramp VCC to the new voltage. Do not float any power pins. With VCC ≤ VLKO, all write
attempts to the flash memory are inhibited. Device operations at invalid V

CC voltage

(see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results and should
not be attempted. Block erase, byte write and lock-bit configuration operations with V

CC

<

3.0 V are not supported.

GND SUPPLY GROUND : Do not float any ground pins.

NC NO CONNECT : Lead is not internal connected; recommend to be floated.

OUTPUT

DQ

0-DQ7

RP#

INPUT

RY/BY# OUTPUT

V

PP SUPPLY

V

CC SUPPLY

LH28F016SC-L/SCH-L

1 INTRODUCTION

This datasheet contains LH28F016SC-L/SCH-L
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4, and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications. LH28F016SC-L/
SCH-L flash memories documentation also includes
ordering information which is referenced in
Section 7.

1.1 New Features

The LH28F016SC-L/SCH-L SmartVoltage flash
memories maintain backwards-compatibility with the
LH28F008SA. Key enhancements over the
LH28F008SA include :

• SmartVoltage Technology

• Enhanced Suspend Capabilities

• In-System Block Locking

Both devices share a compatible pinout, status
register, and software command set. These
similarities enable a clean upgrade from the
LH28F008SA to LH28F016SC-L/SCH-L. When
upgrading, it is important to note the following
differences :

• Because of new feature support, the two
devices have different device codes. This allows
for software optimization.

•V

PPLK has been lowered from 6.5 V to 1.5 V to

support 3.3 V and 5 V block erase, byte write,
and lock-bit configuration operations. Designs
that switch V

PP off during read operations

should make sure that the V

PP voltage

transitions to GND.

• To take advantage of SmartVoltage technology,
allow V

PP connection to 3.3 V or 5 V.

1.2 Product Overview

The LH28F016SC-L/SCH-L are high-performance
16 M-bit SmartVoltage flash memories organized
as 2 M-byte of 8 bits. The 2 M-byte of data is

arranged in thirty-two 64 k-byte blocks which are
individually erasable, lockable, and unlockable in­system. The memory map is shown in Fig. 1.

SmartVoltage technology provides a choice of V

CC

and VPP combinations, as shown in Table 1, to
meet system performance and power expectations.

2.7 V V

CC consumes approximately one-fifth the

power of 5 V V

CC and 3.3 V VCC consumes

approximately one-fourth the power of 5 V V

CC. But,

5 V V

CC provides the highest read performance.

V

PP at 3.3 V and 5 V eliminates the need for a

separate 12 V converter, while V

PP = 12 V

maximizes block erase and byte write performance.
In addition to flexible erase and program voltages,
the dedicated V

PP pin gives complete data

protection when V

PP ≤ VPPLK.

Table 1 VCC and VPP Voltage Combinations

Offered by SmartVoltage Technology

NOTE :

1. Block erase, byte write and lock-bit configuration
operations with V

CC < 3.0 V are not supported.

Internal VCC and VPP detection circuitry auto­matically configures the device for optimized read
and write operations.

A Command User Interface (CUI) serves as the
interface between the system processor and
internal operation of the device. A valid command
sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM)
automatically executes the algorithms and timings
necessary for block erase, byte write, and lock-bit
configuration operations.

A block erase operation erases one of the device’s
64 k-byte blocks typically within 1 second (5 V V

CC,

VCC VOLTAGE VPP VOLTAGE

2.7 V

(NOTE 1)

—

3.3 V 3.3 V, 5 V, 12 V
5 V 5 V, 12 V

- 5 -

- 6 -

LH28F016SC-L/SCH-L

12 V VPP) independent of other blocks. Each block
can be independently erased 100 000 times (3.2
million block erases per device). Block erase
suspend mode allows system software to suspend
block erase to read data from, or write data to any
other block.

Writing memory data is performed in byte
increments typically within 6 µs (5 V V

CC, 12 V

V

PP). Byte write suspend mode enables the system

to read data from, or write data to any other flash
memory array location.

Individual block locking uses a combination of bits,
thirty-two block lock-bits and a master lock-bit, to
lock and unlock blocks. Block lock-bits gate block
erase and byte write operations, while the master
lock-bit gates block lock-bit modification. Lock-bit
configuration operations (Set Block Lock-Bit, Set
Master Lock-Bit, and Clear Block Lock-Bits
commands) set and cleared lock-bits.

The status register indicates when the WSM’s block
erase, byte write, or lock-bit configuration operation
is finished.

The RY/BY# output gives an additional indicator of
WSM activity by providing both a hardware signal
of status (versus software polling) and status
masking (interrupt masking for background block
erase, for example). Status polling using RY/BY#
minimizes both CPU overhead and system power
consumption. When low, RY/BY# indicates that the
WSM is performing a block erase, byte write, or
lock-bit configuration. RY/BY#-high indicates that
the WSM is ready for a new command, block erase
is suspended (and byte write is inactive), byte write
is suspended, or the device is in deep power-down
mode.

The access time is 95 ns (t

AVQV) at the VCC supply

voltage range of 4.75 to 5.25 V over the
temperature range, 0 to +70°C (LH28F016SC-L)/
–40 to +85°C (LH28F016SCH-L). At 4.5 to 5.5 V
V

CC, the access time is 100 ns or 120 ns. At lower

V

CC voltage, the access time is 120 ns or 150 ns

(3.0 to 3.6 V) and 150 ns or 170 ns (2.7 to 3.6 V).

The Automatic Power Saving (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
In APS mode, the typical I

CCR current is 1 mA at

5 V V

CC and 3 mA at 2.7 V and 3.3 V VCC.

When CE# and RP# pins are at V

CC, the ICC

CMOS standby mode is enabled. When the RP#
pin is at GND, deep power-down mode is enabled
which minimizes power consumption and provides
write protection during reset. A reset time (t

PHQV) is

required from RP# switching high until outputs are
valid. Likewise, the device has a wake time (t

PHEL)

from RP#-high until writes to the CUI are
recognized. With RP# at GND, the WSM is reset
and the status register is cleared.

- 7 -

LH28F016SC-L/SCH-L

Fig. 1 Memory Map

2 PRINCIPLES OF OPERATION

The LH28F016SC-L/SCH-L SmartVoltage flash
memories include an on-chip WSM to manage
block erase, byte write, and lock-bit configuration
functions. It allows for : 100% TTL-level control
inputs, fixed power supplies during block erasure,
byte write, and lock-bit configuration, and minimal
processor overhead with RAM-like interface timings.

After initial device power-up or return from deep
power-down mode (see Table 2 "Bus Operations"),
the device defaults to read array mode. Manipulation
of external memory control pins allow array read,
standby, and output disable operations.

Status register and identifier codes can be
accessed through the CUI independent of the V

PP

voltage. High voltage on VPP enables successful
block erasure, byte writing, and lock-bit
configuration. All functions associated with altering
memory contents—block erase, byte write, lock-bit
configuration, status, and identifier codes—are
accessed via the CUI and verified through the
status register.

Commands are written using standard micro­processor write timings. The CUI contents serve as
input to the WSM, which controls the block erase,
byte write, and lock-bit configuration. The internal
algorithms are regulated by the WSM, including
pulse repetition, internal verification, and margining
of data. Addresses and data are internally latched
during write cycles. Writing the appropriate
command outputs array data, accesses the
identifier codes, or outputs status register data.

Interface software that initiates and polls progress
of block erase, byte write, and lock-bit configuration
can be stored in any block. This code is copied to
and executed from system RAM during flash
memory updates. After successful completion,
reads are again possible via the Read Array
command. Block erase suspend allows system

64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block

1FFFFF
1F0000

1EFFFF
1E0000

1DFFFF
1D0000

1CFFFF
1C0000

1BFFFF
1B0000

1AFFFF
1A0000

19FFFF
190000

18FFFF
180000

17FFFF
170000

16FFFF
160000

15FFFF
150000

14FFFF
140000

13FFFF
130000

12FFFF
120000

11FFFF
110000

10FFFF
100000

0FFFFF
0F0000

0EFFFF
0E0000

0DFFFF
0D0000

0CFFFF
0C0000

0BFFFF
0B0000

0AFFFF
0A0000

09FFFF
090000

08FFFF
080000

07FFFF
070000

06FFFF
060000

05FFFF
050000

04FFFF
040000

03FFFF
030000

02FFFF
020000

01FFFF
010000

00FFFF
000000

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1
0

- 8 -

LH28F016SC-L/SCH-L

software to suspend a block erase to read/write
data from/to blocks other than that which is
suspended. Byte write suspend allows system
software to suspend a byte write to read data from
any other flash memory array location.

2.1 Data Protection

Depending on the application, the system designer
may choose to make the V

PP power supply

switchable (available only when memory block
erases, byte writes, or lock-bit configurations are
required) or hardwired to V

PPH1/2/3. The device

accommodates either design practice and
encourages optimization of the processor-memory
interface.

When V

PP ≤ VPPLK, memory contents cannot be

altered. The CUI, with two-step block erase, byte
write, or lock-bit configuration command sequences,
provides protection from unwanted operations even
when high voltage is applied to V

PP. All write

functions are disabled when V

CC is below the write

lockout voltage V

LKO or when RP# is at VIL. The

device’s block locking capability provides additional
protection from inadvertent code or data alteration
by gating erase and byte write operations.

3 BUS OPERATION

The local CPU reads and writes flash memory in­system. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.

3.1 Read

Information can be read from any block, identifier
codes, or status register independent of the V

PP

voltage. RP# can be at either VIH or VHH.

The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes, or
Read Status Register) to the CUI. Upon initial
device power-up or after exit from deep power­down mode, the device automatically resets to read
array mode. Four control pins dictate the data flow

in and out of the component : CE#, OE#, WE#,
and RP#. CE# and OE# must be driven active to
obtain data at the outputs. CE# is the device
selection control, and when active enables the
selected memory device. OE# is the data output
(DQ

0-DQ7) control and when active drives the

selected memory data onto the I/O bus. WE# must
be at V

IH and RP# must be at VIH or VHH. Fig. 13

illustrates a read cycle.

3.2 Output Disable

With OE# at a logic-high level (VIH), the device
outputs are disabled. Output pins DQ

0-DQ7 are

placed in a high-impedance state.

3.3 Standby

CE# at a logic-high level (VIH) places the device in
standby mode which substantially reduces device
power consumption. DQ

0-DQ7 outputs are placed

in a high-impedance state independent of OE#. If
deselected during block erase, byte write, or lock-bit
configuration, the device continues functioning, and
consuming active power until the operation
completes.

3.4 Deep Power-Down

RP# at VIL initiates the deep power-down mode.

In read modes, RP#-low deselects the memory,
places output drivers in a high-impedance state and
turns off all internal circuits. RP# must be held low
for a minimum of 100 ns. Time t

PHQV is required

after return from power-down until initial memory
access outputs are valid. After this wake-up
interval, normal operation is restored. The CUI is
reset to read array mode and status register is set
to 80H.

During block erase, byte write, or lock-bit
configuration modes, RP#-low will abort the
operation. RY/BY# remains low until the reset
operation is complete. Memory contents being
altered are no longer valid; the data may be

- 9 -

LH28F016SC-L/SCH-L

partially erased or written. Time tPHWL is required
after RP# goes to logic-high (V

IH) before another

command can be written.

As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash
memory. Automated flash memories provide status
information when accessed during block erase, byte
write, or lock-bit configuration modes. If a CPU
reset occurs with no flash memory reset, proper
CPU initialization may not occur because the flash
memory may be providing status information
instead of array data. SHARP’s flash memories
allow proper CPU initialization following a system
reset through the use of the RP# input. In this
application, RP# is controlled by the same RESET#
signal that resets the system CPU.

3.5 Read Identifier Codes Operation

The read identifier codes operation outputs the
manufacture code, device code, block lock
configuration codes for each block, and the master
lock configuration code (see Fig. 2). Using the
manufacture and device codes, the system CPU
can automatically match the device with its proper
algorithms. The block lock and master lock
configuration codes identify locked and unlocked
blocks and master lock-bit setting.

Fig. 2 Device Identifier Code Memory Map

1FFFFF

1F0004
1F0003
1F0002
1F0001
1F0000

01FFFF

010004
010003
010002
010001
010000
00FFFF

000004
000003
000002
000001
000000

Reserved for

Future Implementation

Block 31 Lock Configuration Code

Block 31

Block 1

Block 0

(Blocks 2 through 30)

Reserved for

Future Implementation

Reserved for

Future Implementation

Block 1 Lock Configuration Code

Reserved for

Future Implementation

Reserved for

Future Implementation

Master Lock Configuration Code

Block 0 Lock Configuration Code

Device Code

Manufacture Code

LH28F016SC-L/SCH-L

3.6 Write

Writing commands to the CUI enable reading of
device data and identifier codes. They also control
inspection and clearing of the status register. When
V

PP = VPPH1/2/3, the CUI additionally controls

block erasure, byte write, and lock-bit configuration.

The Block Erase command requires appropriate
command data and an address within the block to
be erased. The Byte Write command requires the
command and address of the location to be written.
Set Master and Block Lock-Bit commands require
the command and address within the device
(Master Lock) or block within the device (Block
Lock) to be locked. The Clear Block Lock-Bits
command requires the command and address
within the device.

The CUI does not occupy an addressable memory

location. It is written when WE# and CE# are
active. The address and data needed to execute a
command are latched on the rising edge of WE# or
CE# (whichever goes high first). Standard
microprocessor write timings are used. Fig. 14 and
Fig. 15 illustrate WE# and CE#-controlled write
operations.

4 COMMAND DEFINITIONS

When the VPP voltage ≤ VPPLK, read operations
from the status register, identifier codes, or blocks
are enabled. Placing V

PPH1/2/3 on VPP enables

successful block erase, byte write and lock-bit
configuration operations.

Device operations are selected by writing specific
commands into the CUI. Table 3 defines these
commands.

- 10 -

Table 2 Bus Operations

MODE NOTE RP# CE# OE# WE#

ADDRESS

V

PP

DQ

0-7

RY/BY#

Read 1, 2, 3, 8

VIHor V

HH

V

IL

V

IL

V

IH

XXD

OUT

X

Output Disable 3

VIHor V

HH

V

IL

V

IH

V

IH

X X High Z X

Standby 3

VIHor V

HH

V

IH

XXXXHigh Z X

Deep Power-Down 4 VIL XXXXXHigh Z V

OH

Read Identifier Codes 8

VIHor V

HH

V

IL

V

IL

V

IH

See Fig. 2

X(

NOTE 5)

V

OH

Write 3, 6, 7, 8

VIHor V

HH

V

IL

V

IH

V

IL

XXDINX

NOTES :

1. Refer to Section 6.2.3 "DC CHARACTERISTICS".
When V

PP ≤ VPPLK, memory contents can be read, but

not altered.

2. X can be V

IL or VIH for control pins and addresses, and

V

PPLK or VPPH1/2/3 for VPP. See Section 6.2.3 "DC

CHARACTERISTICS" for V

PPLK and VPPH1/2/3 voltages.

3. RY/BY# is V

OL when the WSM is executing internal

block erase, byte write, or lock-bit configuration
algorithms. It is V

OH during when the WSM is not busy,

in block erase suspend mode (with byte write inactive),
byte write suspend mode, or deep power-down mode.

4. RP# at GND±0.2 V ensures the lowest deep power­down current.

5. See Section 4.2 for read identifier code data.

6. Command writes involving block erase, byte write, or
lock-bit configuration are reliably executed when V

PP =

V

PPH1/2/3 and VCC = VCC2/3/4. Block erase, byte write, or

lock-bit configuration with V

CC < 3.0 V or VIH < RP# <

V

HH produce spurious results and should not be

attempted.

7. Refer to Table 3 for valid D

IN during a write operation.

8. Don't use the timing both OE# and WE# are V

IL.

COMMAND

BUS CYCLES

NOTE

FIRST BUS CYCLE SECOND BUS CYCLE

REQ’D.

Oper

(NOTE 1)

Addr

(NOTE 2)

Data

(NOTE 3)

Oper

(NOTE 1)

Addr

(NOTE 2)

Data

(NOTE 3)

Read Array/Reset 1 Write X FFH
Read Identifier Codes ≥ 2 4 Write X 90H Read IA ID
Read Status Register 2 Write X 70H Read X SRD
Clear Status Register 1 Write X 50H
Block Erase 2 5 Write BA 20H Write BA D0H
Byte Write 2 5, 6 Write WA

40H or 10H

Write WA WD

Block Erase and

1 5 Write X B0H

Byte Write Suspend
Block Erase and

1 5 Write X D0H

Byte Write Resume
Set Block Lock-Bit 2 7 Write BA 60H Write BA 01H
Set Master Lock-Bit 2 7 Write X 60H Write X F1H
Clear Block Lock-Bits 2 8 Write X 60H Write X D0H

Table 3 Command Definitions

(NOTE 9)

NOTES :

1. Bus operations are defined in Table 2.

2. X = Any valid address within the device.
IA = Identifier code address : see Fig. 2.
BA = Address within the block being erased or locked.
WA = Address of memory location to be written.

3. SRD = Data read from status register. See Table 6 for a

description of the status register bits.

WD = Data to be written at location WA. Data is latched

on the rising edge of WE# or CE# (whichever
goes high first).

ID = Data read from identifier codes.

4. Following the Read Identifier Codes command, read
operations access manufacture, device, block lock, and
master lock codes. See Section 4.2 for read identifier
code data.

5. If the block is locked, RP# must be at V

HH to enable

block erase or byte write operations. Attempts to issue a
block erase or byte write to a locked block while RP# is
V

IH.

6. Either 40H or 10H is recognized by the WSM as the
byte write setup.

7. If the master lock-bit is set, RP# must be at V

HH to set a

block lock-bit. RP# must be at V

HH to set the master

lock-bit. If the master lock-bit is not set, a block lock-bit
can be set while RP# is V

IH.

8. If the master lock-bit is set, RP# must be at V

HH to clear

block lock-bits. The clear block lock-bits operation
simultaneously clears all block lock-bits. If the master
lock-bit is not set, the Clear Block Lock-Bits command
can be done while RP# is V

IH.

9. Commands other than those shown above are reserved
by SHARP for future device implementations and should
not be used.

LH28F016SC-L/SCH-L

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LH28F016SC-L/SCH-L

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4.1 Read Array Command

Upon initial device power-up and after exit from
deep power-down mode, the device defaults to
read array mode. This operation is also initiated by
writing the Read Array command. The device
remains enabled for reads until another command
is written. Once the internal WSM has started a
block erase, byte write or lock-bit configuration, the
device will not recognize the Read Array command
until the WSM completes its operation unless the
WSM is suspended via an Erase Suspend or Byte
Write Suspend command. The Read Array
command functions independently of the V

PP

voltage and RP# can be VIH or VHH.

4.2 Read Identifier Codes Command

The identifier code operation is initiated by writing
the Read Identifier Codes command. Following the
command write, read cycles from addresses shown
in Fig. 2 retrieve the manufacture, device, block
lock configuration and master lock configuration
codes (see Table 4 for identifier code values). To
terminate the operation, write another valid
command. Like the Read Array command, the
Read Identifier Codes command functions
independently of the V

PP voltage and RP# can be

V

IH or VHH. Following the Read Identifier Codes

command, the following information can be read :

Table 4 Identifier Codes

4.3 Read Status Register Command

The status register may be read to determine when
a block erase, byte write, or lock-bit configuration is
complete and whether the operation completed
successfully. It may be read at any time by writing
the Read Status Register command. After writing
this command, all subsequent read operations
output data from the status register until another
valid command is written. The status register
contents are latched on the falling edge of OE# or
CE#, whichever occurs. OE# or CE# must toggle to
V

IH before further reads to update the status

register latch. The Read Status Register command
functions independently of the V

PP voltage. RP#

can be V

IH or VHH.

4.4 Clear Status Register Command

Status register bits SR.5, SR.4, SR.3, and SR.1 are
set to "1"s by the WSM and can only be reset by
the Clear Status Register command. These bits
indicate various failure conditions (see Table 6). By
allowing system software to reset these bits,
several operations (such as cumulatively erasing or
locking multiple blocks or writing several bytes in
sequence) may be performed. The status register
may be polled to determine if an error occurred
during the sequence.

To clear the status register, the Clear Status
Register command (50H) is written. It functions
independently of the applied V

PP voltage. RP# can

be V

IH or VHH. This command is not functional

during block erase or byte write suspend modes.

4.5 Block Erase Command

Erase is executed one block at a time and initiated
by a two-cycle command. A block erase setup is
first written, followed by a block erase confirm.
This command sequence requires appropriate
sequencing and an address within the block to be
erased (erase changes all block data to FFH).
Block preconditioning, erase, and verify are handled
internally by the WSM (invisible to the system).
After the two-cycle block erase sequence is written,

CODE ADDRESS DATA

Manufacture Code 00000H 89
Device Code 00001H AA
Block Lock Configuration

X0002H

(NOTE 1)

•Block is Unlocked DQ0 = 0

•Block is Locked DQ0 = 1

•Reserved for Future Use DQ1-7
Master Lock Configuration 00003H

•Device is Unlocked DQ0 = 0

•Device is Locked DQ0 = 1

•Reserved for Future Use DQ

1-7

NOTE :

1. X selects the specific block lock configuration code to be
read. See Fig. 2 for the device identifier code memory
map.

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LH28F016SC-L/SCH-L

the device automatically outputs status register data
when read (see Fig. 3). The CPU can detect block
erase completion by analyzing the output data of
the RY/BY# pin or status register bit SR.7.

When the block erase is complete, status register
bit SR.5 should be checked. If a block erase error
is detected, the status register should be cleared
before system software attempts corrective actions.
The CUI remains in read status register mode until
a new command is issued.

This two-step command sequence of set-up
followed by execution ensures that block contents
are not accidentally erased. An invalid Block Erase
command sequence will result in both status
register bits SR.4 and SR.5 being set to "1". Also,
reliable block erasure can only occur when V

CC =

V

CC2/3/4 and VPP = VPPH1/2/3. In the absence of this

high voltage, block contents are protected against
erasure. If block erase is attempted while V

PP ≤

V

PPLK, SR.3 and SR.5 will be set to "1". Successful

block erase requires that the corresponding block
lock-bit be cleared or, if set, that RP# = V

HH. If

block erase is attempted when the corresponding
block lock-bit is set and RP# = V

IH, SR.1 and SR.5

will be set to “1”. Block erase operations with V

IH <

RP# < V

HH produce spurious results and should

not be attempted.

4.6 Byte Write Command

Byte write is executed by a two-cycle command
sequence. Byte write setup (standard 40H or
alternate 10H) is written, followed by a second write
that specifies the address and data (latched on the
rising edge of WE#). The WSM then takes over,
controlling the byte write and write verify algorithms
internally. After the byte write sequence is written,
the device automatically outputs status register data
when read (see Fig. 4). The CPU can detect the
completion of the byte write event by analyzing the
RY/BY# pin or status register bit SR.7.

When byte write is complete, status register bit
SR.4 should be checked. If byte write error is
detected, the status register should be cleared. The
internal WSM verify only detects errors for “1”s that
do not successfully write to “0”s. The CUI remains
in read status register mode until it receives another
command.

Reliable byte writes can only occur when V

CC =

V

CC2/3/4 and VPP = VPPH1/2/3. In the absence of this

high voltage, memory contents are protected
against byte writes. If byte write is attempted while
V

PP ≤ VPPLK, status register bits SR.3 and SR.4 will

be set to "1". Successful byte write requires that the
corresponding block lock-bit be cleared or, if set,
that RP# = V

HH. If byte write is attempted when the

corresponding block lock-bit is set and RP# = V

IH,

SR.1 and SR.4 will be set to "1". Byte write
operations with V

IH < RP# < VHH produce spurious

results and should not be attempted.

4.7 Block Erase Suspend Command

The Block Erase Suspend command allows block
erase interruption to read or byte write data in
another block of memory. Once the block erase
process starts, writing the Block Erase Suspend
command requests that the WSM suspend the
block erase sequence at a predetermined point in
the algorithm. The device outputs status register
data when read after the Block Erase Suspend
command is written. Polling status register bits
SR.7 and SR.6 can determine when the block
erase operation has been suspended (both will be
set to "1"). RY/BY# will also transition to V

OH.

Specification t

WHRH2 defines the block erase

suspend latency.

At this point, a Read Array command can be
written to read data from blocks other than that
which is suspended. A Byte Write command
sequence can also be issued during erase suspend
to program data in other blocks. Using the Byte

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LH28F016SC-L/SCH-L

Write Suspend command (see Section 4.8), a byte
write operation can also be suspended. During a
byte write operation with block erase suspended,
status register bit SR.7 will return to “0” and the
RY/BY# output will transition to V

OL. However,

SR.6 will remain "1" to indicate block erase
suspend status.

The only other valid commands while block erase is
suspended are Read Status Register and Block
Erase Resume. After a Block Erase Resume
command is written to the flash memory, the WSM
will continue the block erase process. Status
register bits SR.6 and SR.7 will automatically clear
and RY/BY# will return to V

OL. After the Erase

Resume command is written, the device
automatically outputs status register data when
read (see Fig. 5). V

PP must remain at VPPH1/2/3 (the

same V

PP level used for block erase) while block

erase is suspended. RP# must also remain at V

IH

or VHH (the same RP# level used for block erase).
Block erase cannot resume until byte write
operations initiated during block erase suspend
have completed.

4.8 Byte Write Suspend Command

The Byte Write Suspend command allows byte
write interruption to read data in other flash memory
locations. Once the byte write process starts,
writing the Byte Write Suspend command requests
that the WSM suspend the byte write sequence at
a predetermined point in the algorithm. The device
continues to output status register data when read
after the Byte Write Suspend command is written.
Polling status register bits SR.7 and SR.2 can
determine when the byte write operation has been
suspended (both will be set to "1"). RY/BY# will
also transition to V

OH. Specification tWHRH1 defines

the byte write suspend latency.

At this point, a Read Array command can be
written to read data from locations other than that
which is suspended. The only other valid

commands while byte write is suspended are Read
Status Register and Byte Write Resume. After Byte
Write Resume command is written to the flash
memory, the WSM will continue the byte write
process. Status register bits SR.2 and SR.7 will
automatically clear and RY/BY# will return to V

OL.

After the Byte Write Resume command is written,
the device automatically outputs status register data
when read (see Fig. 6). V

PP must remain at

V

PPH1/2/3 (the same VPP level used for byte write)

while in byte write suspend mode. RP# must also
remain at V

IH or VHH (the same RP# level used for

byte write).

4.9 Set Block and Master Lock-Bit
Commands

A flexible block locking and unlocking scheme is
enabled via a combination of block lock-bits and a
master lock-bit. The block lock-bits gate program
and erase operations while the master lock-bit
gates block-lock bit modification. With the master
lock-bit not set, individual block lock-bits can be set
using the Set Block Lock-Bit command. The Set
Master Lock-Bit command, in conjunction with RP#
= V

HH, sets the master lock-bit. After the master

lock-bit is set, subsequent setting of block lock-bits
requires both the Set Block Lock-Bit command and
V

HH on the RP# pin. See Table 5 for a summary of

hardware and software write protection options.

Set block lock-bit and master lock-bit are executed
by a two-cycle command sequence. The set block
or master lock-bit setup along with appropriate
block or device address is written followed by either
the set block lock-bit confirm (and an address
within the block to be locked) or the set master
lock-bit confirm (and any device address). The
WSM then controls the set lock-bit algorithm. After
the sequence is written, the device automatically
outputs status register data when read (see Fig. 7).
The CPU can detect the completion of the set lock­bit event by analyzing the RY/BY# pin output or
status register bit SR.7.