Sharp LC60-LE751EK232, LCxx-LE651 LC60-LE751K Schematic

October 2013

LC-xxLE651 / 751K

Training Notes

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Training Notes

MODELS:

LC39LE651K
LC39LE751K
LC50LE651K

July 2011

LC50LE751K

LC60LE651K

LC60LE751K

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Speech bubbles are training notes. Click to access the notes

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Contents

1. Model introduction

2. New Technologies

3. Block Diagrams

4. Schematic Diagrams

5. PWB’s

October 2013

6. Service Mode

7. Logging Errors

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Model Introduction

LE751K Series:

• Aquos LED series

• 1080 HD Panel with Active Motion 200

• Sharp Edge LED (Top-Bottom), FULL HD TV, 3D ready:

• 751: DVB-T/T2/C

• Aquos Net+ Based on MMH • Mobile App.

• USB Mediaplayer - • USB REC - Timeshift

• DLNA Renderer (MW 2.0 soon)

• You Tube V3 (Leanback 4 soon) • IP Control

• Broadcaster certification: BBC iPlayer

October 2013

• USB Keyboard support • USB Mouse support (from V1.43.5)
Sizes: 39”,50” and 60”.

Type of cabinet: Type of Stand: Silver

• Bottom speakers

• Silver Colour.

• Control button Unit: Touch type.

MODELS: LC39LE751K, LC50LE751K, LC60LE751K

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Model Introduction

Important Specification Notes:

• Super MVA( 39” 50” Innolux) and X-Gen (60” Sharp)

• LED Full HD Panel (1920 x 1080, 6 ms: 39” 50”, 4ms: 60”)

• 4 x HDMI 1.4 inputs (DVI compatible, up to 1080p

24/50/60Hz, 3D mode)

• Service connector (Ø 3.5 mm jack)

• Wireless Lan Ready (Included USB adapter: AN-WUD630).

• CEC ready (basic mode)

• 3 USB 2.0 terminal:

o Type: Host (A-type socket).
o Devices compatible: USB Memory, USB card
reader,HDD (Mass Storage class), USB
Keyboard, USB Mouse.

o Features: Software update, Media Player,

Smartloader, Wi-Fi, 3D glasses charge, Keyboard
& Mouse support on MMH portal.

• Media Player features: Photo, Video, Music.

• 3D ready • ARC in HDMI1 input

• YouTube (Leanback 4) • CI+ V1.3.

• 2.0 Speaker System • DLNA Certified

• DIVX HD

October 2013

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Model Introduction

LE651K Series:

• Aquos LED series

• 1080 HD Panel with Active Motion 200

• Sharp Edge LED (Top-Bottom), FULL HD TV, 3D ready:

• 751: DVB-T/T2/C

• Aquos Net+ Based on MMH • Mobile App.

• USB Mediaplayer - • USB REC - Timeshift

• DLNA Renderer (MW 2.0 soon)

• You Tube V3 (Leanback 4 soon) • IP Control

• Broadcaster certification: BBC iPlayer

October 2013

• USB Keyboard support • USB Mouse support (from V1.43.5)
Sizes: 39”,50” and 60”.

Type of cabinet: Type of Stand: Black

• Bottom speakers

• Black Colour.

• Control button Unit: Touch type.

MODELS: LC39LE651K, LC50LE651K, LC60LE651K

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Model Introduction

Important Specification Notes:

• Super MVA( 39” 50” Innolux) and X-Gen (60” Sharp)

• LED Full HD Panel (1920 x 1080, 6 ms: 39” 50”, 4ms: 60”)

• 4 x HDMI 1.4 inputs (DVI compatible, up to 1080p

24/50/60Hz, 3D mode)

• Service connector (Ø 3.5 mm jack)

• Wireless Lan Ready (Optional USB adapter: AN-WUD630).

• CEC ready (basic mode)

• 3 USB 2.0 terminal:

o Type: Host (A-type socket).
o Devices compatible: USB Memory, USB card
reader,HDD (Mass Storage class), USB
Keyboard, USB Mouse.

o Features: Software update, Media Player,

Smartloader, Wi-Fi, 3D glasses charge, Keyboard
& Mouse support on MMH portal.

• Media Player features: Photo, Video, Music.

• 3D ready • ARC in HDMI1 input

• YouTube (Leanback 4) • CI+ V1.3.

• 2.0 Speaker System • DLNA Certified

• DIVX HD

October 2013

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Model Introduction

October 2013

LE751K

LE651K

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Model Introduction

October 2013

Remote Control Units

Accessories

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Model Introduction

Part Number Comparison Table LE651K

October 2013

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Model Introduction

Part Number Comparison Table LE751K

October 2013

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New Technologies

YouTube Leanback

YouTube leanback is a new way to watch YouTube videos on your

TV. With simple controls and full screen viewing, Leanback makes
watching videos on Youtube as effortless as watching TV.

It is designed to make watching YouTube feel a bit like watching a
personalized TV channel with a really slick program guide that can
be controlled by keyboard if you are using PC. Videos display in

full-screen mode, and you press the Up Arrow key to search and

the Down Arrow key to reach playback controls, a feed of videos
tailored to your interests (which are search results if you’ve just
searched) and a browsable directory of videos in major
categories.

October 2013

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October 2013

New Technologies

LCN (Logic Channel Number)

The purpose of the Logical Channel Descriptor (LCN) is to provide a broadcaster assigned virtual

channel number or label.
The role of the LCN is to enable user presentation of service numbers in a convenient and familiar form.
To avoid conflicting allocation of LCNs:

• The logical_channel_number should be unique across all the networks that cover the same
geographical region.

• The same logical channel number should be reused only in non-adjacent regions

• Regional variants of a service may nevertheless use the same logical channel number.

Program sorting is done using LCN.
The logical channel descriptor may be inserted once in the second descriptor loop of the NIT. The logical
channel number should be unique within the same network_id (except when its value is zero) but may be
re-used for regional variants of a service, normally under different network_ids. Hence the number is not
unique within the original network. The logical channel number does not take into account the service

type.

This descriptor can be found inside NIT

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New Technologies

October 2013

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New Technologies

October 2013

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New Technologies

October 2013

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New Technologies

October 2013

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New Technologies

October 2013

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New Technologies

October 2013

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New Technologies

October 2013

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New Technologies

October 2013

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New Technologies

October 2013

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October 2013

Block Diagrams

39/50” System Block Diagram

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October 2013

Block Diagrams

60” System Block Diagram

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Block Diagrams

1. General ICs Information

DUNTKF135WE (Main Unit)

IC 1505: HDMI Switch 3 inputs to 1 output.

Part number: BU16028KV (ROHM)
Sharp code: VHIBU16028K-1Q

http://www.rohm.com/products/databook/video/pdf/bu16006kv-e.pdf

Features:

Supports 2.25 Gbps Signaling Rate for 480i/p, 720p, and
1080i/p Resolution to 12-Bit Color Depth.
Compatible with HDMI 1.3a.
5V Tolerance to all DDC and HPD_SINK Inputs.
Integrated Switchable 50ΩΩReceiver Termination.
Integrated DDC buffer.
Integrated Equalizer circuit to adapt long cable.

Major IC Information

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Block Diagrams

IC 2701: Audio Power Amplifier.

Part number: STA333BW13TR (ST MICRO)

Sharp code: VHISTA333BW-1L.

http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATASHEET/CD00166760.pdf

Features:
Wide-range supply voltage, 4.5 V to 21.5 V.
Three power output configurations:
o 2 channels of ternary PWM (2 x 20 W into 8 Ω at 18 V) + PWM output.
o 2 channels of ternary PWM (2 x 20 W into 8 Ω at 18 V) + ternary stereo
line-out.
o 2.1 channels of binary PWM (left, right, LFE) (2 x 9 W into 4 Ω +1 x 20 W
into 8 at 18 V).
FFX with 100-dB SNR and dynamic range.
Scalable FFX modulation index.

Selectable 32- to 192-kHz input sample rates.

I2C control with selectable device address.
Digital gain/attenuation +48 dB to -80 dB with 0.5-dB/step resolution.
Soft volume update with programmable ratio.
Individual channel and master gain/attenuation.

Major IC Information…cont

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Block Diagrams

Features…cont
Dynamic range compression (DRC) or anti-clipping mode.
Audio presets:

o 15 preset crossover filters.

o 5 preset anti-clipping modes.
o Preset night-time listening mode.
Individual channel soft/hard mute.
Independent channel volume and DSP bypass.
I2S input data interface.
Input and output channel mapping.

Automatic invalid input-detect mute.

Up to 5 user-programmable bi-quads by channel.
Three coefficients banks for EQ presets storing with fast recall via I2C interface.
Bass/treble tones and de-emphasis control.
Selectable high-pass filters for DC blocking.
Advanced AM interference frequency switching and noise suppression modes.
Sub channel mix into left and right channels.
Selectable high- or low-bandwidth noise-shaping topologies.
Selectable clock input ratio.
96-kHz internal processing sample rate.
Thermal overload and short-circuit protection technology
Video apps: 576 x fs input mode supported.

Major IC Information…cont

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Block Diagrams

Major IC Information…cont

IC 2702: Headphone Amplifier.

Part number: TS488IQT (ST MICRO)
Sharp code : RH-IXD542WJZZY.

Features:
Pop and click noise protection circuitry.
Operating range from VCC = 2.2 V to 5.5 V.

Standby mode active low (TS488) or high (TS489).

Output power:

– 120 mW at 5 V, into 16 Ω with 0.1% THD+N max (1 kHz).
– 55 mW at 3.3 V, into 16 Ω with 0.1% THD+N max (1 kHz).

Low current consumption: 2.7 mA max at 5 V. High signal-to-noise ratio.
Ultra-low standby current consumption: 10 nA typical. Unity-gain stable.

High crosstalk immunity: 102 dB (F = 1 kHz). Short-circuit protection circuitry.

PSRR: 70 dB typ. (F = 1 kHz), inputs grounded at 5 V.

http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/CD00083715.pdf

The TS488/9 is an enhancement of TS486/7 that eliminates pop and click noise and reduces the number of
external passive components. The TS488/9 is a dual audio power amplifier capable of driving, in single-ended

mode, either a 16 Ω or a 32 Ω stereo headset. Capable of descending to low voltages, it delivers up to 31mW per
channel (into 16 Ω loads) of continuous average power with 0.1% THD+N in the audio bandwidth from a 2.5 V

power supply.

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Block Diagrams

Major IC Information…cont

IC9552: USB 2.0 Hi-Speed Hub Controller

Part number: USB2514B-AEZG (SMSC)
Sharp code: VHI2514BAEZ-1Q

http://www.smsc.com/Downloads/SMSC/Downloads_Public/Data_Sheets/251xb.pdf

The SMSC USB251x hub is a family of low-power, OEM configurable, MTT (multi transaction translator) 1 hub
controller IC products for embedded USB solutions. The “x” in the part number indicates the number of
downstream ports available. The SMSC hub supports low-speed, fullspeed, and hi-speed (if operating as a hi-speed
hub) downstream devices on all of the enabled downstream ports.

Features

Full power management with individual or ganged power control of each
downstream port.
Fully integrated USB termination and pull-up/pull-down resistors.
Supports a single external 3.3 V supply source; internal regulators
provide 1.2 V or 1.8 V internal core voltage.

On-chip driver for 24 MHz crystal resonator or external 24/48 MHz clock.

Customizable vendor ID, product ID, and device ID.
ESD protection up to 4 kilovolts on all USB pins.
Supports self- or bus-powered operation.
USB251xB2 and USB251xBi products support the USB Battery
Charging specification.
Package: 36-pin QFN (6x6 mm).

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Block Diagrams

Major IC Information…cont

IC 3501, IC3502 & IC 3503: 2Gb 16Bits DDR3-1600 SDRAM

Part number: MT41J128M16JT-125:K (MICRON)

Sharp code: RH-IXD538WJZZQ

http://www.micron.com/~/media/Documents/Products/Data%20Sheet/DRAM/2Gb_DDR3_SDRAM.pdf

DDR3 SDRAM uses double data rate architecture to achieve high-speed operation. The double data rate architecture is
an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A
single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock cycle data
transfer at the internal DRAM core and eight corresponding n-bit-wide, one half-clock-cycle data transfers at the I/O
pins. The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the
DDR3 SDRAM input receiver. DQS is center-aligned with data for WRITEs. The read data is transmitted by the DDR3
SDRAM and edge-aligned to the data strobes.
The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK going HIGH and CK# going LOW is
referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of
CK. Input data is registered on the first rising edge of DQS after the WRITE preamble, and output data is referenced on
the first rising edge of DQS after the READ preamble.

Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a selected location and continue for

a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE
command, which is then followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with
the READ or WRITE commands are used to select the bank and the starting column location for the burst access.

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