Datasheet VNQ810M Datasheet (SGS Thomson Microelectronics)

M

®

Janua ry 20 03 1/20

VNQ810M

QUAD CHANNEL HIGH SIDE DRIVER

■ CMOS COMPATIBLE INPUTS

■ OPEN DRAIN STATUS OUTPUTS

■ ON STATE OPEN LOAD DETECTION

■ OFF STATE OPEN LOAD DETECTION

■ SHORTED LOAD PROTECTION

■ UNDERVOLTAGE AND OVERVOLTAGE

SHUTDOWN

■ PROTECTION AGAINST LOSS OF GROUND

■ VERY LOW STAND-BY CURRENT

■ REVERSE BATTERY PROTECTION (**)

DESCRIPTION

The VNQ810M is a quad HSD formed by
assembling two VND810M chips in the same SO­28 package.The VND810M is a monolithic device
made by using STMicroelectronics VIPower M0-3
Technology, i ntended for dr iving any ki nd of load
with one side connected to ground.
Active VCC pin voltage clamp protec ts the device

against low energy spikes (see ISO7637 transient
compatibility table). Active current limitation
combined with thermal shutdown a nd automatic
restart protects the device against over load. The
current lim itation threshold is aimed at detectin g
the 21W/12V st andard b ulb as an overl oad fau lt.
The device detects open load condition both in on
and off state . Output shorted to VCC is detected
in the off state. Device automatically turn s off in
case of ground pin disconnection.

TYPE R

DS(on)

I

OUT

V

CC

VNQ810M 150 mΩ (*) 0.6 A (*) 36 V

SO-28 (DOUBLE ISLAND)

ORDER CODES

PACKAGE TUBE T&R

SO-28

VNQ810M VNQ810M13TR

(*) Per each channel

ABSOLUTE MAXIMUM RATING

(**) See ap plication schematic at page 9

Symbol Parameter Value Unit

V

CC

DC Supply Vol tage 41 V

- V

CC

Reverse DC Supply Volt age -0.3 V

- I

gnd

DC Reverse Ground Pin Current -200 mA

I

OUT

DC Output Current Internally Limited A

- I

OUT

Reverse DC Ou tput Current -6 A

I

IN

DC Input Curre nt +/- 10 mA

I

STAT

DC Status Curr ent +/- 10 mA

V

ESD

Electro static Discharge (Hum an Body Model: R=1.5KΩ; C=100pF)

- INPUT

- STATUS

- OUTPUT

- V

CC

4000
4000
5000
5000

V
V
V
V

E

MAX

Maximum Switching Energy
(L=310mH; R

L

=0Ω; V

bat

=13.5V; T

jstart

=150ºC; IL=0.9A)

174 mJ

P

tot

Power dissipation (per island) at T

lead

=25°C 6.25 W

T

j

Junction Operating Temperature Internally Limited °C

T

stg

Storage Temperat ure -55 to 150 °C

2/20

VNQ810M

BLOCK DIAGRAM

OVERTEMP. 1

V

CC1,2

GND1,2

INPUT1

OUTPUT1

OVERVOLTAGE

LOGIC

DRIVER 1

STATUS1

V

cc

CLAMP

UNDERVOLTAGE

CLAMP 1

OPENLOAD ON 1

CURRENT LIMITER 1

OPENLOAD OFF 1

OUTPUT2

DRIVER 2

CLAMP 2

OPENLOAD ON 2

OPENLOAD OFF 2

OVERTEMP. 2

INPUT2

STATUS2

CURRENT LIMITER 2

OVERTEMP. 3

V

CC3,4

GND3,4

INPUT3

OUTPUT3

OVERVOLT AGE

LOGIC

DRIVER 3

STATUS3

V

cc

CLAMP

UNDERVOLTAGE

CLAMP 3

OPENLOAD ON 3

CURRENT LIMITER 3

OPENLOAD OFF 3

OUTPUT4

DRIVER 4

CLAMP 4

OPENLOAD ON 4

OPENLOAD OFF 4

OVERTEMP. 4

INPUT4

STATUS4

CURRENT LIMITER 4

3/20

VNQ810M

CONNECTI O N DIAGR A M (TOP VIE W )

CURRENT AND VOLTAGE CONVENTIONS

VCC1,2
GND 1,2
INPUT1
STATUS1
STATUS2

V

CC

1,2

V

CC

3,4
GND 3,4
INPUT3

STATUS3

V

CC

3,4

V

CC

3,4

OUTPUT4

OUTPUT4

OUTPUT4

OUTPUT3

OUTPUT2

OUTPUT2

OUTPUT2

OUTPUT1

V

CC

1,2

OUTPUT3

OUTPUT3

OUTPUT1

OUTPUT1

INPUT2

STATUS4
INPUT4

1

14 15

28

I

S3,4

I

GND1,2

OUTPUT3

V

CC3,4

GND

1,2

INPUT2

I

OUT3

V

CC1,2

V

OUT4

OUTPUT2

I

OUT2

V

OUT3

INPUT1

I

IN1

STATUS1

I

STAT1

OUTPUT1

I

OUT1

OUTPUT4

I

OUT4

V

OUT2

V

OUT1

I

IN2

I

STAT2

I

STAT3

I

IN4

I

STAT4

STATUS2

STATUS3

STATUS4

INPUT3

INPUT4

V

STAT4

V

IN4

V

STAT3

V

IN3

V

STAT2

I

IN3

V

IN2

V

STAT1

V

IN1

I

S1,2

V

CC1,2

GND

3,4

I

GND3,4

V

CC3,4

4/20

VNQ810M

THERMAL DATA (Per island)

(*) When mounted on a standar d single-s ided FR-4 boar d with 0.5cm2 of Cu (at leas t 35µ m thick) co nnec ted to all VCC pins.

Horizontal mounting and no artificial air flow.

ELECTRICAL CHARACTERISTICS (8V<VCC<36V; -40°C< Tj <150°C, unless otherwise specified)

POWER OUTPUTS (Per each channel)

SWITCHING (Per each Channel) (VCC=13V)

LOGIC INPUT (Per each channel)

(**) Per island

Symbol Parameter Value Unit

R

thj-lead

Thermal R esistanc e Junctio n-lead per chip 20 °C/W

R

thj-amb

Thermal Resistance Junction-ambient (one chip ON) 60 (*) °C/W

R

thj-amb

Thermal Resistance Junction-ambient (two chips ON ) 46 (*) °C/W

Symbol Parameter Test Conditions Min Typ Max Unit

V

CC

(**) Operating Supply Voltage 5.5 13 36 V

V

USD

(**) Undervoltage Shut-down 3 4 5.5 V

V

OV

(**) Overvoltage Shut-down 36 V

R

ON

On State Resistance

I

OUT

=0.5A; Tj=25°C

I

OUT

=0.5A; VCC> 8V

150
300

mΩ
mΩ

I

S

(**) Supply Current

Off State; V

CC

=13V; VIN=V

OUT

=0V

Off State; V

CC

=13V; VIN=V

OUT

=0V;

T

j

=25°C

On State; V

CC

=13V; VIN=5V; I

OUT

=0A

12

12

5

40

25

7

µA

µA

mA

I

L(off1)

Off State Output Curr ent VIN=V

OUT

=0V 0 50 µA

I

L(off2)

Off State Output Curr ent VIN=0V; V

OUT

=3.5V -75 0 µA

I

L(off3)

Off State Output Curr ent VIN=V

OUT

=0V; Vcc=13V; Tj =125°C 5 µA

I

L(off4)

Off State Output Curr ent VIN=V

OUT

=0V; Vcc=13V; Tj =25°C 3 µA

Symbol Parameter Test Conditions Min Typ Max Unit

t

d(on)

Turn-on Delay Time RL=26Ω from VIN rising edge to V

OUT

=1.3V 30 µs

t

d(off)

Turn-off Dela y Ti me

RL=26Ω from VIN falling edge to
V

OUT

=11.7V

30 µs

dV

OUT

/dt

(on)

Turn-on Voltage Slope RL=26Ω from V

OUT

=1.3V to V

OUT

=10.4V

See

relative

diagram

V/µs

dV

OUT

/dt

(off)

Turn-off Voltage Slope RL=26Ω from V

OUT

=11.7V to V

OUT

=1.3V

See

relative

diagram

V/µs

Symbol Param eter Test Conditions Min Typ Max Unit

V

IL

Input Low Level 1.25 V

I

IL

Low Level Input Current VIN = 1.25V 1 µA

V

IH

Input High Level 3.25 V

I

IH

High Level Input Curr ent VIN = 3.25V 10 µA

V

I(hyst)

Input Hyst eresis Voltage 0.5 V

V

ICL

Input Clamp Voltage

I

IN

= 1mA

I

IN

= -1mA

66.8

-0.7

8V

V

1

5/20

VNQ810M

VCC - OUTPUT DIODE

ELECTRICAL CHARACTERISTICS (continued)
STATUS PIN (Per each channel)

PROTECTIONS (Per each channel)

OPENLOAD DETECTION (per each channel)

Symbol Param eter Test Conditions Min Typ Max Unit

V

F

Forward on Voltage -I

OUT

=0.5A; Tj=150°C 0.6 V

Symbol Parameter Test Conditions Min Typ Max Unit

V

STAT

Status Low Output Voltage I

STAT

= 1.6 mA 0.5 V

I

LSTAT

Status Leakage Current Normal Operation; V

STAT

= 5V 10 µA

C

STAT

Status Pin Input
Capacitance

Normal Operation; V

STAT

= 5V 100 pF

V

SCL

Status Clamp Voltage

I

STAT

=1mA

I

STAT

=-1mA

66.8

-0.7

8V

V

Symbol Parame ter Test Condit ions Min Ty p Max Unit

T

TSD

Shut-down Temperature 150 175 200 °C

T

R

Reset Temp erature 135 °C

T

hyst

Ther ma l Hy steres i s 7 15 °C

t

SDL

Status Delay in Overload
Conditions

Tj>T

TSD

20 µs

I

lim

Current limitation

5.5V < V

CC

< 36V

0.7 0.9 1.4

1.4

A
A

V

demag

Turn-off Output Clamp
Voltage

I

OUT

=0.5A VCC-41 VCC-48 VCC-55 V

Symbol Param eter Test Conditions Min Typ M ax Uni t

I

OL

Openload ON State
Detectio n Threshold

V

IN

=5V 20 40 80 mA

t

DOL(on)

Openload ON State
Detection Delay

I

OUT

=0A 200 µs

V

OL

Openload OFF State
Voltage Detection
Threshold

VIN=0V 1.5 2.5 3.5 V

t

DOL(off)

Openload Detection Delay
at Turn Off

1000 µs

2

V

INn

V

STATn

t

DOL(off)

OPENLOAD STATUS TIMING (with external pull-up)

V

INn

V

STATn

OVERTEMP STA TUS TIMING

t

SDL

t

SDL

I

OUT

< I

OL

V

OUT

> V

OL

t

DOL(on)

Tj > T

TSD

6/20

VNQ810M

t

t

v

OUTn

V

INn

80%

10%

dV

OUT

/dt

(on)

t

d(off)

90%

dV

OUT

/dt

(off)

t

d(on)

Switching time Waveforms

TRUTH TABLE

CONDITIONS INPUT OUTPUT STATUS

Normal Operation

L

H

L

H

H
H

Current Limitation

L
H
H

L
X
X

H

(T

j

< T

TSD

) H

(T

j

> T

TSD

) L

Overtemperature

L

H

L

L

H

L

Undervoltage

L

H

L

L

X
X

Overvoltage

L

H

L

L

H
H

Output Voltage > V

OL

L

H

H
H

L

H

Output Current < I

OL

L

H

L
H

H

L

7/20

VNQ810M

ELECTRICAL TRANS IENT REQUIREMENTS O N VCC PIN

ISO T/R 7637/1

Test Pulse

TEST LEVELS

I II III IV Delays and

Impedance

1 -25 V - 50 V -75 V -100 V 2 ms 10 Ω

2 +25 V +50 V +75 V + 100 V 0.2 ms 10 Ω
3a -25 V -50 V -100 V -150 V 0.1 µs 50 Ω
3b +25 V +50 V +75 V +100 V 0.1 µs 50 Ω

4 -4 V -5 V -6 V -7 V 100 ms, 0.01

Ω

5 +26.5 V +46.5 V +66.5 V +86.5 V 400 ms, 2

Ω

ISO T/R 76 37 / 1

Test Pulse

TEST LEVELS RESULTS

I II III IV

1CCCC

2CCCC
3aCCCC
3bCCCC

4CCCC

5CEEE

CLASS CONTENTS

C All functions of t he device ar e performed as designed afte r exposure to disturbance.
E One or more f unctions of the device is not performed as designe d after exposure and cannot be

returned to proper operat ion without replacing the device.

8/20

VNQ810M

1

OPEN LOAD without external pull-up

STATUS

n

INPUT

n

NORMAL OPERATION

UNDERVOLTAGE

V

CC

V

USD

V

USDhyst

INPUT

n

OVERVOLTAGE

V

CC

STATUS

n

INPUT

n

STATUS

n

STATUS

n

INPUT

n

STATUS

n

INPUT

n

OPEN LOAD wi th external pull-up

undefined

OVERTEMPE RATURE

INPUT

n

STATUS

n

T

TSD

T

R

Figure 1: Waveforms

T

j

OUTPUT VOLTAGE

n

VCC<V

OV

OUTPUT VOLTAGE

n

OUTPUT VOLTAGE

n

OUTPUT VOLTAGE

n

OUTP U T VO LTAGE

n

OUTPUT CURRENT

n

VCC>V

OL

V

OL

V

OUT>VOL

9/20

VNQ810M

GND PROTECTION NETWORK AGAINST
REVERSE BATTERY

Soluti on 1: Resistor in the ground line (R

GND

only). This

can be us ed with any type of load .
The fo llowing i s an indication on how to dimen sion the

R

GND

resistor.

1) R

GND

≤ 600mV / 2(I

S(on)max

).

2) R

GND

≥ (−VCC) / (-I

GND

)

where -I

GND

is the DC re vers e grou nd pi n cu rren t an d can

be found in the abso lute maximum rating section of the

device’s datasheet.
Power Dissipa tion in R

GND

(when VCC<0: during reverse

battery situations) is:

P

D

= (-VCC)2/R

GND

This resistor can be shared amongst several different
HSD. Please note that the value of this resistor should be
calculat ed wit h for mula (1) wh ere I

S(on)max

becomes the
sum of th e maximum on-state currents of the different
devices.

Please note that if the microprocessor ground is not
common with the device ground then the R

GND

will

produce a shi ft (I

S(on)max

* R

GND

) in the input thresholds
and the status output values. This shift will vary
depending on how man y devic es are ON in the ca se of
several high side drivers s haring the same R

GND

.

If the calculated power dissipation leads to a large resistor
or seve ral de vic es have to s hare t he s ame r esisto r then
the ST suggests to uti li ze Solution 2.

APPLICATION SCHEMATIC

V

CC1,2

OUTPUT2

+5V

R

prot

OUTPUT1

STA T US1

INPUT1

+5V

STA T US2

INPUT2

+5V

D

GND

R

GND

V

GND

GND1,2

GND3,4

OUTPUT 3

OUTPUT4

µ

C

V

CC3,4

STA TUS3

INPUT3

STA T US4

INPUT4

+5V

+5V

R

prot

R

prot

R

prot

R

prot

R

prot

R

prot

R

prot

D

ld

Note: Channels 3 & 4 have the same internal circuit as ch annel 1 & 2.

10/20

VNQ810M

Soluti o n 2: A diode (D

GND

) in the gr ound line .

A resistor (R

GND

=1kΩ) should be inserted in parallel to

D

GND

if the devi ce will be dri ving an in ductive load.

This small signal diode can be safely shared amongst
several different HSD. Also in this case, the presence of
the grou nd netwo rk will prod uce a shi ft (

j

600mV) i n the
input threshold and the status output values if the
microprocessor ground is not common with the device
ground. This shift will not vary if more than one HSD
shares the same diode/resistor network.

LOAD DUMP PROTECTION

Dld is necessary (Voltage Transient Suppressor) if the
load dump peak voltage exceeds VCC max DC rating. The
same applies if the device will be subj ect to transient s on
the VCC line that are greater than the ones shown in the
ISO T/R 7637/1 table.

µ

C I/Os PROTECTION:

If a ground protection network is used and negative
trans ien ts are pr esen t on t he VCC line, t he c ontro l pi ns wi ll
be pu lled negative . S T suggests to insert a resi st o r (R

prot

)

in line to prevent t he µC I/Os pins to latch-up.
The value of these resistors is a compromise between

the leakage current of µC and th e current required by the
HSD I/Os (Inp ut le vels comp atibilit y) wit h the lat ch-up li mit
of µC I/Os.

-V

CCpeak/Ilatchup

≤ R

prot

≤ (V

OHµC-VIH-VGND

) / I

IHmax

Calculation example:
For V

CCpeak

= - 100V an d I

latchup

≥ 20mA; V

OHµC

≥ 4.5V

5kΩ ≤ R

prot

≤ 65kΩ.

Recommended R

prot

value is 10kΩ.

11/20

VNQ810M

OPEN LOAD DETECTION IN OFF STATE

Off state open load detection requires an external pu ll-up
resistor (R

PU

) connected between OUTPUT pin and a

positive supply voltage (V

PU

) like the +5 V line used to

supply the microprocessor.
The external resistor has to be selected according to the
following requirements:

1) no f al se op en load i nd icat ion wh en load i s co nne cted :

in thi s case we have to avoi d V

OUT

to be hi gher than

V

Olmin

; this results in the follo wing condition

V

OUT

=(VPU/(RL+RPU))RL<V

Olmin.

2) no misdetection when load is disconnected: in this
case the V

OUT

has to be higher than V

OLmax

; this

results in the following c ondition R

PU

<(V

PU–VOLma x

)/

I

L(off2)

.

Beca us e I

s(OFF)

may si gn ifi c a ntly increase i f V

out

is pulled

high (up t o several mA ), the pul l-up resi stor R

PU

should

be conne cted t o a su pp ly t ha t is swit ch ed OFF when t h e
module is in standby.
The values of V

OLmin

, V

OLmax

and I

L(off2)

are available in

the Electrical Characteristics section.

V

OL

V batt. VPU

R

PU

R

L

R

DRIVER

+

LOGIC

+

-

INPUT

STATUS

V

CC

OUT

GROUND

I

L(off2)

Open Load detection in off state

12/20

VNQ810M

High Level Input Current

Input Clamp Voltage Status Leakage Current

Off State Output Current

Status Clamp VoltageStatus Low Output Voltage

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Iih (uA)

Vin=3.25V

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

6

6.2

6.4

6.6

6.8

7

7.2

7.4

7.6

7.8

8

Vicl (V)

Iin=1mA

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

0

0.01

0.02

0.03

0.04

0.05

Ilstat (uA)

Vstat=5V

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Vstat (V)

Istat=1.6mA

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

6

6.2

6.4

6.6

6.8

7

7.2

7.4

7.6

7.8

8

Vscl (V)

Istat=1mA

-50 -25 0 25 50 75 100 125 150 175

Tc (ºC)

0

0.16

0.32

0.48

0.64

0.8

0.96

1.12

1.28

1.44

1.6

IL(off1) (uA)

Off state
Vcc=36V

Vin=Vout=0V

13/20

VNQ810M

Input Hysteresis VoltageInput Low Level

On State Resistance Vs T

case

On State Resistance Vs V

CC

Input High LevelOpenload On State Detection Threshold

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

Vih (V)

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

1

1.2

1.4

1.6

1.8

2

2.2

2.4

2.6

Vil (V)

-50 -25 0 25 50 7 5 100 125 150 175

Tc (°C)

0.5

0.6

0.7

0.8

0.9

1

1.1

1.2

1.3

1.4

1.5

Vhyst (V)

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

10

15

20

25

30

35

40

45

50

55

60

Iol (mA)

Vcc=13V

Vin=5V

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

0

50

100

150

200

250

300

350

400

Ron (mOhm)

Iout=1A

Vcc=8V; 13V & 36V

5 10152025303540

Vcc (V)

50

75

100

125

150

175

200

225

250

275

300

Ron (mOhm)

Iout=1A

Tc= - 40°C

Tc= 25°C

Tc= 150°C

14/20

VNQ810M

Overvoltage Shutdown

Turn-on Voltage Slope Turn-off Voltage Slope

I

LIM

Vs T

case

Openload Off State Voltage Detection Threshold

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

30

32

34

36

38

40

42

44

46

48

50

Vov (V)

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Vol (V)

Vin=0V

-50 -25 0 25 50 75 100 125 150 175

Tc (ºC)

0

100

200

300

400

500

600

700

800

900

1000

dVout/dt(on) (V/ms)

Vcc=13V

Rl=13Ohm

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

0

50

100

150

200

250

300

350

400

450

500

dVout/dt(off) (V/ms)

Rl=26Ohm

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Ilim (A)

Vcc=13V

15/20

VNQ810M

Maximum turn off current versus load inductance

A = Single Pulse at T

Jstart

=150ºC

B= Repetitive pulse at T

Jstart

=100ºC

C= Repetitive Pulse at T

Jstart

=125ºC

Conditions:
VCC=13.5V

Values are generated with RL=0Ω
In case of repetitive pulses, T

jstart

(at beginning of each demagnetization) of every pulse must not exceed

the temperature specified above for curves B and C.

VIN, I

L

t

Demagnetization

Demagnetization

Demagnetization

0.1

1

10

1 10 100 1000

L(mH)

I

LMAX (A)

A

B

C

16/20

VNQ810M

SO-28 Double island PC Board

Thermal calculation according to the PCB heatsink area

R

thA

= Thermal resistance Junction to Ambient with one chip ON

R

thB

= Thermal resistance Junction to Ambient with both chips ON and P

dchip1=Pdchip2

R

thC

= Mutual thermal resistance

R

thj-amb

Vs. PCB copper area in open box free air condition

Chip 1 Chip 2 T

jchip1

T

jchip2

Note

ON OFF R

thA

x P

dchip1

+ T

amb

R

thC

x P

dchip1

+ T

amb

OFF ON R

thC

x P

dchip2

+ T

amb

R

thA

x P

dchip2

+ T

amb

ON ON R

thB

x (P

dchip1

+ P

dchip2

) + T

amb

R

thB

x (P

dchip1

+ P

dchip2

) + T

amb

P

dchi p1=Pdchi p2

ON ON (R

thA

x P

dchip1

) + R

thC

x P

dchip2

+ T

amb(RthA

x P

dchip2

) + R

thC

x P

dchip1

+ T

ambPdchip1≠Pdchip2

SO-28 DOUBLE ISLAND THERMAL DAT A

Layout condition of Rth and Zth measur ements (PCB FR4 area= 58mm x 58mm, PCB thick ness=2m m ,
Cu thickness=35µm, Copper areas: 0.5cm

2

, 3cm2, 6cm2).

10

20

30

40

50

60

70

01234567

PCB Cu heatsink area (cm^2)/island

RTHj_amb

(°C/W)

R

thA

R

thB

R

thC

17/20

VNQ810M

Thermal fitting model of a four channels HSD
in SO-28

Pulse calculation formula

Thermal Parameter

Area/island (cm2)0.56

R1=R7= R13=R15 (°C/W) 0.35
R2=R8= R14=R16 (°C/W) 1.8
R3=R9 ( ° C/W) 4.5
R4=R10 (°C/W) 11
R5=R11 (°C/W) 15
R6=R12 (°C/W) 30 13
C1=C7=C13=C15 (W.s/°C) 0.0001
C2=C8=C14=C16 (W.s/°C) 7.00E-04
C3=C9 (W.s/°C) 6.00E-03
C4=C10 (W.s/°C ) 0.2
C5=C11 (W.s/°C ) 1.5
C6=C12 (W.s/°C ) 5 8
R17=R18 (°C/W) 150

Z

THδ

RTHδ Z

THtp

1 δ–()+⋅=

where

δ tpT⁄=

SO-28 Thermal Impedance Junction Ambient Single Pulse

0.01

0.1

1

10

100

0.0001 0.001 0.01 0.1 1 10 100 1000

time(s)

Zth(°C/W)

6 cm ^2/island

3 cm ^2/island

0,5 cm^2/island

One channel ON
Two channels

ON on same chip

Pd1

C1

R4

C3 C4

R3R1 R6R5R2

C5 C6C2

Pd2

R14

C13 C14

R13

Tj_1

Tj_2

T_amb

Pd3

C7

R10

C9

C10

R9R7 R12R11R8

C11 C12

C8

Pd4

R16

C15 C16

R15

Tj_3

Tj_4

R17 R18

18/20

VNQ810M

DIM.

mm. inch

MIN. TYP MAX. MIN. TYP. MAX.

A 2.65 0.104

a1 0.10 0.30 0.004 0.012

b 0.35 0.49 0.013 0.019

b1 0.23 0.32 0.009 0.012

C 0.50 0.020

c1 45 (typ .)

D 17.7 18.1 0.697 0.713
E 10 .00 10.65 0. 393 0.419

e 1.27 0.050

e3 16.51 0.650

F 7.40 7.60 0.291 0.299
L 0.40 1.27 0.016 0.050

S8 (max.)

SO-28 MECHANICAL DATA

19/20

VNQ810M

SO-28 TUBE SHIPMENT (no suffix)

All dimensions are in mm.

Base Q.ty 28
Bulk Q.ty 700
Tube length (± 0.5) 532

A 3.5
B 13.8
C (± 0.1) 0.6

TAPE AND REEL SHIPMENT (suffix “13TR”)

Base Q.ty 1000
Bulk Q.ty 1000
A (max) 330
B (min) 1.5
C (± 0.2) 13

F 20.2
G (+ 2 / -0) 16.4
N (min) 60
T (max) 22.4

TAPE DIMENSIONS

According to Electronic Industries Associat ion
(EIA) S tandard 481 rev. A, Feb 1986

All dimensions are in mm.

Tape width W 16
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 12
Hole Diameter D (± 0.1/-0) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.05) 7.5
Compartment Depth K (max) 6.5
Hole Spacing P1 (± 0.1) 2

Top

cover

tape

End

Start

No componentsNo components Components

500mm min

500mm min

Empty components pockets
saled with cover tape.

User direction of feed

A

C

B

REEL DIMENSIONS

20/20

VNQ810M

Information furnished is believed to be acc ur ate and reliable. Howev er, STMicroel ec tronics assumes no responsibility for the co nsequences
of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is
granted by implication or otherwise u nder any patent or patent rights of STMicroelectronics. Specifications mentio ned in this publication are
subject to c hange without notice. This publication supersedes and replaces all information previously supplied. STMic r oelectronics produc ts
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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