SGS Thomson Microelectronics VNS3NV04, VNN3NV04, VND3NV04-1, VND3NV04 Datasheet
®
VNN3NV04 / VNS3NV04
/ VND3NV 04 / VND3NV0 4-1
“OMNIFE T II” :
FULLY AUTOPROTECTED POWER MOSFET
TYPE R
VNN3NV04
VNS3NV04
VND3NV04
VND3NV04-1
n
LINEAR CURRENT LIMITATION
n
THERMAL SHUT DOWN
n
SHORT CIRCUIT PROTECTION
n
INTEGRATED CLAMP
n
LOW CURRENT DRAWN FRO M INPUT PIN
n
DIAGNOSTIC FEEDBACK THROUGH INPUT
DS(on)
120 mΩ 3.5 A 40 V
I
lim
V
clamp
PIN
n
ESD PROTECTION
n
DIRECT ACCESS TO THE GATE OF THE
POWER MOSFET (ANALOG DRIVING)
n
COMPATIBLE WITH STANDARD POWER
MOSFET
DESCRIPTION
The VNN3NV04, VNS3NV04, VND3NV04
VND3NV04-1, are mon ol ithi c devic es desi g ned in
STMicroelectronics VIPower M0-3 Technology,
BLOCK DIAGRAM
2
3
2
1
SOT-223
3
1
TO252 (DPAK)
ORDER CODES:
SOT-223
SO-8
TO-252 (DPAK)
TO-251 (IPAK)
SO-8
1
TO251 (IPAK)
VNN3NV04
VNS3NV04
VND3NV04
VND3NV04-1
3
2
intended for replacement of standard Power
MOSFETS from DC up to 50KHz applications.
Built in thermal shutdown, l inear curren t limitation
and overvoltage clamp protect the chip in harsh
environments.
Fault feedback can be de tected by mon itori ng the
voltage at the input pin.
DRAIN
2
INPUT
1
Februa ry 2003 1/21
Gate
Control
Over
Temperature
Overvoltage
Clamp
Linear
Current
Limiter
3
SOURCE
FC01000
VNN3NV04 / VNS3NV04 / VND3NV04 / VND3NV04-1
ABSOLUTE MAXIMUM RATI NG
Symbol Parameter
Drain-source Voltage (VIN=0V) Intern ally Clam p ed V
Input Voltage Internally Clamped V
IN
Input Current +/-20 mA
Minimum I nput Series Impedance 220 Ω
Drain Current Internally Limited A
Reverse DC Output Current -5.5 A
Electros tatic Discharge (R=1.5KΩ, C=100pF) 4000 V
Electros tatic Discharge on output pin only
(R=330Ω, C=150pF)
Total Dissipation at Tc=25°C 7 8.3 35 W
tot
Operating Junction Temperature Internally limited °C
j
Case Operating Temperature Internally limit ed °C
c
Storage Temperatu re -55 to 150 °C
R
V
V
V
DS
V
I
IN
IN MIN
I
D
I
R
ESD1
ESD2
P
T
T
T
stg
CONNECTION DIAGRAM (TO P VI EW)
SO-8 Pack ag e (*)
SOT-223 SO-8 DPAK/IPAK
Value
Unit
16500 V
SOURCE
1
SOURCE
SOURCE
INPUT
(*) For the pins configuration related to SOT-223, DPAK, IPAK see outlines at page 1.
4
CURRENT AND VOLTAGE CONVENTIONS
R
I
IN
IN
INPUT
V
IN
8
DRAIN
DRAIN
DRAIN
5
DRAIN
DRAIN
SOURCE
I
D
V
DS
2/21
VNN3NV04 / VNS3NV04 / VND3NV04 / VND3NV04-1
THERMAL DATA
Symbol Parameter
R
thj-case
R
thj-lead
R
thj-amb
(*) When mounted on a standard single-sided FR4 board with 50mm
Thermal R esistance Junction-case}} } MAX 18 3.5 3.5 °C/W
Thermal R esistance Junction-lead MAX 15 °C/W
Thermal R esistance Junction -ambient MAX 70(*) 65(*) 54(*) 100 °C/W
SOT-223 SO-8 DPAK IPAK
2
of Cu (at leas t 35 µm thick) connected to all DRAIN pins.
ELECTRICAL CHARACTERISTICS (-40°C < Tj < 150°C, unless otherwise specified)
OFF
Symbol Parameter Test Conditions Min Typ Max Unit
V
CLAMP
V
CLTH
V
INTH
I
ISS
V
INCL
I
DSS
Drain-source Clamp
Voltage
Drain-source Clamp
Threshold Voltage
Input Thre shold Voltage VDS=VIN; ID=1mA 0. 5 2.5 V
Supply Current from Input
Pin
Input-Source Clamp
Voltage
Zero Input Voltage Drain
Current (VIN=0V)
V
=0V; ID=1.5A 40 45 55 V
IN
VIN=0V; ID=2mA 36 V
VDS=0V; VIN=5V 100 150 µA
IIN=1mA
I
=-1mA
IN
=13V; VIN=0V; Tj=25°C
V
DS
V
=25V; VIN=0V
DS
Value
-1.0
6
6.8 8
-0.3
30
75
Unit
V
µA
ON
Symbol Parameter Test Conditions Min Typ Max Unit
R
DS(on)
Static Drain-source On
Resistance
=5V; ID=1.5A; Tj=25°C
V
IN
V
=5V; ID=1.5A
IN
120
240
mΩ
3/21
1
VNN3NV04 / VNS3NV04 / VND3NV04 / VND3NV04-1
ELECTRICAL CHARACTERISTICS (continued) (Tj=25°C, unless otherwise specified)
DYNAMIC
Symbol Parameter Test Conditions Min Typ Max Unit
gfs (*)
C
OSS
SWITCHING
Symbol Parame ter Test Conditions Min Typ M ax Unit
t
d(on)
t
t
d(off)
t
t
d(on)
t
t
d(off)
t
(dI/dt)
Q
Forward
Transconductanc e
VDD=13V; ID=1.5A 5.0 S
Output Capacitance VDS=13V; f=1MHz; VIN=0V 150 pF
Turn-on Delay Time
Rise Time 250 750 ns
r
Turn-off Delay Time 450 1350 ns
Fall Time 250 750 ns
f
Turn-on Delay Time
Rise Time 2.5 7.5 µs
r
Turn-off Delay Time 3.3 10.0 µs
Fall Time 2.0 6.0 µs
f
Turn-on Current Slope
on
Total Input Charge
i
=15V; ID=1.5A
V
DD
V
=5V; R
gen
gen=RIN MIN
(see figure 1)
=15V; ID=1.5A
V
DD
V
gen
=5V; R
=2.2 KΩ
gen
(see figure 1)
=15V; ID=1.5A
V
DD
V
=5V; R
V
I
gen
DD
gen
gen=RIN MIN
=12V; ID=1.5A; VIN=5V
=2.13m A (see figure 5)
=220Ω
=220Ω
90 300 ns
0.45 1.35 µs
4.7 A/µs
8.5 nC
SOURCE DRAIN DIODE
Symbol Param eter Test Conditions Min Typ Max Unit
(*) Forward On Vol tage ISD=1.5A; VIN=0V 0.8 V
V
SD
Q
I
RRM
t
Reverse Recovery Time ISD=1.5A; dI/dt=12A/µs
rr
Reverse Recovery Charge 37 µC
rr
Reverse Recovery Current 0.7 A
V
=30V; L= 20 0 µ H
DD
(see test circuit, figure 2)
107 ns
PROTECTIONS (-40°C < Tj < 150°C, unless otherwise specified)
Symbol Param eter Test Conditions Min Typ Max Unit
I
lim
t
dlim
T
T
I
E
(*) Pulsed: Pu ls e duration = 300µs, duty c y c le 1.5%
Drain Current Limit VIN=5V; VDS=13V 3.5 5 7 A
=5V; VDS=13V
Step Response Current
Limit
Overtemperature
jsh
Shutdown
Overtemperature Reset 135 °C
jrs
Fault Sink Current VIN=5V; VDS=13V; Tj=T
gf
Sing l e Pu lse
as
Avala nche Energy
V
IN
starti ng T
V
IN
=25°C; VDD=24V
j
=5V R
gen=RIN MIN
(see figures 3 & 4)
jsh
=220Ω; L=24mH
10 µs
150 175 200 °C
10 15 20 mA
100 mJ
4/21
2
VNN3NV04 / VNS3NV04 / VND3NV04 / VND3NV04-1
PROTECTION FEATURES
During normal operation, the INPUT pin is
electrically connected to the gate of the internal
power MOSFET through a low impedance path.
The device then behaves like a standard power
MOSFET and can be used as a switch from DC up
to 50KHz. The only difference from the user’s
standpoint is that a small DC current I
100µA) flows into the INPUT pin in order to supply
ISS
(typ.
the internal circuitry.
The de vice integrates:
- OVERVOLTAGE CLAMP PROTECTION:
internally set at 45V, along with the rugged
avalanche characteristics o f the Power MOSFET
stage giv e this device unrivall ed ruggedne ss and
energy handl ing capability. This feat ure is mainly
important when driving inductive loads.
- LINEAR CURRENT LIMITER CIRCUIT:
limits the drain current ID to I
INPUT pin voltages. When the current limiter is
whatever the
lim
active, the device operates in the linear region, so
power dissipation may exceed the capability of the
heatsink. Both case and junction temperatures
increase, and if this phase lasts long enough,
junction temperature may reach the
overtemperature threshold T
jsh
.
- OVERTEMPERATURE AND SHORT CIRCUIT
PROTECTION:
these are based on sensing the chip t emperatur e
and are not dependen t on the input voltage. The
location o f t he s ensing el emen t on the c h ip i n t he
power stage area ensures fast, accurate detection
of the junction temperature. Overtemperature
cutout occurs in the range 150 to 190 °C, a typical
value being 170 °C. The device is auto matically
restarted when the chip temp eratu re fall s of about
15°C below shut-down temperature.
- STATUS FEEDBACK:
in the case of an overtem perature fault cond ition
(Tj > T
current Igf through the INPUT pin in order to
), the device tries to sink a diagnostic
jsh
indicate fault condition. If driven from a low
impedance source, this current may be used in
order to warn the control circuit of a device
shutdown. If the drive imped ance is high enough
so that the INPUT p in dri ver is no t abl e to su pply
the current Igf, the INPUT pin will fall to 0V. This
will not however affect the device operation:
no requirement is put on the current capability
of the INPUT pin driver except to be able to
supply the normal operation drive current I
ISS
Additional features of this device are ESD
protection according to the Human Body model
and the ability to be driven from a TTL Logic
circuit.
.
5/21
VNN3NV04 / VNS3NV04 / VND3NV04 / VND3NV04-1
Fig.1: Switching Time Test Circuit for Resistive Load
V
gen
I
D
90%
V
D
R
gen
t
r
t
V
gen
d(on) t
Fig.2: Test Circuit for Diode Recovery Times
A
D
I
OMNIFET
S
220Ω
B
10%
R
gen
FAST
DIODE
d(off)
I
t
f
A
B
OMNIFET
L=100uH
D
t
t
V
DD
6/21
1
V
gen
S
8.5 Ω
VNN3NV04 / VNS3NV04 / VND3NV04 / VND3NV04-1
Thermal Impedance for DPAK/IPAK Thermal Impedance for SOT-223
7/21
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