SGS Thomson Microelectronics VNW35NV04, VNV35NV04, VNP35NV04, VNB35NV04 Datasheet
®
VNB35NV04 / VNP35NV04
/ VNV35NV04 / VNW35NV04
“OMNIFET II”:
FULLY AUTOPROTECTED POW ER M OSFET
TYPE R
DS(on)
I
lim
V
clamp
VNB35NV04
VNP35NV04
VNV35NV04
10 mΩ (*) 30 A 40 V
VNW35NV04
(*) For PowerSO-10 only
n
LINEAR CURRENT LIMITATION
n
THERMAL SHUT DOWN
n
SHORT CIRCUIT PROTECTION
n
INTEGRATED CLAMP
n
LOW CURRENT DRAWN FRO M INPUT PIN
n
DIAGNOSTIC FEEDBACK THROUGH INPUT
PIN
n
ESD PROTECTION
n
DIRECT ACCESS TO THE GATE OF THE
POWER MOSFET (ANALOG DRIVING)
n
COMPATIBLE WITH STANDARD POWER
MOSFET
DESCRIPTION
The VNB35NV04, VNP35NV04, VNV35NV04,
VNW35NV04 are mono lithic devices desig ned in
STMicroelectronics VIPower M0-3 Technology,
BLOCK DIAGRAM
10
D2PAK
TO-220
3
1
PowerSO-10
3
2
1
TO-247
1
™
3
2
1
ORDER CODES:
2
PAK
D
VNB35NV04
TO-220 VNP35NV04
PowerSO-10
™
VNV35NV04
TO-247 VNW35NV04
intended for replacement of standard Power
MOSFETS from DC up to 25KHz applications.
Built in thermal shutdown, l inear curre nt limitation
and overvoltage clamp protect the chip in harsh
environments. F ault f eedba c k can b e detected by
monitoring the voltage at the input pin.
DRAIN
2
Overvoltage
Clamp
INPUT
1
Gate
Control
Linear
Over
T emperature
Current
Limiter
3
SOURCE
FC01000
July 2003 1/19
VNB35NV04 / VNP35NV04 / VNV35NV04 / VNW35NV04
ABSOLUTE MAXIMUM RATI NG
Symbol Parameter
V
R
IN MIN
V
V
T
V
ESD1
ESD2
P
Drain-source Voltage (VIN=0V) Internally Clamped V
DS
Input Voltage Internally Clamped V
IN
Input Current +/-20 mA
I
IN
Minim um Input Series Impe dance 4.7 Ω
Drain Current Internally Limited A
I
D
Reverse DC Output Current -30 A
I
R
Electrostatic Di scharge (R=1 . 5 K Ω, C=100pF) 4000 V
Electrostatic Discharge on output pin only
(R=330Ω, C=150pF)
Total Dissipation at Tc=25°C 125 125 125 208 W
tot
Opera ting Junct ion Temp erature Internal ly limi ted °C
T
j
Case Operating Temperature Internally limited °C
T
c
Storage Temper ature -55 to 150 °C
stg
CONNECTION DIAGRAM (TO P VI EW)
PowerSO-10
™ D
Value Unit
2
PAK TO-220 TO-247
16500 V
INPUT
INPUT
INPUT
INPUT
INPUT
6
7
8
9
10
11
DRAIN
(*) For the pins configuration related to TO-220, TO-247, D2PAK, see outlines at page 1.
CURRENT AND VOLTAGE CONVENTION S
R
I
IN
IN
INPUT
5
4
3
2
1
DRAIN
SOURCE
SOURCE
SOURCE
N.C.
SOURCE
SOURCE
I
D
V
DS
2/19
V
IN
VNB35NV04 / VNP35NV04 / VNV35NV04 / VNW35NV04
THERMAL DATA
Symbol Parameter
R
thj-case
R
thj-amb
(*) When mounted on a s tandard single - s ided FR4 board with 50mm
Thermal R esistanc e Junction-case }}} MAX 1 1 1 0.6 °C/W
Thermal Resistance Junction-ambient MAX 50(*) 50(*) 50 30 °C/W
PowerSO-10
2
of Cu (at leas t 35 µm thick) connected to all DRAIN pins.
ELECTRICAL CHARACTERISTICS (-40°C < Tj < 150°C, unless otherwise specified)
OFF
Symbol Parameter Te st Conditions Min Typ Max Unit
V
CLAMP
V
CLTH
V
I
V
I
DSS
INTH
ISS
INCL
Drain-source Clamp
Voltage
Drain-source Clamp
Threshold Voltage
Input Thre shold Vol tage VDS=VIN; ID=1mA 0.5 2.5 V
Supply Current from Input
Pin
Input-Source Clamp
Voltage
Zero Input Voltage Dr ain
Current (VIN=0V)
V
=0V; ID=15A 40 45 55 V
IN
VIN=0V; ID=2mA 36 V
=0V; VIN=5V 100 150 µA
V
DS
IIN=1mA
I
=-1mA
IN
V
=13V; VIN=0V; Tj=25°C
DS
V
=25V; VIN=0V
DS
Value
™ D2PAK TO-220 TO-247
6
-1.0
6.8 8
-0.3
30
75
Unit
V
µA
ON
Symbol Parameter Test Conditions
V
R
DS(on)
Static Drain-sour ce On
Resistance
=5V; ID=15A; Tj=25°C
IN
V
=5V; ID=15A; Tj=150°C
IN
PowerSO-10
10
20
Max
2
D
PAK
TO-220 / TO-247
13
24
Unit
mΩ
3/19
1
VNB35NV04 / VNP35NV04 / VNV35NV04 / VNW35NV04
ELECTRICAL CHARACTERISTICS (continued) (Tj=25°C, unless otherwise specified)
DYNAMIC
Symbol Pa rameter Test Condit ions Min Typ Max Unit
gfs (*)
C
OSS
SWITCHING
Symbol Parame ter Tes t Conditions Min Typ Max Unit
t
d(on)
t
t
d(off)
t
t
d(on)
t
t
d(off)
t
(di/dt)
Q
Forward
Transconductance
VDD=13V; ID=15A 35 S
Output Capacitance VDS=13V; f=1MHz; VIN=0V 1300 pF
Turn-on Delay Time
Rise Time 840 2500 ns
r
Turn-off Delay Time 980 3000 ns
Fall Time 600 1500 ns
f
Turn-on Delay Time
Rise Time 27 100 µs
r
Turn-off Delay Time 34 120 µs
Fall Time 31 110 µs
f
Turn-on Current Slope
on
Total Input Charge
i
=15V; ID=15A
V
DD
V
=5V; R
gen
gen=RIN MIN
(see figure 1)
=15V; ID=15A
V
DD
V
gen
=5V; R
gen
=2.2K Ω
(see figure 1)
=15V; ID=15A
V
DD
V
=5V; R
V
I
gen
DD
gen
gen=RIN MIN
=12V; ID=15A; VIN=5V
=2.13mA (see figure 5)
=4.7Ω
=4.7Ω
150 500 ns
412µs
18 A/µs
118 nC
SOURCE DRAIN DIODE
Symbol Param eter Test Condit ions Min Typ Max Unit
(*) Forward On Voltag e ISD=15A; VIN=0V 0.8 V
V
SD
Q
I
RRM
t
Reverse Recovery Time ISD=15A; dI/dt=100 A /µs
rr
Reverse Recovery Charge 1.4 µC
rr
Reverse Recovery Current 7 A
V
=30V; L= 20 0 µ H
DD
(see test circuit, figure 2)
400 ns
PROTECTIONS (-40°C < Tj < 150°C, unless otherwise specified)
Symbol Param eter Test Condit ions Min Typ Max Unit
I
lim
t
dlim
T
T
I
E
(*) Pulsed: Pu ls e duration = 300 µ s , duty cycle 1.5%
Drain Current Limit VIN=6V; VDS=13V 30 45 60 A
=6V; VDS=13V
Step Response Curre nt
Limit
Overtemperature
jsh
Shutdown
Overtemperature Reset 135 °C
jrs
Fault Sink Current VIN=5V; VDS=13V; Tj=T
gf
Sing l e Pu lse
as
Avala nche Ener gy
V
IN
starti ng T
V
IN
=25°C; VDD=24V
j
=5V; R
gen=RIN MIN
(see figures 3 & 4)
jsh
=4.7Ω; L=24mH
50 µs
150 175 200 °C
10 15 20 mA
1.7 J
4/19
2
VNB35NV04 / VNP35NV04 / VNV35NV04 / VNW35NV04
PROTECTION FEATURES
During normal operation, the INPUT pin is
electrically connected to the gate of the internal
power MOSFET through a low impedance path.
The device then behaves like a standard power
MOSFET and can be used as a switch from DC up
to 25KHz. The only difference from the user’s
standpoint is that a small DC current I
100µA) flows into the INPUT pin in order to supply
ISS
(typ.
the internal circuitry.
The de vice integrates:
- OVERVOLTAGE CLAMP PROTECTI ON:
internally set at 45V, along with the rugged
avalanche characteristics o f the Power MOSFET
stage giv e this device unrivall ed ruggedne ss and
energy handl ing capability. This feat ure is mainly
important when driving inductive loads.
- LINEAR CURRENT LIMITER CIRCUIT:
limits the drain current ID to I
INPUT pin voltage s is. When the curr ent limiter is
whatever the
lim
active, the device operates in the linear region, so
power dissipation may exceed the capability of the
heatsink. Both case and junction temperatures
increase, and if this phase lasts long enough,
junction temperature may reach the
overtemperature threshold T
jsh
.
- OVERTEMPERATURE AND SHORT CIRCUIT
PROTECTION:
these are based on sensing the chip t emperatur e
and are not dependen t on the input voltage. The
location o f t he s ensing el emen t on the c h ip i n t he
power stage area ensures fast, accurate detection
of the junction temperature. Overtemperature
cutout occurs in the range 150 to 190 °C, a typical
value being 170 °C. The device is automatically
restarted when the chip temp eratu re fall s of about
15°C below shut-down temperature.
- STATUS FEEDBACK:
in the case of an overtem perature fault cond ition
(Tj > T
current Igf through the INPUT pin in order to
), the device tries to sink a diagnostic
jsh
indicate fault condition. If driven from a low
impedance source, this current may be used in
order to warn the control circuit of a device
shutdown. If the drive imped ance is high enough
so that the INPUT p in dri ver is no t abl e to su pply
the current Igf, the INPUT pin will fall to 0V. This
will not however affect the device operation:
no requirement is put on the current capability
of the INPUT pin driver except to be able to
supply the normal operation drive current I
ISS
Additional features of this device are ESD
protection according to the Human Body model
and the ability to be driven from a TTL Logic
circuit.
.
5/19
VNB35NV04 / VNP35NV04 / VNV35NV04 / VNW35NV04
Fig.1: Switching Time Test Circuit for Resistive L oad
V
R
gen
V
gen
I
D
90%
D
t
r
t
V
gen
d(on) t
Fig.2: Test Circuit for Diode Recovery Times
D
I
OMNIFET
S
25 Ω
B
10%
A
R
FAST
DIODE
gen
d(off)
I
OMNIFET
t
f
t
t
A
L=100uH
B
D
V
DD
6/19
V
gen
S
8.5 Ω
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