The VN920D-B5, VN920DSO are monolithic
devices made by usingSTMicroelectronics
VIPower M0-3 Technology, intended for driving
any kind of load with one side connected to
ground. Active VCC pin voltage clamp protects the
(*) When mounted on a standard single-sided FR-4 board with 0.5cm2 of Cu (at leas t 35µ m t hick) .
(**) When mounted on FR4 printed circuit board with 0.5cm
Thermal Resistanc e Junctio n-case Max1.3-°C/W
Thermal R esistanc e Junction-lead Max-15°C/W
Thermal R esistanc e Junction-ambientMax51.3 (*)65 (**)°C/W
2
of Cu (at leas t 35µ thick) connected to all VCC pins.
CAll functions of the device are performe d as designed after exposure to disturbance.
EOne or more function s of the dev ice is not p erformed as design ed after ex posure to disturbance
and canno t be retur ned to proper operation without repla cing the device.
IIIIIIIVDelays and
IIIIIIIV
TEST LEVELS
TEST LEVEL S RESULTS
Impedance
Ω
Ω
6/22
Figure1: Waveforms
INPUT
LOAD VOLTAGE
STATUS
V
CC
INPUT
LOAD VOLTAGE
STATUS
V
CC
INPUT
LOAD VOLTAGE
STATUS
NORMAL OPERATION
UNDERVOLTAGE
V
USD
OVERVOLTAGE
V
CC<VOV
V
USDhyst
undefined
VCC>V
VN920D-B5 / VN920DSO
OV
INPUT
LOAD VOLTAGE
STATUS
INPUT
LOAD VOLTAGE
STATUS
T
j
INPUT
LOAD CURRENT
STATUS
OPEN LOAD wi th external pull-up
V
OUT>VOL
V
OL
OPEN LOAD without external pull-up
T
TSD
T
R
OVERTEMPERATURE
7/22
VN920D-B5 / VN920DSO
APPLICATION SCHEMATIC
+5V
µ
R
C
R
prot
prot
+5V
STA T US
INPUT
GND PROTECTION NETWORK AGAINST
REVERSE BATTERY
Soluti on 1: Resistor in the ground line (R
can be us ed with any t ype of load.
The fo llowin g is an indica tion on how to dim ension the
resistor.
R
GND
1) R
2) R
where -I
be foun d in the abs olute max i mum rating se ct i on of the of
≤ 600mV / (I
GND
≥ (−VCC) / (-I
GND
is the DC re vers e grou nd pi n cu rren t an d can
GND
S(on)ma x
)
GND
).
the devic e’s datasheet.
Power Dissipation in R
battery situations) is:
= (-VCC)2/R
P
D
GND
(when VCC<0: during reverse
GND
This resistor can be shared amongst several different
HSD. Please note that the value of this resistor should be
calcul ated with form ula (1) wher e I
sum of the maximum on-state currents of the different
S(on)max
devices.
Please note that if the microprocessor ground is not
common with the device ground then the R
produce a shift (I
and the status output values. This shift will vary
S(on)max
* R
) in the input thresholds
GND
depending on many devices are ON in the case of several
high side drivers sharing the same R
GND
If the calculated power dissipation leads to a large resistor
or several devices hav e to share the sa me resisto r then
the ST suggest to utilize Solution 2 (see below).
Solution 2:
A resistor (R
D
GND
A diode (D
=1kΩ) sh ould b e insert ed in paral lel to
GND
if the device will be driving an inductive load.
) in the gr ound line.
GND
only). This
GND
becomes t he
GND
.
will
V
CC
D
OUTPUT
GND
R
V
GND
GND
D
GND
This small signal diode can be safely shared amongst
several different HSD. Also in this case, the presence of
j
the ground network wi ll produce a shift (
600mV) in t he
input threshold and the status output values if the
microprocessor ground is not common with the device
ground. This shift will not vary if more than one HSD
shares the same diode/resi stor net work.
LOAD DUMP PROTECTION
Dld is necessary (Voltage Transient Suppressor) if the
load dump peak voltage exceeds VCC max DC rating. The
same applies if the device will be subject to transients on
the VCC line that are grea ter tha n the ones sh own in the
ISO T/R 7637/1 table.
C I/Os PROTECTION:
µ
If a ground protection network is used and negative
transient are p resent on the VCC line, the control pins will
be pulled negative. ST suggests to insert a resistor (R
in lin e to prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between the
leakage c urrent of µC an d the current required by the
HSD I/Os ( Input le vels comp atibilit y) wi th the lat ch-up li mit
of µC I/Os.
≤ R
-V
CCpeak/Ilatchup
Calculation example:
CCpeak
prot
= - 100V an d I
≤ 65kΩ.
prot
For V
5kΩ≤ R
Recommended R
≤ (V
prot
OHµC-VIH-VGND
≥ 20mA; V
latchup
value is 10kΩ.
) / I
OHµC
ld
IHmax
≥ 4.5V
prot
)
8/22
1
VN920D-B5 / VN920DSO
Off State Output Current
IL(off1) (u A)
9
8
7
6
5
4
3
2
1
0
-50 -250255075100 125 150 17 5
Tc (°C)
Input Clamp Voltage
Vicl (V)
8
7.8
7.6
7.4
7.2
7
6.8
6.6
6.4
6.2
6
Iin=1mA
-50 -250255075 100 125 150 175
Tc (°C)
High Level Input Current
Iih (uA)
5
4.5
3.5
2.5
1.5
0.5
Vin=3.25V
4
3
2
1
0
-50 -250255075 100 125 150 175
Input High Level
Vih (V)
3.6
3.4
3.2
3
2.8
2.6
2.4
2.2
2
-50 -250255075 100 125 150 175
Input Hysteresis VoltageInput Low Level
Tc (°C)
Tc (°C)
Vil (V)
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
-50 -250255075 100 125 150 175
Tc (°C)
Vhyst (V)
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
-50 -250255075 100 125 150 175
Tc (°C)
9/22
11
VN920D-B5 / VN920DSO
Overvoltage Shutdown
I
LIM
Vs. T
case
Vov (V)
50
48
46
44
42
40
38
36
34
32
30
-50 -250255075 100 125 150 175
Ilim (A)
100
90
80
70
60
50
40
30
20
10
Vcc=13V
0
-50 -250255075 100 125 150 175
Tc (°C)
Turn-on Voltage SlopeTurn-off Voltage Slope
dVout/dt(on) (V/ms)
700
650
600
550
500
450
400
350
300
250
-50 -250255075 100 125 150 175
Vcc=13V
Rl=1.3Ohm
Tc (ºC)
dVout/dt(off) (V/ms)
550
500
450
400
350
300
250
200
150
100
50
Vcc=13V
Rl=1.3Ohm
0
-50 -250255075 100 125 150 175
Tc (ºC)
Tc (°C)
On State Resistance Vs. T
case
Ron (mOhm)
50
45
40
35
30
25
20
15
10
5
0
-50 -250255075 100 125 150 175
Iout=10A
Vcc=8V; 36V
Tc (ºC)
10/22
On State Resistance Vs. V
CC
Ron (mOhm)
50
45
40
35
30
25
20
15
10
5
0
5 10152025303540
Iout=10A
Tc=150ºC
Tc=25ºC
Tc= -40ºC
Vcc (V)
VN920D-B5 / VN920DSO
Status Leakage Current
Ilstat(µA)
0.05
0.045
0.04
0.035
0.03
0.025
0.02
0.015
0.01
0.005
Vstat=5V
0
-50 -25025 5075 100 125 150 175
Tc (ºC )
Status Low Output Voltage
Vstat (V)
0.8
0.7
0.6
0.5
Istat=1.6mA
Status Clamp Voltage
Vscl (V)
8
7.8
7.6
7.4
7.2
6.8
6.6
6.4
6.2
Istat=1mA
7
6
-50 -250255075 100 125 150 175
Tc (ºC)
0.4
0.3
0.2
0.1
0
-50 -250255075 100 125 150 175
Tc (ºC)
11/22
VN920D-B5 / VN920DSO
P2PAK Maximum turn off current versus load inductance
LMAX (A)
I
100
10
1
A
B
C
0.010.1110100
A = Single Pulse at T
B= Repetitive pulse at T
C= Repetitive Pulse at T
Conditions:
VCC=13.5V
Values are generated with RL=0Ω
In case of repetitive pulses, T
the temperature specified above for curves B and C.
VIN, I
L
=150ºC
Jstart
=100ºC
Jstart
=125ºC
Jstart
jstart
Demagnetization
(at beginning of each demagnetization) of every pulse must not exceed
L(mH)
Demagnetization
Demagnetization
12/22
t
SO-16L Maximum turn off current versus load inductance
LMAX (A)
I
100
10
C
VN920D-B5 / VN920DSO
A
B
1
0.010.1110100
A = Single Pulse at T
B= Repetitive pulse at T
C= Repetitive Pulse at T
Conditions:
VCC=13.5V
Values are generated with RL=0Ω
In case of repetitive pulses, T
the temperature specified above for curves B and C.
VIN, I
L
=150ºC
Jstart
=100ºC
Jstart
=125ºC
Jstart
jstart
Demagnetization
(at beginning of each demagnetization) of every pulse must not exceed
L(mH)
Demagnetization
Demagnetization
t
13/22
VN920D-B5 / VN920DSO
P2PAK PC Board
P2PAK THERMAL DATA
R
thj-amb
Layout conditio n of Rth and Zth measurements (PCB F R4 area= 60mm x 60mm, PCB thi ckness=2mm,
Cu thickness=35µm, Copper areas: 0.97cm
Vs. PCB copper area in open box free air condition
RTHj_amb (°C/W)
2
, 8cm2).
55
Tj-Tamb=50°C
50
45
40
35
14/22
30
0246810
PCB Cu heatsink area (cm^2)
SO-16L PC Board
VN920D-B5 / VN920DSO
SO-16L THERMAL DATA
R
thj-amb
Layout conditio n of Rth and Zth measur ements (P CB FR4 area= 41mm x 48mm , PCB thickness=2mm,
Cu thickness=35µm, Copper areas: 0.5cm
Vs. PCB copper area in open box free air condition
RTH j-amb (°C/W)
70
2
, 6cm2).
65
60
55
50
45
40
01234567
PCB Cu heatsink area ( cm ^2)
15/22
VN920D-B5 / VN920DSO
SO-16L Thermal Impedance Junction Ambient Single Pulse
ZTH (°C/W)
100
10
1
0.1
0.01
0.00010.0010.010.11101001000
Time (s )
Thermal fitting model of a single channel HSD
in SO-16L
Information furnished is believed to be accurate and reliable. Ho wev er, STMicroelectr onics assumes no r es ponsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is
granted by implication or otherwise under any patent or patent r ights of STMicr oelectronics . Specifications mentioned in this publication are
subject to c hange withou t notice. This publicatio n s upersedes an d r eplaces all information p r ev iously supplied. STMic r oelectroni c s pr oducts
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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The ST logo is a trademark of ST M ic r oelectronic s
2003 STMicroelectronics - Printed in ITALY- All Rights Reserved.
STMicroelectronics GROUP OF COMPANIES
http://www.st.com
22/22
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