VI Per 5 0/ SP620V1.5 A5 Ω
VI Per 5 0A /ASP700V1.5 A5.7 Ω
FEATURE
■ ADJUSTABLESWITCHING FREQUENCY UP
TO200KHZ
■ CURRENT MODE CONTROL
■ SOFTSTART ANDSHUT DOWN CONTROL
■ AUTOMATIC BURST MODE OPERATION IN
STAND-BY CONDITION ABLE TO MEET
”BLUE ANGEL” NORM(<1W TOTAL POWER
CONSUMPTION)
■ INTERNALLY TRIMMED ZENER
REFERENCE
■ UNDERVOLTAGE LOCK-OUT WITH
HYSTERESIS
■ INTEGRATED START-UPSUPPLY
■ AVALANCHERUGGED
■ OVERTEMPERATURE PROTECTION
■ LOW STAND-BYCURRENT
■ ADJUSTABLECURRENTLIMITATION
BLOCK DIAGRAM
VIPer50A/ASP
SMPS PRIMARY I.C.
10
PENTAWATTHVPENTAWATT HV
PowerSO-10
DESCRIPTION
VIPer50/50AmakeusingVIPowerM0
Technology combines on the same silicon chip a
state-of-the-art PWM circuit together with an
optimized high voltage avalancherugged Vertical
Power MOSFET (620Vor 700V / 1.5A).
Typical applications cover off line power supplies
with a secondary power capabilityof 25W in wide
range condition and 50W in single range or with
doubler configuration. It is compatible from both
primary or secondary regulation loop despite
using around 50% less components when
compared with a discrete solution. Burst mode
operation is an additional feature of this device,
offering the possibility to operate in stand-by
mode withoutextra components.
1
(022Y)
May 1999
_
2 V/A
CURRENT
AMPLIFIER
DRAIN
SOURCE
1
9
2
0
0
C
F
OSC
ON/OFF
SECURITY
LATCH
FF
R/SSQ
OVERTEMP.
DETECTOR
1.7µs
DELAY
ERROR
AMPLIFIER_
LOGIC
0.5 V
UVLO
+
_
4.5 V
VDD
13 V
+
OSCILLATOR
PWM
LATCH
S
R1
FF
R2 R3
COMP
Q
250 ns
BLANKING
0.5V
+
+
_
1/20
VIPer50/SP - VIPer50A/ASP
ABSOLUTEMAXIMUMRATING
Symb o lPara met erVal u eUni t
V
I
V
V
OSC
V
COMP
I
COMP
V
I
D(AR)
P
T
T
THERMALDATA
R
thj-case
R
thj-a mb.
(*) When mounted using the minimum recommended pad size on FR-4 board.
Continuous Drain- Sour ce Volta ge (Tj = 25 t o 125oC)
DS
for VIPer50/S P
for VIPer50A/ ASP
Maximum CurrentInte rnally Li mitedA
D
Supply Volt age0 to 15V
DD
Volt age Range Input0 t o V
-0.3 to 620
-0.3 to 700
DD
Volt age Range Input0 t o 5V
Maximum Continuous Cur rent±2mA
Elect r o st at ic discharge (R = 1.5 KΩ C = 100pF)4000V
esd
Avalanche Drain-Source Curre nt , Repetitive or N ot -Repet it ive
(T C = 100
for VIPer50/S P
for VIPer50A/ ASP
Power Dissipation at Tc = 25oC60W
tot
Junction Operatin g TemperatureInt ernally Limited
j
St orage T emperature-65 to 150
stg
o
C, Pulse Width Limited by TJmax, δ <1%)
1.5
1
PENTAWATT-HV PowerSO-10(*)
Ther mal Res istan ce Junc ti on-c aseMax1.91.9
Ther mal Res istan ce Ambient-caseMax6050
o
o
o
C/W
o
C/W
V
V
V
A
A
C
C
CONNECTION DIAGRAMS (Top View)
PENTAWATTHVPENTAWATTHV (022Y)PowerSO-10
CURRENT AND VOLTAGE CONVENTIONS
IDDID
OSC
I
OSC
DD
V
13V
OSC
V
+
ICOMP
VCOMP
DRAINVDD
COMP SOURCE
VDS
2/20
FC00020
ORDERING NUMBERS
PENTAWATT HVPENT AWATT HV (022Y)PowerSO - 10
VIPer50
VIPer50A
VIPer50 ( 022Y)
VI Per50A (022Y)
VIPer50/SP - VIPer50A/ASP
VIP er 50SP
VIPer50ASP
PINSFUNCTIONAL DESCRIPTION
DRAINPIN:
Integrated power MOSFET drain pin. It provides
internal bias current during start-up via an
integrated high voltage current source which is
switched off during normal operation. The device
is able to handle an unclamped current during its
normal operation, assuring self protection against
voltage surges, PCB stray inductance, and
allowing a snubberless operation for low output
power.
SOURCEPIN:
Power MOSFET source pin. Primary side circuit
commonground connection.
VDD PIN :
This pin provides two functions:
- It corresponds to the low voltage supply of the
controlpart of the circuit. If V
the start-up current source is activated and the
output power MOSFET is switched off untilthe
V
voltage reaches 11V. During this phase,
DD
the internal current consumption is reduced,
the V
pin is sourcing a currentof about 2mA
DD
and the COMP pin is shorted to ground. After
that, the current source is shut down, and the
devicetries to start upby switchingagain.
goes below 8V,
DD
- This pin is also connected to the error
amplifier, in order to allow primary as well as
secondary regulation configurations.In case of
primary regulation, an internal 13V trimmed
reference voltage is used to maintain V
13V. For secondary regulation, a voltage
between 8.5V and 12.5V will be puton V
by transformer design, in order to stuck the
output of the transconductanceamplifier to the
high state. The COMP pin behaves as a
DD
DD
at
pin
constant current source, and can easily be
connected to the output of an optocoupler.
Note that any overvoltage due to regulation
loop failure is still detected by the error
amplifier through the V
voltage, which
DD
cannot overpass 13V. The output voltage will
be somewhathigher than the nominalone, but
still undercontrol.
COMP PIN :
This pin providestwo functions :
- It is the output of the error transconductance
amplifier, and allows for the connection of a
compensation network to provide the desired
transfer function of the regulation loop. Its
bandwidth can be easily adjusted to the
needed value with usual componentsvalue. As
statedabove,secondaryregulation
configurations are also implemented through
the COMPpin.
- When the COMP voltage is going below 0.5V,
the shut-downof thecircuit occurs, with a zero
duty cycle for thepower MOSFET. This feature
can be used to switchoff the converter, and is
automatically activated by the regulation loop
(whatever is the configuration) to provide a
burst mode operation in case of negligible
output power or open load condition.
OSC PIN :
An R
to define the switching frequency. Note that
despite the connection of R
significant frequency change occurs for V
varying from 8V to 15V. It provides also a
synchronisationcapability, when connected to an
external frequency source.
Symb o lParamet erTest Con d it i onsMin.Typ .Max.Unit
BV
I
DSS
R
DS(on)
C
OSS
(1) OnInductive Load, Clamped.
Avalanche Current, Repetitive or Not-Repet it ive
(pulse widt h limited by T
for VIPer50/S P
for VIPer50A/ ASP(see f ig. 12)
Single Pulse Avalanche Ener g y
(ar)
(starti ng T
Drain-Source VoltageID=1mAV
DSS
=25oC, ID=I
j
Of f - State Dra in Curr entV
St at ic Drain Source on
Resistance
max, δ <1%)
j
)(see fig. 12)
D(ar)
COMP
for VIPer50/SP
for VIPer50A/ASP(see fig. 5)
=0V TJ=125oC
COMP
V
= 620 Vfor VI P er5 0/ SP
DS
= 700 Vfor VI P er5 0A/AS P
V
DS
ID=1A
for VIPer50/SP
for VIPer50A/ASP
=1ATJ= 100oC
I
D
1.5
1.0
30mJ
=0V
620
700
4.0
4.6
for VIPer50/SP
for VIPer50A/ASP
t
Fall TimeID = 0.2 AVin= 300 V (1)
f
100ns
(see f ig. 3)
Rise TimeID=1AVin= 300 V (1)
t
r
50ns
(see f ig. 3)
Out put CapacitanceVDS= 25 V120pF
1
1
5.0
5.7
9.0
10.3
A
A
V
V
mA
mA
Ω
Ω
Ω
Ω
SUPPLY SECTION
Symb o lParamet erTest Con d it i onsMin.Typ .Max.Unit
4/20
I
DDch
I
DD0
I
DD1
I
DD2
V
DDo f f
V
DDo n
V
DDhyst
St art - u p Charging
Current
Oper at i ng Supply Current VDD=12V, FSW=0KHz
VDD=5VVDS=70V
(see fig. 2 and fig . 15)
-2mA
1216mA
(see f ig. 2)
Oper at i ng Supply Current VDD=12V, FSW= 100 KHz14mA
Oper at i ng Supply Current VDD=12V, FSW= 200 KHz16mA
Undervoltage S hutdown(see fig. 2)8V
Undervoltage Reset(see fig. 2)1112V
Hysteresis Start-up(see f ig. 2)2.43V