SGS Thomson Microelectronics VIPER20BSP, VIPER20B Datasheet

VIPer20B



TYPE V

DSS

I

R

n

DS(on)

VIPer20B/SP 400V 1.3 A 8.7 Ω

FEATURE

■ ADJUSTABLESWITCHINGFREQUENCYUP

TO200KHZ

■ CURRENT MODE CONTROL

■ SOFTSTART AND SHUT DOWN CONTROL

■ AUTOMATIC BURST MODE OPERATION IN

STAND-BY CONDITIONABLE TO MEET
”BLUE ANGEL” NORM (1W TOTAL POWER
CONSUMPTION)

■ INTERNALLY TRIMMEDZENER

REFERENCE

■ UNDERVOLTAGE LOCK-OUT WITH

HYSTERESIS

■ INTEGRATED START-UPSUPPLY

■ AVALANCHERUGGED

■ OVERTEMPERATUREPROTECTION

■ LOW STAND-BYCURRENT

■ ADJUSTABLECURRENTLIMITATION

VIPer20BSP

SMPS PRIMARY I.C.

PRELIMINARY DATA

10

1

PENTAWATT HV Power SO-10

DESCRIPTION

VIPer20B combineson the same silicon chip a
state-of-the-art PWM circuit together with an
optimized high voltageavalanche rugged Vertical
Power MOSFET(400V 1.3A).

Typical applications cover off line power supplies
with a secondarymax power capabilityof 30W. It
is compatible from both primary or secondary
regulation loop despite using around 50% less
components when compared with a discrete
solution. Burst mode operation is an additional
feature of this device, offering the possibility to
operate in stand-by mode without extra
components.

BLOCK DIAGRAM

VDD

September 1999

13 V

_

+

ERROR

AMPLIFIER

0.5V

UVLO

LOGIC

ON/OFF

+
_

4.5V

SECURITY

LATCH

R/SSQ

OVERTEMP.

DETECTOR

2 µs

delay

OSC

OSCILLATOR

PWM

LATCH

R1

R2 R3

COMP

DRAIN

S

FFFF

Q

0.5V
_

+

+

300 ns

Blanking

6 V/A

_

CURRENT

AMPLIFIER

SOURCE

FC00490

1/17

VIPer20B / VIPer20BSP

ABSOLUTEMAXIMUM RATING

Symbol Para met e r Val u e Uni t

V

I

V

V

OSC

V

COMP

I

COMP

V

I

D(AR)

P

T

T

THERMALDATA

R

thj-case

R

thj-a mb.

Continuous Dr ain-Sour ce Voltage (Tj = 25 to 125oC) -0.3 to 400 V

DS

Maximum Current Internally Limited A

D

Supply Volt age 0 to 15 V

DD

Volt a ge Range Input 0 to V

DD

Volt a ge Range Input 0 t o 5 V
Maximum Conti nuou s C urrent ±2mA
Electrostatic d ischarge (R = 1.5 KΩ C = 100p F )

esd

Avalanche Drain-Source Current , Repetiti ve or No t-R epetitiv e

=100oC, Pulse Width Limite d by TJmax, δ <1%)

(T

C

Power Dissi pation at Tc = 25oC57W

tot

Junction Op erating Temperature -40 to 140

j

St orage Temper at u r e -65 to 150

stg

2000 V

TBD A

Ther mal Resistan c e Junction- case Ma x 2.0
Ther mal Resistan c e Junction- ambient

70

Max

o
o

o

C/W

o

C/W

V

C
C

CONNECTION DIAGRAMS (Top View)

PENTAWATT HV PowerSO-10

CURRENT AND VOLTAGE CONVENTIONS

IDD ID

IOSC

OSC

VDD

13V

VOSC

­+

ICOMP

VCOMP

DRAINVDD

COMP SOURCE

VDS

2/17

FC00020

ORDERING NUMBERS

PENTAW AT T HV PowerSO -10

VIPer 20B VIPer20BSP

VIPer20B / VIPer20BSP

PINSFUNCTIONAL DESCRIPTION
DRAINPIN:

Integrated power MOSFET drain pin. It provides
internal bias current during start-up via an
integrated high voltage current source which is
switched off during normal operation.The device
is able to handle an unclampedcurrent during its
normal operation, assuring self protectionagainst
voltage surges, PCB stray inductance, and
allowing a snubberless operation for low output
power.

SOURCEPIN:

Power MOSFET source pin. Primary side circuit
commongroundconnection.

VDD PIN :

This pin providestwo functions:

- It corresponds to the low voltage supply of the

controlpart of the circuit. If V
the start-up current source is activatedand the
output power MOSFET is switched off untilthe
V

voltage reaches 11V. During this phase,

DD

the internal current consumption is reduced,
the V

pin is sourcing a currentof about 1mA

DD

and the COMP pin is shorted to ground. After
that, the current source is shut down, and the
devicetries to startupby switching again.

goes below 8V,

DD

- Thispin isalsoconnected to the error amplifier,

in order to allow primary as well as secondary
regulation configurations. In case of primary
regulation, an internal 13V trimmed reference
voltage is used to maintain V
secondary regulation, a voltage between 8.5V
and 12.5V will be put on V
transformerdesign, in orderto stuckthe output
of the transconductance amplifier to the high
state. The COMP pin behaves as a constant

at 13V. For

DD

DD

pin by

current source, and can easily be connectedto
the output of an optocoupler. Note that any
overvoltage due toregulation loop failure is still
detected by the error amplifier through the V

DD

voltage, which cannot overpass 13V. The
output voltage will be somewhat higher than
the nominalone, but still under control.

COMP PIN :

This pin provides two functions :

- It is the output of the error transconductance

amplifier, and allows for the connection of a
compensation network to provide the desired
transfer function of the regulation loop. Its
bandwidth can be easily adjusted to the
needed value withusual componentsvalue. As
stated above, secondary regulation
configurations are also implemented through
the COMP pin.

- When the COMP voltage is going below 0.5V,

the shut-downof the circuit occurs, with a zero
duty cycle for the power MOSFET.This feature
can be used to switch off the converter, and is
automatically activated by the regulation loop
(whatever is the configuration) to provide a
burst mode operation in case of negligible
output power or openload condition.

OSC PIN :

An R
to define the switching frequency. Note that
despite the connection of R
significant frequency change occurs for V
varying from 8V to 15V. It provides also a
synchronisationcapability, when connectedto an
external frequencysource.

network must be connected on that pin

T-CT

to VDD,no

T

DD

3/17

VIPer20B / VIPer20BSP

ELECTRICAL CHARACTERISTICS (TJ=25oC, VDD=13 V, unless otherwise specified)

POWERSECTION

Symbol Parameter Test Cond itions Min. Typ. Max. Unit

BV

I

DSS

R

DS(on)

C

OSS

(1) On Inductive Load, Clamped.

SUPPLY SECTION

Symbol Parameter Test Cond itions Min. Typ. Max. Unit

I

DDch

I

DD0

I

DD1

I

DD2

V

DDo f f

V

DDo n

V

DDhyst

Drain-Sourc e V olt age ID=10mA V

DSS

= 0 V 400 V

COMP

Off -St ate Drain Current VDS=300V TJ= 125oC

=0V

V

COMP

St at i c Drain Source o n
Resistance

t

Fall Time ID=0.1A Vin=300V(1)

f

ID=0.9A

=0.9A TJ= 100oC

I

D

7.3 8.7

80 ns

(see fig. 3)

Rise Tim e ID=0.9A Vin= 3 00 V ( 1)

t

r

50 ns

(see fig. 3)

Out put C apa c itance VDS=25V 90 pF

St art-up C harging
Current

Oper ating S upp ly
Current

Oper ating S upp ly

VDD=0toV

DDo n

VDS=70V

-2 mA

(see fig. 2)
VDD=12V, FSW=0KHz

12 TBD mA

(see fig. 2)
VDD=12V, FSW=100KHz 13 mA

Current
Oper ating S upp ly

VDD=12V, FSW=200KHz 14 mA

Current
Unde rv oltage

(see fig. 2) 8 V

Shutdown
Unde rv oltage Res et ( s ee fig. 2) 11 12 V
Hyst eresis S tart-up (see fig. 2) 2.4 3 V

0.6 mA

15.7

Ω
Ω

OSCILLATORSECTION

Symbol Parameter Test Cond itions Min. Typ. Max. Unit

4/17

F

F

V

V

SW1

SW2

OSCih

OSCil

Os cillator F r equ en c y
Init ial Acc ur a c y

Os cillator F r equ en c y
Total Variation

R

T

=8.2K

Ω

CT=2.4 nF

(see fig.7)
R

T

V

DD

=8.2K

Ω

CT=2.4 nF

=9to15V TJ= 0 t o 100oC

Os cillator Pe a k V oltage 7.1 V
Os cillator Va lle y

Voltage

90 100 110 K Hz

80 100 120 K Hz

3.7 V

VIPer20B / VIPer20BSP

ELECTRICAL CHARACTERISTICS (continued)

ERRORAMPLIFIERSECTION

Symbol Parameter Test Cond itions Min. Typ. Max. Unit

V

DDreg

∆V

DDreg

G

A

VOL

G

V

COMPLO

V

COMPHI

I

COMPLO

I

COMPHI

PWM COMPARATOR SECTION

Symbol Parameter Test Cond itions Min. Typ. Max. Unit

H

V

COMPoffVCOMP

I

Dpeak

t

t

VDD Re gul at i on Point I

=0mA(seefig.1) 12.61313.4 V

COMP

Total Variation TJ= 0 to 100oC2%
Unity Gain Bandwidth F rom I nput = VDDto Output = V

BW

COMP

150 KHz

COM P pi n is open (see f ig. 8)

Open Loop Volt age

COM P pi n is open (see f ig. 8) TBD 5 0 dB

Gain
DC Tran sconduct an c e V

m

Out put L ow Level
Out put H igh Level
Out put L ow Curr ent

= 2.5 V (see fig. 1) TBD 1.5 T BD mA/V

COMP

=-400µAVDD=14V

I

COMP

=400µAVDD=12V

I

COMP

V

=2.5V VDD=14V -600 µA

COMP

0.2 V

4.5 V

Capa bility
Output High Current

V

=2.5V VDD= 1 2 V 600 µA

COMP

Capa bility

V

∆V

ID

COMP

/∆I

Dpeak

offset I

= 1 to 3 V TBD 2.3 TBD V/A

COMP

=10mA 0.5 V

Dpeak

Peak Curr ent Limitation VDD= 1 2 V COM P pin open 1.3 TBD A
Current Sense Delay

d

ID= 0. 4 A 250 ns

to turn-off
Blanking Time 300 ns

b

SHUTDOWNAND OVERTEMPERATURE SECTION

Symbol Parameter Test Cond itions Min. Typ. Max. Unit

V

COMPth

t

DISsu

T

T

hyst

Restart threshold (see fig. 4) 0.5 V
Disabl e Set Up Time (see fig. 4 ) 1. 7 5 µ s
Thermal Shutdown

tsd

(see fig. 6) 140 160

Tem p er at u re
Thermal Shutdown

(see fig. 6) 34

Hyst e r esis

o

o

C

C

5/17

VIPer20B / VIPer20BSP

Figure1:VDDRegulationPoint

COMP

I

ICOMPHI

0

ICOMPLO

VDDreg

Figure3: TransitionTime

ID

10%Ipeak

VDS

90%VD

Slope =

Gm in mA/V

FC00150

Figure2: UndervoltageLockout

IDD

IDD0

DD

V

VDDhyst

V

DDoff

IDDch

Figure4: ShutDown Action

VOSC

V

COMP

t

VCOMPth

I

D

tDISsu

VDS=70V

Fsw = 0

V

DDon

FC00170

VDD

t

t

10%V

D

tf tr

t

FC00160

ENABLE

t

ENABLE

DISABLE

FC00060

6/17

Figure5: Start-upWaveforms

VIPer20B / VIPer20BSP

Figure6: OvertemperatureProtection

Tj

Ttsd

ID

VDD

VDDon

VCOMP

Thyst

t

t

t

t

FC10192

7/17

VIPer20B / VIPer20BSP

Figure7: Oscillator

Ct

Rt

OSC

~360Ω

VDD

Dmax

0.9

0.8

0.7

For RT> 1.2 KΩ:

SW

MAX

=

= 1 −

R

2.3

TCT

R

D

MAX

550

− 150

T

MAX

values:

F

CLK

D
RecommendedD

100KHz: > 80%
200KHz: > 70%

FC00050

Maximum duty cycle vs Rt

1

FC00040

Frequency (kHz)

0.6

0.5
1 2 3 5 10 20 30 50

Rt (kΩ)

Oscillatorfrequency vs Rt and Ct

1,000

Ct =1.5nF

500

Ct =2.7 nF

300

Ct = 4.7 nF

200

Ct =10nF

100

50

30

1 2 3 5 10 20 30 50

Rt (kΩ)

FC00030FC00030

8/17

Figure8: ErrorAmplifier FrequencyResponse

60

RCOMP= +∞
RCOMP= 270k

40

RCOMP= 82k

RCOMP= 27k

VIPer20B / VIPer20BSP

FC00200

20

VoltageGain (dB)

RCOMP= 12k

0

(20)

0.001 0.01 0.1 1 10 100 1,000

Figure9: ErrorAmplifierPhase Response

200

150

Frequency (kHz)

FC00210

RCOMP= +∞
RCOMP= 270k

RCOMP= 82k

RCOMP= 27k

Phase (°)

100

50

RCOMP= 12k

0

(50)

0.001 0.01 0.1 1 10 100 1,000

Frequency (kHz)

9/17

VIPer20B / VIPer20BSP

Figure10: Off Line Power Supply WithAuxliary Supply Feedback

F1

BR1

D1

C2

C4

R1

D3

C3

R7

ACIN

TR2

C1

R9

TR1

D2

C7

C10

L2

C9

+Vcc

GND

R2

13V

­+

C11

OSC

C5

DRAINVDD

COMP SOURCE

C6

R3

Figure11: Off Line Power Supply With OptocouplerFeedback

F1

13V

BR1

­+

C2

D3

C4

COMP SOURCE

D1

R1

C3

R7

DRAINVDD

VIPer

AC I N

TR2

C1

R9

R2

OSC

C5

VIPer

TR1

FC00402

D2

C7

C10

L2

C9

+Vcc

GND

10/17

C11

C6

R3

R6

ISO1

R4

U2

C8

R5

FC00412

VIPer20B / VIPer20BSP

OPERATIONDESCRIPTION :
CURRENT MODETOPOLOGY:

The current mode control method, like the one
integrated in the VIPer20B uses two control loops

- an inner current control loop and an outer loop
for voltage control. When the Power MOSFET
output transistor is on, the inductor current
(primaryside of the transformer)is monitoredwith
a SenseFET technique and converted into a
voltage V
reaches V

proportional to this current. When V

S

COMP

(the amplified output voltage
error) the power switch is switched off. Thus, the
outer voltage control loop defines the level at
which the inner loop regulates peak current
through the power switch and theprimary winding
of the transformer.

Excellent open loop D.C. and dynamic line
regulation is ensured due to the inherent input
voltage feedforward characteristic of the current
mode control. This results in an improved line
regulation, instantaneous correction to line
changes and better stability for the voltage
regulationloop.

Current mode topology also ensures good
limitation in the case of short circuit. During a first
phase the output current increases slowly
followingthe dynamic of the regulation loop. Then
it reaches the maximum limitation current
internally set and finally stops because the power
supply on V

is no longer correct. For specific

DD

applications the maximum peak current internally
set can be overridden by externally limiting the
voltage excursion on the COMP pin. An
integrated blanking filter inhibits the PWM
comparator output for a short time after the
integrated Power MOSFET is switched on. This
function prevents anomalous or premature
termination of the switching pulse in the case of
current spikes caused by primary side
capacitance or secondary side rectifier reverse
recovery time.

STAND-BY MODE

Stand-by operation in nearly open load condition
automatically leads to a burst mode operation
allowing voltage regulation on the secondary
side. The transition from normal operation to
burst mode operation happens for a power P

STBY

given by :

1

2

P

STBY

L

=

PISTBY

2

F

SW

Where:
L

isthe primaryinductance of the transformer.

P

F

is the normalswitching frequency.

SW

I

is the minimum controllable current,

STBY

corresponding to the minimum on time that the
deviceis able to provide in normal operation. This
currentcan be computedas :

+ td) V

(t

I

STBY

S

tb+tdis the sum of the blanking time and of the

b

=

IN

L

P

propagation time of the internal current sense
and comparator, and represents roughly the
minimum on time of the device. Note that P
may be affectedby the efficiency of the converter
at low load, and mustinclude the power drawn on
the primary auxiliaryvoltage.

As soon as the power goes below this limit, the
auxiliary secondary voltage starts to increase
above the 13V regulation level forcing the output
voltage of the transconductance amplifier to low
state (V

COMP

<V

). This situation leads to

COMPth

the shutdown mode where the power switch is
maintained in the off state, resulting in missing
cycles and zero duty cycle. As soon as V
back to the regulation level and the V
threshold is reached, the device operates again.
The above cycle repeats indefinitely, providing a
burst mode of which the effective duty cycle is
much lower than the minimum one when in
normal operation. The equivalent switching
frequency is also lower than the normal one,
leading to a reduced consumption on the input
mains lines. This mode of operation allows the
VIPer20B to meet the new German ”Blue Angel”
Norm with 1W total power consumption for the
system when working in stand-by. The output
voltage remains regulated around the normal
level, with a low frequency ripple corresponding
to the burst mode. The amplitude of this ripple is
low, because of the output capacitors and of the
low output current drawn in such conditions.The
normal operation resumes automaticallywhen the
power get back to higher levels than P

HIGH VOLTAGE START-UP CURRENT
SOURCE

An integrated high voltage current source
provides a bias current from the DRAIN pin
during the start-up phase. This current is partially
absorbed by internal control circuits which are
placed into a standby mode with reduced

STBY

STBY

gets

DD

COMPth

.

11/17

VIPer20B / VIPer20BSP

consumption and also provided to the external
capacitor connected to the V

pin. As soon as

DD

the voltage on this pin reaches the high voltage
threshold V

of the UVLO logic, the device

DDon

turns into active mode and starts switching. The
start up current generator is switched off, and the
converter should normally provide the needed
current on the V

pin through the auxiliary

DD

winding of the transformer, as shown on figure

12.
In case of abnormalcondition where the auxiliary

winding is unable to provide the low voltage
supply current to the V

pin (i.e. short circuit on

DD

the output of the converter), the external
capacitor discharges itself down to the low
threshold voltage V

of the UVLO logic, and

DDoff

the device get back to the inactive state where
the internal circuits are in standby mode and the
start up currentsource isactivated.Theconverter
enters a endless start up cycle, with a start-up
duty cycle defined by the ratio of charging current
towards discharging when the VIPer20B tries to
start. This ratio is fixed by design to 2 to 14,
which gives a 13% start up duty cycle while the
power dissipation at start up is approximately1W,
for a 230 Vrms input voltage. This low value of
start-up duty cycle prevents the stress of the
output rectifiers and of the transformer when in
short circuit.

The external capacitor C

on the VDDpin must

VDD

be sized according to the time needed by the
converter to start up, when the device starts
switching. This time t

depends on many

SS

parameters, among which transformer design,
output capacitors, soft start feature and
compensation network implemented on the
COMP pin. The followingformula can be used for
definingthe minimum capacitorneeded:

I

>

DDtSS

V

DDhyst

C

VDD

where:
I

is the consumption current on the VDDpin

DD

when switching. Refer to specified I

DD1

and I

DD2

values.
t

is the start up time of the converter when the

SS

device begins to switch. Worst case is generally
at full load.

V

DDhyst

is the voltage hysteresis of the UVLO

logic. Referto the minimumspecified value.
Soft start feature can be implemented on the

COMP pin through a simple capacitor which will
be also used as the compensation network. In
this case, the regulation loop bandwidth is rather
low, because of the large value of this capacitor.
In case a large regulation loop bandwidth is
mandatory, the schematics of figure 13 can be
used. It mixes a high performance compensation

Figure12: Behaviourof the high voltagecurrent source at start-up

VDD

VDDon

VDDoff

t

Auxiliary primary

winding

2mA

15 mA

CVDD

VDD

15 mA1mA

Ref.

UNDERVOLTAGE
LOCK OUT LOGIC

VIPer

Start up duty cycle ~ 10%

12/17

3mA

DRAIN

SOURCE

FC00422

VIPer20B / VIPer20BSP

network together with a separate high value soft
start capacitor. Both soft start time and regulation
loop bandwidth can be adjustedseparately.

If the device is intentionally shut down by putting
the COMP pin to ground, the device is also
performingstart-up cycles, and the V
oscillatingbetween V

DDon

and V

DDoff

voltage is

DD

. This voltage
can be used for supplying external functions,
provided that their consumption doesn’t exceed

0.5mA. Figure 14 shows a typical application of
this function, with a latched shut down. Once the
”Shutdown” signal has been activated, the device
remains in the off state until the input voltage is
removed.

TRANSCONDUCTANCE ERROR AMPLIFIER

The VIPer30B includes a transconductance error
amplifier. Transconductance Gm is the change in
output current (I
voltage (V

∂

=

G

m

I

COMP

∂ V

). Thus:

DD

DD

The output impedanceZ

) versus change in input

COMP

at the output of this

COMP

amplifier(COMP pin)can be definedas:
Z

COMP

∂V

COMP

=

∂ I

=

COMP

G

∂ V

1

m

COMP

x

∂ V

DD

This last equation shows that the open loop gain
A

canbe related to GmandZ

VOL

A

VOL=GmxZCOMP

COMP

:

where Gmvalue for VIPer20B is 1.5 mA/V
typically.

G

is well defined by specification, but Z

m

COMP

and therefore A

are subject to large

VOL

tolerances. An impedance Z can be connected
between the COMP pin and ground in order to
define more accurately the transfer function F of
the error amplifier, according to the following
equation,very similar to the oneabove:

F

=Gm x Z(S)

(S)

The error amplifier frequency response is
reported in figure 8 for different values ofa simple
resistance connected on the COMP pin. The
unloaded transconductanceerror amplifier shows
an internal Z

COMP

of about 330 KΩ. More
complex impedance can be connected on the
COMP pin to achieve different compensation
laws. A capacitor will provide an integrator
function, thus eliminating the DC static error, and
a resistance in series leads to a flat gain at higher
frequency, insuring a correct phase margin. This
configurationis illustrated on figure 15.

As shown in figure 15 an additional noise filtering
capacitor of 2.2 nF is generally needed to avoid
any high frequencyinterference.

It can be also interesting to implement a slope
compensation when working in continuous mode
with duty cycle higher than 50%. Figure 16 shows
such a configuration.Note that R1 and C2 build
the classical compensation network, and Q1 is
injecting the slope compensationwith the correct
polarity from the oscillatorsawtooth.

EXTERNALCLOCK SYNCHRONIZATION:

The OSC pin provides a synchronisation
capability, when connected to an external
frequency source. Figure 17 shows one possible

Figure13: MixedSoft Start and Compensation

D2

C2

+

D3

R3

R2

FC00432

AUXILIARY
WINDING

VIPer

OSC

C3

+

-

13V

+

C4

DRAINVDD

COMP SO URCE

R1

C1

D1

Figure14: LatchedShutDown

R1

Shutdown

Q2

R4

OSC

R2R3

Q1

VIPer

-

13V

+

D1

DRAINVDD

COMP SOURCE

FC00442

13/17

VIPer20B / VIPer20BSP

schematic to be adapted depending the specific
needs. If the proposed schematic is used, the
pulse duration must be kept at a low value (500ns
is sufficient) for minimizing consumption. The
optocoupler must be able to provide 20mA
through the optotransistor.

PRIMARY PEAK CURRENT LIMITATION

The primary I

DPEAK

current and, as resulting
effect, the output power can be limited using the
simple circuit shown in figure 18. The circuit
based on Q1, R

and R2clamps the voltage on

1

the COMP pin in order to limit the primary peak
current of the device to a value:

I

DPEAK

V

=

COMP

H

− 0.5

ID

Figure15: TypicalCompensation Network

VIPer

DRAINVDD

COMP SOURCE

R1

C1

OSC

13V

-

+

C2

where:

+ R

R

1

V

COMP

= 0.6 x

2

R

2

The suggested value for R1+R2is in the range of
220KΩ.

OVER-TEMPERATURE PROTECTION:

Over-temperature protection is based on chip
temperature sensing. The minimum junction
temperature at which over-temperature cut-out
occurs is 140

o

C while the typical value is 160oC.
The device is automatically restarted when the
junction temperature decreases to the restart
temperaturethresholdthat is typically 34

o

C below

the shutdownvalue (see figure 6).

Figure16: SlopeCompensation

R1R2

OSC

Q1

VIPer

-

13V

+

C2

DRAINVDD

COMP SOURCE

C3

C1 R3

FC00452

FC00462

Figure17:ExternalClock Synchronization Figure 18:Current LimitationCircuit Example

VIPer

DRAINVDD

COMP SOURCE

Q1

FC00482

14/17

10 kΩ

OSC

13V

VIPer

­+

DRAINVDD

COMP SOURCE

FC00472

OSC

13V

-

+

R1

R2

VIPer20B / VIPer20BSP

PENTAWATT HV (VERTICAL) MECHANICAL DATA

DIM.

MIN. TYP. MAX. MIN. TYP. MAX.

mm inch

A 4.30 4.80 0.169 0.189
C 1.17 1.37 0.046 0.054
D 2.40 2.80 0.094 0.110
E 0.35 0.55 0.014 0.022
F 0.60 0.80 0.024 0.031

G1 4.90 5.28 0.193 0.208
G2 7.42 7.82 0.292 0.308

H1 9.30 9.70 0.366 0.382
H2 10.40 0.409
H3 10.05 10.40 0.396 0.409

L 16.60 17.30 0.653 0.681

L1 14.60 15.22 0.575 0.599
L2 21.20 21.85 0.835 0.860
L3 22.20 22.82 0.874 0.898
L5 2.60 3.00 0.102 0.118
L6 15.10 15.80 0.594 0.622
L7 6.00 6.60 0.236 0.260

M 2.50 3.10 0.098 0.122

M1 7.56 8.16 0.298 0.321

R 0.50 0.020

V4 90

o

90

Diam. 3.70 3.90 0.146 0.154

G2

G1

M1

M

leads

E

Resin

between

V4

F

L

L1

A

L5

H1

C

H3

H2

Diam

P023H3

R

D

L6

L7

L2

L3

15/17

VIPer20B / VIPer20BSP

PowerSO-10 MECHANICAL DATA

DIM.

MIN. TYP. MAX. MIN. TYP. MAX.

mm inch

A 3.35 3.65 0.132 0.144

A1 0.00 0.10 0.000 0.004

B 0.40 0.60 0.016 0.024
C 0.35 0.55 0.013 0.022
D 9.40 9.60 0.370 0.378

D1 7.40 7.60 0.291 0.300

e 1.27 0.050

E 9.30 9.50 0.366 0.374
E1 7.20 7.40 0.283 0.291
E2 7.20 7.60 0.283 0.300
E3 6.10 6.35 0.240 0.250
E4 5.90 6.10 0.232 0.240

F 1.25 1.35 0.049 0.053

h 0.50 0.002

H 13.80 14.40 0.543 0.567

L 1.20 1.80 0.047 0.071
q 1.70 0.067

α 0

o

o

8

==

==

HE

h

A

F

A1

610

51

eB

M

0.25

D

==

D1

==

E2

==

DETAIL”A”

DETAIL”A”

Q

B

0.10 A

E1E3

==

SEATING
PLANE

A

C

α

B

E4

==

SEATING

PLANE

A1

L

==

0068039-C

16/17

VIPer20B / VIPer20BSP

Information furnished is believed to beaccurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
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subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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