SGS Thomson Microelectronics VIPER20SP, VIPER20DIP, VIPER20ASP, VIPER20ADIP, VIPER20A Datasheet
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VIPer20/SP/DIP
TYPE V
DSS
I
R
n
DS(on)
VI Per 2 0/ SP/DI P 620V 0.5 A 16 Ω
VIPer20A/A SP/ AD IP 700V 0.5 A 18 Ω
FEATURE
■ ADJUSTABLESWITCHINGFREQUENCYUP
TO200KHZ
■ CURRENT MODE CONTROL
■ SOFTSTART AND SHUT DOWN CONTROL
■ AUTOMATIC BURST MODE OPERATION IN
STAND-BY CONDITIONABLE TO MEET
”BLUE ANGEL” NORM (<1W TOTAL POWER
CONSUMPTION)
■ INTERNALLY TRIMMEDZENER
REFERENCE
■ UNDERVOLTAGE LOCK-OUT WITH
HYSTERESIS
■ INTEGRATED START-UPSUPPLY
■ AVALANCHERUGGED
■ OVERTEMPERATURE PROTECTION
■ LOW STAND-BYCURRENT
■ ADJUSTABLECURRENTLIMITATION
DESCRIPTION
VIPer20/20A, made using VIPower M0
VIPer20A/ASP/ADIP
SMPS PRIMARY I.C.
PENTAWATTHV
10
1
PowerSO-10
Technology, combines on the same silicon chip a
state-of-the-art PWM circuit together with an
optimized high voltage avalanche rugged Vertical
Power MOSFET (620Vor 700V / 0.5A).
Typical applications cover off line power supplies
with a secondary power capability of 10W in wide
range condition and 20W in single range or with
doubler configuration. It is compatible from both
primary or secondary regulation loop despite
using around 50% less components when
compared with a discrete solution. Burst mode
operation is an additional feature of this device,
offering the possibility to operate in stand-by
mode without extra components.
PENTAWATT HV (022Y)
DIP-8
BLOCK DIAGRAM
November 1999
VDD
13 V
_
+
ERROR
AMPLIFIER
UVLO
LOGIC
0.5V +
ON/OFF
_
4.5V
SECURITY
LATCH
R/SSQSR1
OVERTEMP.
DETECTOR
1.7
µ
s
delay
OSCILLATOR
PWM
LATCH
R2 R3
COMP
OSC
DRAIN
FFFF
Q
0.5V
_
+
+
250ns
Blanking
6 V/A
_
CURRENT
AMPLIFIER
FC00491
SOURCE
1/21
VIPer20/SP/DIP- VIPer20A/ASP/ADIP
ABSOLUTEMAXIMUM RATING
Symb o l Para met er Val u e Uni t
V
I
V
V
OSC
V
COMP
I
COMP
V
I
D(AR)
P
T
T
THERMALDATA
R
thj-pin
R
thj-case
R
thj-a mb.
(*) When mounted using the minimum recommended pad size on FR-4 board.
# On multylayer PCB
Continuous Drain-Sour ce Voltage (Tj = 25 to 125oC)
DS
for VIPer20/ SP/DI P
for VIPer20A/ASP/ A DI P
Maximum Current Inte rnally Limited A
D
Supply Volt age 0 to 15 V
DD
Volt age Range Input 0 to V
-0.3 to 620
-0.3 to 700
DD
Volt age Range Input 0 to 5 V
Maximum Continuous Curre nt ±2mA
Elect r o st at ic discharge (R = 1. 5 K Ω C = 100pF)
esd
Avalanche Drain-Sour ce Curr e nt , Repetitive or Not-Repetit ive
(T C = 100
o
C, Pulse Width Limited by TJmax, δ <1%)
for VIPer20/ SP
for VIPer20A/ASP/ A DI P
Power Dissipation at Tc = 25oC57W
tot
Junction Operating Tempe r at ure Int ernally Limited
j
St orage T emperature -65 to 150
stg
4000 V
0.5
0.4
PENTAW ATT Po w erS O -10 DIP-8
20
Ther mal Res istance Junc ti on-case Max 2.0 2.0
Ther mal Res istance Ambient-case Max 70 60 35 #
o
o
o
C/W
o
C/W
o
C/W
V
V
V
A
A
C
C
CONNECTION DIAGRAMS(Top View)
PENTAWATT HV PENTAWATT HV (022Y) PowerSO-10 DIP-8
OS C
Vdd
SOURC E
COMP
CURRENT AND VOLTAGECONVENTIONS
IDD ID
OSC
I
OSC
DD
V
OSC
V
13V
+
ICOMP
VCOMP
DRAINVDD
COMP SOURCE
VDS
FC00020
1
4
8
5
SC105 40
DRAIN
DRAIN
DRAIN
DRAIN
2/21
VIPer20/SP/DIP- VIPer20A/ASP/ADIP
ORDERING NUMBERS
PENT AWATT HV PENT AWATT HV (022Y) Powe rSO-10 DIP -8
VIPer20
VIPer20A
VIP er 20 (022Y)
VIPer20A (0 22Y)
VIPer20SP
VIPer20ASP
VIPer20DIP
VIPer20ADIP
PINSFUNCTIONAL DESCRIPTION
DRAINPIN:
Integrated power MOSFET drain pin. It provides
internal bias current during start-up via an
integrated high voltage current source which is
switched off during normal operation.The device
is able to handle an unclampedcurrent during its
normal operation, assuring self protection against
voltage surges, PCB stray inductance, and
allowing a snubberless operation for low output
power.
SOURCEPIN:
Power MOSFET source pin. Primary side circuit
commonground connection.
VDD PIN :
This pin providestwo functions:
- It corresponds to the low voltage supply of the
controlpart of the circuit. If V
the start-up current source is activated and the
output power MOSFET is switched off until the
V
voltage reaches 11V. During this phase,
DD
the internal current consumption is reduced,
the V
pin is sourcing a currentof about 2mA
DD
and the COMP pin is shorted to ground. After
that, the current source is shut down, and the
devicetries to start upby switching again.
goes below 8V,
DD
- This pin is also connected to the error
amplifier, in order to allow primary as well as
secondary regulation configurations. In caseof
primary regulation, an internal 13V trimmed
reference voltage is used to maintain V
13V. For secondary regulation, a voltage
between 8.5V and 12.5V will be put on V
by transformer design, in order to stuck the
output of the transconductanceamplifier to the
high state. The COMP pin behaves as a
DD
DD
at
pin
constant current source, and can easily be
connected to the output of an optocoupler.
Note that any overvoltage due to regulation
loop failure is still detected by the error
amplifier through the V
voltage, which
DD
cannot overpass 13V. The output voltage will
be somewhathigher thanthe nominalone, but
still under control.
COMP PIN :
This pin provides two functions:
- It is the output of the error transconductance
amplifier, and allows for the connection of a
compensation network to provide the desired
transfer function of the regulation loop. Its
bandwidth can be easily adjusted to the
needed value with usual componentsvalue. As
stated above, secondary regulation
configurations are also implemented through
the COMPpin.
- When the COMP voltage is going below 0.5V,
the shut-downof the circuit occurs, with a zero
duty cycle for thepower MOSFET. This feature
can be used to switch off the converter, and is
automatically activated by the regulation loop
(whatever is the configuration) to provide a
burst mode operation in case of negligible
output power or openload condition.
OSC PIN :
An R
to define the switching frequency. Note that
despite the connection of R
significant frequency change occurs for V
varying from 8V to 15V. It provides also a
synchronisationcapability, when connected to an
external frequencysource.
network must be connectedon that pin
T-CT
to VDD,no
T
DD
3/21
VIPer20/SP/DIP- VIPer20A/ASP/ADIP
AVALANCHE CHARACTERISTICS
Symb o l Para met er Max Valu e Uni t
I
D(ar)
E
ELECTRICAL CHARACTERISTICS (TJ=25oC, VDD=13 V, unless otherwisespecified)
POWERSECTION
Symb o l Parameter Test Con d it i ons Mi n . Typ . Ma x. Unit
BV
I
DSS
R
DS(on)
C
OSS
(1) On Inductive Load, Clamped.
Avalanche Current , Repetit ive or Not-Repet it ive
(pulse widt h limited by T
for VIPer20/ SP/DI P
for VIPer20A/ASPA/DIP (see fig. 12)
Single Pulse Avalanche Ener g y
(ar)
(starti ng T
Drain-Source Voltage ID=1mA V
DSS
=25oC, ID=I
j
Of f - State Drain Current V
max, δ <1%)
j
) (see fig.12)
D(ar)
COMP
for VIPer20/SP/D IP
for VIPer20A/ASP/ DIP (see fig.5)
=0V TJ=125oC
COMP
= 620 V
V
DS
0.5
0.4
10 mJ
=0V
620
700
for VIPer20/SP/D IP
= 700 V
V
DS
for VIPer20A/ASP/ ADIP
St at ic Drain Source on
Resistance
ID=0.4A
for VIPer20/SP/D IP
for VIPer20A/ASP/ ADIP
=0.4A TJ=100oC
I
D
13.5
15.5
for VIPer20/SP/D IP
for VIPer20A/ASP/ ADIP
t
Fall T ime ID = 0.2 A Vin=300V(1)
f
100 ns
(see fig. 3)
Rise Time ID=0.4A Vin= 300 V (1)
t
r
50 ns
(see fig. 3)
Out put Capacitance VDS=25V 90 pF
1.0
1.0
16
18
29
32
A
A
V
V
mA
mA
Ω
Ω
Ω
Ω
SUPPLY SECTION
Symb o l Parameter Test Con d it i ons Mi n . Typ . Ma x. Unit
4/21
I
DDch
I
DD0
I
DD1
I
DD2
V
DDo f f
V
DDo n
V
DDhyst
St art - u p Charging
Current
Oper at i ng Supply Current VDD=12V, FSW=0KHz
VDD=5V VDS=70V
(see fig. 2 and fig. 15)
-2 mA
12 16 mA
(see fig. 2)
Oper at i ng Supply Current VDD=12V, FSW=100KHz 13 mA
Oper at i ng Supply Current VDD=12V, FSW=200KHz 14 mA
Undervoltage Shutdown (see fig. 2) 7.5 8 V
Undervoltage Reset (see fig. 2) 11 12 V
Hysteresis Start-up (see fig. 2) 2.4 3 V
VIPer20/SP/DIP- VIPer20A/ASP/ADIP
ELECTRICAL CHARACTERISTICS (continued)
OSCILLATORSECTION
Symb o l Parameter Test Con d it i ons Mi n . Typ . Ma x. Unit
F
V
OSCih
V
OSCil
ERRORAMPLIFIERSECTION
Symbol Parameter Test C ondition s Min. Typ . Max. Un it
V
DDreg
∆V
DDreg
G
A
VOL
G
V
COMPLO
V
COMPHI
I
COMPLO
I
COMPHI
Os cillator Frequency
SW
Total Variation
= 8.2 K
R
T
= 9 t o15 V
V
DD
with R
Ω
CT=2.4 nF
± 1% CT ± 5%
T
90 100 110 KHz
(see fig. 6 and fig. 9)
Os cillator Peak Voltage 7.1 V
Os cillator Valley V o lt age 3.7 V
VDD Regulat ion Point I
= 0 m A (see fig.1) 12.6 13 13. 4 V
COMP
Total Variation TJ= 0 to 100oC2%
Unity Gain Bandwidt h Fr om Input = VDDto Output = V
BW
COMP
150 KHz
COM P pin is open (see fig. 10 )
Open Loop V o lt age
COM P pin is open (see fig. 10 ) 45 52 dB
Gain
DC Transconduc tance V
m
Out put Low Level
Out put High L evel
Out put Low Current
= 2.5 V (see fig. 1) 1.1 1.5 1.9 mA/V
COMP
=-400µAVDD=14V
I
COMP
= 400 µ AVDD=12V
I
COMP
V
=2.5V VDD= 14 V -600 µ A
COMP
0.2 V
4.5 V
Capability
Out put High C urr ent
V
=2.5V VDD= 12 V 600 µA
COMP
Capability
PWM COMPARATORSECTION
Symbol Parameter Test C ondition s Min. Typ . Max. Un it
H
V
COMPoffVCOMP
I
Dpeak
t
∆V
ID
Peak Current Limitation VDD= 12 V COMP pin open 0.5 0.67 0.9 A
Current Sense Delay
d
/∆I
COMP
Dpeak
off s et I
V
= 1 to 3 V 4.2 6 7.8 V/A
COMP
=10mA 0.5 V
Dpeak
ID= 1 A 250 ns
to turn-off
t
t
on(min)
Blanking T ime 250 3 60 ns
b
Minimum on T ime 350 ns
SHUTDOWNAND OVERTEMPERATURESECTION
Symbol Parameter Test C ondition s Min. Typ . Max. Un it
V
COMPth
t
DISsu
T
T
hyst
Restart threshold (see fig. 4) 0.5 V
Disable Set Up Time (see f ig. 4 ) 1.7 5 µs
Ther mal Shut down
tsd
(see fig. 8 ) 140 170 190
Tem perature
Ther mal Shut down
(see fig. 8 ) 40
Hyst eresis
o
o
C
C
5/21
VIPer20/SP/DIP- VIPer20A/ASP/ADIP
Figure1:VDDRegulationPoint
COMP
I
ICOMPHI
0
ICOMPLO
VDDreg
Figure3: TransitionTime
ID
10%Ipeak
Slope =
Gm in mA/V
FC00150
Figure2: UndervoltageLockout
IDD
IDD0
DD
V
VDDhyst
V
DDoff
IDDch
Figure4: ShutDown Action
VOSC
VCOMP
t
tDISsu
VDS=70V
Fsw = 0
V
DDon
FC00170
VDD
t
VDS
VCOMPth
90%VD
ID
10%V
D
t
tf tr
FC00160
ENABLE
DISABLE
Figure5: BreakdownVoltage vs Temperature Figure6: Typical FrequencyVariation
1.15
BV
DS S
(Nor malize d)
1.1
1.05
0.95
1
0 20406080100120
Temperature ( C)
FC00180
1
(%)
0
-1
-2
-3
-4
-5
0 20 40 60 80 100 120 140
Temperature ( C)
t
t
ENABLE
FC00060
FC00190
6/21
Figure7: Start-upWaveforms
VIPer20/SP/DIP- VIPer20A/ASP/ADIP
Figure8: OvertemperatureProtection
Ttsd
Tts d-Thys t
Vddon
Vddoff
Tj
t
Vdd
t
Id
t
Vco mp
t
SC1 019 1
7/21
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