SGS Thomson Microelectronics TSA1204IFT, TSA1204IF, TSA1204 Datasheet
TSA1204
DUAL-CHANNEL, 12-BIT, 20MSPS, 120mW A/D CONVERTER
■ 0.5Msps to 20Msps sampling frequency
■ Adaptive power consumption: 120mW @
20Msps, 95mW@10Msps
■ Single supply voltage: 2.5V
Independent supply for CMOS output stage
with 2.5V/3.3V capability
■ ENOB=11.2 @ Nyquist
■ SFDR= -81.5 dBc @ Nyquist
■ 1GHz analog bandwidth Track-and-Hold
■ Common clocking between channels
■ Dual simultaneous Sample and Hold inputs
■ Multiplexed outputs
■ Built-in reference voltage with external bias
capability.
DESCRIPTION
The TSA1204 is a new generati on of high speed,
dual-channel Analog to Digital converter pro-
cessed in a mainstream 0.25µm CMOS techno logy yielding high performances and very low power
consumption.
The TSA1204 is specifically designed for applications requiring very low noise floor, high SFDR
and good isolation b etween channels. It is based
on a pipeline structure and digital error correction
to provide excellent static linearity and over 11.2
effective bits at Fs=20Msps, and Fin=10MHz.
For each channel, a voltage reference is integrated to simplify the design and minimize external
components. It is nevertheless possible to use the
circuit with external references.
Each ADC outputs are multiplexed in a common
bus with small number of pins. A tri-state capability is available for the outputs, allowing chip s election. The inputs of t he ADC must be differentially
driven.
The TSA1204 is available in extended (-40 to
+85°C) temperature range, in a small 48 pins
TQFP package.
APPLICATIONS
■ Medical imaging and ultrasound
■ 3G base station
■ I/Q signal processing applications
■ High speed data acquisition system
■ Portable in st ru me nta t ion
PIN CONNECTIONS (top view)
REFPI
REFMI
INCMI
index
corner
AGND
AGND
AGND
AVCCB
AGND
AGND
INBQ
AGND
48 44 43 42 41 40 39 38
46 45
47
1
2
INI
3
4
INIB
5
6
IPOL
7
8
INQ
9
10
11
12
13 14 15 16 17 18 19 20 21 22
REFPQ
INCMQ
REFMQ
AVCC
AVCC
TSA1204
AGND
AVCC
GNDBE
VCCBI
VCCBI
OEB
SELECT
CLK
DGND
DVCC
BLOCK DIAGRAM
SELECT
CLK
Timing
12
12
GND
VINI
VINBI
VINCMI
common mode
VREFPI
VREFMI
Polar.
IPO L
VREFPQ
VREFMQ
VINCMQ
common mo de
VINQ
VINBQ
PACKAGE
+2.5V/3.3V
AD 12
I channel
REF I
REF Q
AD 12
Q channel
DGND
M
U
X
VCCBE
D0(LSB)
23 24
DVCC
12
D1
37
GNDBI
OEB
36
35
34
33
32
31
30
29
28
27
26
25
Buffers
GNDBE
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11(MSB)
VCCBE
GNDBE
VCCBE
12
D0
TO
D11
ORDER CODE
Part Number
TSA1204IF -40°C to +85°C TQFP48 Tray SA120 4I
TSA1204IFT -40°C to +85°C TQFP48 Tape & Reel SA1204I
EVAL1204/BA Evaluation board
February 2003
Temperature
Range
Package Conditioning Marking
7 × 7 mm TQFP48
1/20
TSA1204
CONDITIONS
AVCC = DVCC = VCCB = 2.5V , Fs= 20Msps, Fin=10.5MHz, Vin@ -1dBFS, VREFP=1.0V, VREFM=0V
Tamb = 25°C (unless otherwise specified)
DYNAMIC CHARACTERISTICS
Symbol Parameter Test conditions Min Typ Max Unit
SFDR Spurious Free Dynamic Range -81.5 -71.0 dBc
SNR Signal to Noise Ratio 66.9 68.5 dB
THD Total Harmonics Distortion -80 -70 dBc
SINAD Signal to Noise and Distortion Ratio 64.8 68 dB
ENOB Effective Number of Bits 10.6 11.2 bits
TIMING CHARACTERISTICS
Symbol Parameter Test conditions Min Typ Max Unit
FS Sampling Frequency 0.5 20 MHz
DC Clock Duty Cycle 45 50 55 %
TC1 Clock pulse width (high) 22.5 25 ns
TC2 Clock pulse width (low) 22.5 25 ns
Tod Data Output Delay (Clock edge to Data Valid) 10pF load capacitance 9 ns
Tpd I Data Pipeline delay for I channel 7 cycles
Tpd Q Data Pipeline delay for Q channel 7.5 cycles
Ton Falling edge of OEB to digital output valid data 1 ns
Toff Rising edge of OEB to digital output tri-state 1 ns
2/20
TIMING DIAGRAM
Simultaneous sampling
on I/Q channels
N+3
N+4
N+5
N+6
N+12
TSA1204
N+13
I
Q
CLK
SELECT
OEB
DATA
OUTPUT
sample N-9
I channel
N-1
N
sample N-8
I channel
samp le N-7
Q channel
N+1
N+2
sample N-6
Q channel
PIN CONNECTIONS (top view)
index
corner
AGND
INI
AGND
INIB
AGND
IPOL
AVCCB
AGND
AGND
INBQ
AGND
INQ
Tpd I + Tod
CLOCK AND SELECT CONNECTED TOGETHER
REFPI
REFMI
INCMI
AVCC
47
48 44 43 42 41 4 0 39 38
46 45
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22
REFPQ
INCMQ
REFMQ
TSA1204
AGND
VCCBI
AVCC
OEB
DGND
AVCC
DVCC
N+7
sample N+1
I channel
VCCBI
SELECT
CLK
N+8
sample N
Q channe l
GNDBE
VCCBE
DGND
N+9
Tod
sample N+1
Q channel
sample N+2
I channel
D0(LSB)
D1
37
23 24
DVCC
GNDBI
D2
36
D3
35
D4
34
D5
33
32
D6
31
D7
D8
30
D9
29
D10
28
D11(MSB)
27
26
VCCBE
GNDBE
25
N+10
sample N+2
Q channel
sample N+3
I chan n el
N+11
3/20
TSA1204
PIN DESCRIPTION
Pin No Name Description Observation Pin No Name Description Observation
1 AGND Analog ground 0V 25 GNDBE Digital buffer ground 0V
2 INI I channel analog input 26 VCCBE Digital Buffer power supply 2.5V/3.3V
3 AGND Analog ground 0V 27 D11(MSB) Most Sign ificant Bi t output CMOS output (2.5V/3.3V)
4 INBI I channel inverted analog input 28 D10 Digital output CMOS output (2.5V/3.3V)
5 AGND Analog ground 0V 29 D9 Digital output CMOS output (2.5V/3.3V)
6 IPOL Analog bias current i nput 30 D8 Digital output CMOS output (2.5 V/3.3V)
7 AVCC Analog power supply 2.5V 31 D7 Digital output CMOS output (2.5V/3.3V)
8 AGND Analog ground 0V 32 D6 Digital output CMOS output (2.5V/3.3V)
9 INQ Q channel analog input 33 D5 Digital output CMOS output (2.5V/3.3V)
10 AGND Analog ground 0V 34 D4 Digital output CMOS output (2.5V/3.3V)
11 INBQ Q channel inverted analog input 35 D3 Digital output CMOS output (2.5V/3.3V)
12 AGND Analog ground 0V 36 D2 Digital output CMOS output (2.5V/3.3V)
13 REFPQ Q channel top reference voltage 37 D1 Digital output CMOS output (2.5V/3.3V)
14 REFMQ Q channel bottom reference
15 INCMQ Q channel input common mode 39 VCCBE Digital Buffer power supply 2.5V/3.3V - See Application
16 AGND Analog ground 0V 40 GNDBE Digital buffer ground 0V
17 AVCC Analog power supply 2.5V 41 VCCBI Digital Buffer power supply 2.5V
18 DVCC Digital power supply 2.5V 42 DVCC Digital Buffer power s upply 2.5V
19 DGND Digital ground 0V 43 OEB Output Enable inpu t 2.5V/3.3V CMO S input
20 CLK Clock input 2.5V CMOS input 44 AVCC Analog power su pply 2.5V
21 SELECT Channel select ion 2.5V CMOS inp ut 45 AVCC Analog power supp ly 2.5V
22 DGND Digital ground 0V 46 INCMI I channel input common mode
23 DVCC Digital power supply 2.5V 47 REFMI I channel bottom reference voltage 0V
24 GNDBI Digital buffer ground 0V 48 REFPI I channel top reference voltage
voltage
0V 38 D0(LSB) Least Significant Bit output CMOS output (2.5V/3.3V)
Note
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Values Unit
AVCC
DVCC
VCCBE
VCCBI
Analog Supply voltage
Digital Supply voltage
Digital buffer Supply voltage
Digital buffer Supply voltage
IDout Digital output current -100 to 100 mA
Tstg Storage temperature +150 °C
ESD
HBM: Human Body Model
CDM: Charged Device Model
Latch-up
1). All voltages values, except differential voltage, are with respect to network ground terminal. The magnitude of input and output voltages must not exceed -0.3V or VCC
2). ElectroStatic Discharge pulse (ESD pulse) simulating a human body discharge of 100 pF through 1.5kΩ
3). Discharge to Ground of a device that has been previously charged.
4). Corporate ST Microelectronics procedure number 0018695
Class
4)
OPERATING CONDITIONS
Symbol Parameter Min Typ Max Unit
AVCC Analog Supply voltage 2.25 2.5 2.7 V
DVCC Digital Supply voltage 2.25 2.5 2.7 V
VCCBE External Digital buffer Supply voltage 1.8 2.5 3.5 V
VCCBI Internal Digital buffer Supply voltage 2.25 2.5 2.7 V
1)
1)
1)
1)
2)
3)
0 to 3.3 V
0 to 3.3 V
0 to 3.6 V
0 to 3.3 V
2
1.5
kV
A
4/20
TSA1204
Symbol Parameter Min Typ Max Unit
VREFPI
VREFPQ
VREFMI
VREFMQ
INCMI
INCMQ
1)
Condition V RefP-VRe fM>0.3V
Forced top voltage reference
Forced bottom reference voltage
Forced input common mode voltage 0.2 1 V
ELECTRICAL CHARACTERISTICS
AVCC = DVCC = VCCB = 2.5V, Fs= 20Msps, Fin=2MHz, Vin@ -1dBFS, VREFP=1.0V, VREFM=0V
Tamb = 25°C (unless otherwise specified)
ANALOG INPUTS
Symbol Parameter Test conditions Min Typ Max Unit
VIN-VINB Full scale refere nce voltag e Differential inputs mandatory 1.1 2.0 2.8 Vpp
Cin Input capacitance 7.0 pF
Req Equivalent input resistor 3 K
BW Analog Input Bandwidth Vin@Full Scale, Fs=20Msps 1000 MHz
ERB Effective Resolution Bandwidth 70 MHz
1)
1)
0.96 1.4 V
0 0.4 V
Ω
DIGITAL INPUTS AND OUTPUTS
Symbol Parameter Test conditions Min Typ Max Unit
Clock and Select inputs
VIL Logic "0" voltage 0 0.8 V
VIH Logic "1" voltage 2.0 2.5 V
OEB input
VIL Logic "0" voltage 0
VIH Logic "1" voltage
0.75 x
VCCBE
VCCBE V
Digital Outputs
VOL
VOH
Logic "0" voltage
Logic "1" voltage
Iol=10µA
Ioh=10µA 0.9 x
VCCBE
VCCBE V
IOZ High Impedance leakage current OEB set to VIH -1.7 1.7 µA
C
Output Load Capacitance 15 pF
L
0.25 x
VCCBE
0.1 x
0
VCCBE
V
V
5/20
TSA1204
ELECTRICAL CHARACTERISTICS
AVCC = DVCC = VCCB = 2.5V, Fs= 20Msps, Fin=2MHz, Vin@ -1dBFS, VREFP= 1.0V, VREFM=0V
Tamb = 25°C (unless otherwise specified)
REFERENCE VOLTAGE
Symbol Parameter Test conditions Min Typ Max Unit
VREFPI
VREFPQ
VINCMI
VINCMQ
POWER CONSUMPTION
Symbol Parameter Min Typ Max Unit
Top internal reference voltage 0.807 0.89 0.963 V
Input common mode voltage 0.40 0.46 0.52 V
ICCA Analog Supply current 40 49.5 mA
ICCD Digital Supply Current 2 3 mA
ICCBE Digital Buffer Supply Current (10pF load) 6.2 9 mA
ICCBI Digital Buffer Supply Current 73 221
Pd Power consumption in normal operation mode 120 155 mW
Rthja Thermal resistance (TQFP48) 80 °C/W
ACCURACY
Symbol Parameter Min Typ Max Unit
OE Offset Error -1.8 -0.5 1.8 LSB
GE Gain Error -0.1 0 0.1 %
DNL Differential Non Linearity -0.93 ±0.4 +0.93 LSB
INL Integral Non Linearity -1.8 ±0.8 +1.8 LSB
Mono tonicity and no missing codes Guaranteed
A
µ
MATCHING BETWEEN CHANNELS
Symbol Parameter Min Typ Max Unit
GM Gain match 0.033 0.1 %
OM Offset match 0.4 2.5 LSB
PHM Phase match 1 dg
XTLK Crosstalk rejection 87 dB
6/20
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