SGS Thomson Microelectronics TSA1201IF Datasheet
TSA1201
12-BIT, 50MSPS, 150mW A/D CONVERTER
■ 0.5Msps to 50Msps sampling frequency
■ 40mW @5Msps, 150mW @ 50Msps
■ 2.5V supply voltage with 2.5V/3.3V compati-
bility for digital I/O
■ Input range: 2Vpp differential
■ SFDR up to 77dB @ 50Msps, Fin=15MHz
■ ENOB up to10.5 bits @ 50Msps, Fin=15MHz
■ Built-in reference voltage with external bias
capability
■ Pinout compatibility with TSA0801, TSA1001
and TSA1002
DESCRIPTION
The TSA1201 is a 12-bit, 50MHz maximum
sampling frequency Analog to Digital converter
using a CMOS technology combining high
performances and very low power consumption.
The TSA1201 is based on a pipeline structure and
digital error correction to provide excellent static
linearity and achieve 10.5 effective bits at
Fs=50Msps, and Fin=15M Hz, with a global power
consumption of 150mW.
The TSA1201 features adaptative behaviour to
the application. Its architecture allows to sample
from 0.5Msps up to 50Msps, with a programmable
power consumption which makes the application
board even more optimized.
It integrates a proprietary track-and-hold structure
to ensure an high analog bandwidth of 1GHz and
enable IF-sampling.
Several features are available on the device. A
voltage reference is integrated in the circuit.
Differential or single-ended analog inputs can be
applied. The output data can be coded into two
differential formats. A Data Ready signal is raised
as the data is valid on the output and can be used
for synchronization purposes.
The TSA1201 is available in extended (-40°C to
+85°C) temperature range, in small 48 pins TQFP
package.
ORDER CODE
Part Number
TSA1201IF -40°C to +85°C TQFP48 Tray SA120 1I
TSA1201IFT -40°C to +85°C TQFP48 Tape & Reel SA1201I
EVAL1201/AA Evaluation board
Temperature
Range
Package Conditioning Marking
PIN CONNECTIONS (top view)
GNDBE
VCCBE
VCCBI
SRC
OEB
NC
GNDBE
GNDBI
DGND
VCCBENCOR
DR
23 24
NC
37
NC
36
D0 (LSB)
35
D1
34
33
D2
32
D3
31
D4
30
D5
D6
29
D7
28
D8
27
26
D9
25
D10
D11 (MSB)
index
corner
IPOL
VREFP
VREFM
AGND
VIN
AGND
VINB
AGND
INCM
AGND
AVCC
AVCC
AVCC
AGND
AVCC
DFSB
48 44 43 42 41 40 39 38
46 45
47
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22
DVCC
DVCC
TSA1201
CLK
DGND
DGND
PACKAGE
7 x 7 mm TQFP48
APPLICATIONS
■ High speed data acquisition
■ Medical imaging and ultrasound
■ Portable instrumentation
■ High speed DSP interface
■ Digital communica t ion - IF s ampling
March 2001
1/20
TSA1201
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Values Unit
AVCC
DVCC
VCCBI
VCCBE
Analog Supply voltage
Digital Supply voltage
Digital buffer Supply voltage
Digital buffer Supply voltage
Tstg Storage temperature +150 °C
Electrical Static Discharge
ESD
- HBM
- CDM-JEDEC Standard
1. All voltages v al ues, except diffe rential vol tage, are with respect to net work ground termi nal. The m agnitude of input and outpu t volt ag es
must neve r exceed -0. 3V or VCC+0V
OPERATING CONDITIONS
Symbol Parameter Test conditions Min Typ Max Unit
AVCC Analog Supply voltage 2.25 2.5 2.7 V
DVCC Digital Supply voltage 2.25 2.5 2.7 V
VCCBI Internal (quiet) buffer Supply voltage 2.25 2.5 2.7 V
VCCBE External (noisy) buffer Supply voltage 2.25 2.5 3.5 V
VREFP Forced top voltage reference 0.8 - AVCC V
VREFM Bottom internal reference voltage input 0 1 V
1)
1)
1)
1)
0 to 3.3 V
0 to 3.3 V
0 to 3.3 V
0 to 3.6 V
2
KV
1.5
BLOCK DIAGRAM
VIN
IN CM
VINB
CLK
+2.5V
Timing
+2.5V/3.3V
stage stage
1
GND
2
Sequ en cer-pha se sh ifting
Dig ita l d a ta cor re ctio n
stage
n
Buffers
VREFP
Reference
circuit
GNDA
IPOL
VREFM
DFSB
SRC
OEB
DR
DO
TO
D11
OR
2/20
PIN CONNECTIONS (top view)
index
corner
1
IPOL
2
VREFP
AGND
VIN
AGND
VINB
AGND
INCM
AGND
AVCC
AVCC
3
4
5
6
7
8
9
10
11
12
VREFM
GNDBE
VCCBE
AVCC
AGND
AVCC
DFSB
OEB
47
48 44 43 42 41 40 39 38
46 45
VCCBI
SRC
NC
TSA1201
13 14 15 16 17 18 19 20 21 22
DVCC
DVCC
DGND
CLK
DGND
DGND
GNDBE
GNDBI
VCCBENCOR
DR
23 24
NC
37
D11 (MSB)
36
35
34
33
32
31
30
29
28
27
26
25
TSA1201
NC
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
PIN DESCRIPTION
Pin No Name Description Observation Pin No Name Description Observation
1 IPOL Analog bi as current input 25 D10 Digital outp ut CMOS output (2.5V/3.3V)
2 VREFP To p voltage re ference 1V 26 D9 Digital outp ut CMOS output (2.5V/3.3V)
3 VREFM Bottom voltage refer ence 0V 27 D8 Digital output CMOS output (2.5V/3.3V)
4 AGND Analog ground 0V 28 D7 Digital output CMOS output (2.5V/3.3V)
5 VIN Analog input 1Vpp 29 D6 Digital output CMOS output (2.5V/3.3V)
6 AGND Analog ground 0V 30 D5 Digital output CMOS output (2.5V/3.3V)
7 VINB Inverted analog input 1Vpp 31 D4 Digital output CMOS output (2.5V/3.3V)
8 AGND Analog ground 0V 32 D3 Digital output CMOS output (2.5V/3.3V)
9 INCM Input common mode 0.5V 33 D2 Digital output CMOS output (2.5V/3.3V)
10 AGND Analog ground 0V 34 D1 Digital output CMOS output (2.5V/3.3V)
11 AVCC Analog power supply 2.5V 35 D0(LSB) Least Significant Bit output CMOS output (2.5V/3.3V)
12 AVCC Analog power supply 2.5V 36 NC Non connected
13 DVCC Digital power supply 2.5V 37 NC Non con nected
14 DVCC Digital power supply 2.5V 38 DR Data Ready output CMOS output (2.5V/3.3V)
15 DGND Digital ground 0V 39 VCCBE Digital Buffer po wer su pply 2.5V/3.3V
16 CLK Clock input 2.5V compatible CMOS input 40 GND BE Digital Buffer ground 0V
17 DGND Digital ground 0V 41 VCCBI Digital Buff er power supply 2.5V
18 NC Non connec ted 42 NC Non connected
19 DGND Digita l ground 0V 43 SRC Slew ra te cont r ol input 2.5V/3.3V CMOS input
20 GNDBI Digital buffer ground 0V 44 OEB Output Enable input 2.5V/3.3V CMOS input
21 GNDBE Digital buffer ground 0V 45 DFSB Data Format Select input 2.5V/3.3V CMOS input
22 VCCBE Digital buffer power supply 2.5V/3.3V 46 AVCC Analog power supply 2.5V
23 OR Out Of Range output CMOS output (2.5V/3.3V) 47 AVCC Analog power supply 2.5V
24 D11(MSB) Most Significant Bit output CMOS output (2.5V/3.3V) 48 AGND Analog ground 0V
3/20
TSA1201
ELECTRICAL CHARACTERISTICS
AVCC = DVCC = VCCBE = VCCBI = 2.5V,Fs= 50Msps,Fin=2MHz, Vin@ -1dBFS, VREFM=0V
Tamb = 25°C (unless otherwise specified)
TIMING CHARACTERISTICS
Symbol Parameter Test conditions Min Typ Max Unit
FS Sampling Frequency 0.5 50 MHz
DC Clock Duty Cycle 45 50 55 %
TC1 Clock pulse width (high) 9 10 ns
TC2 Clock pulse width (low) 9 10 ns
Tod
Data Output Delay (Fall of Clock
to Data Valid)
Tpd Data Pipeline delay 5.5 cycles
Ton
Toff
Falling edge of OEB to digital
output valid data
Rising edge of OEB to digital
output tri-state
6pF load capacitance
8ns
1ns
1ns
TIMING DIAGRAM
N-3
CLK
OEB
Tod
DATA
OUT
DR
N-2
N-1
N+2
N+1
N
Tpd + Tod
Toff
N+3
N-3
N+4
N+5
N+6
Ton
N-1N-4N-5N-6N-7N-8N-9
N
4/20
HZ state
TSA1201
CONDITIONS
AVCC = DVCC = VCCBE = VCCBI = 2.5V,Fs= 50Msps,Fin=2M Hz, Vin@ -1dBFS, VRE FM=0V
Tamb = 25°C (unless otherwise specified)
ANALOG INPUTS
Symbol Parameter Test conditions Min Typ Max Unit
VIN-VINB Full scale reference voltage 2.0 Vpp
Cin Input capacitance 7.0 pF
Rin Differential input resistance 5 MΩ
BW Analog Input Bandwitdh Vin@Full Scale, Fs=50Msps 1000 MHz
ERB
1. See parameters definiti on for more in formation .
Effective Resolution Bandwidth
REFERENCE VOLTAGE
Symbol Parameter Test conditions Min Typ Max Unit
1)
90 MHz
VREFP Top internal reference voltage
Tmin= -40°C to Tmax= 85°C
Vpol Analog bias voltage
Tmin= -40°C to Tmax= 85°C
VINCM Input common mode voltage
Tmin= -40°C to Tmax= 85°C
1. Not f ul l y tested over the temperat ure range. Guaranted by sampling.
0.79 1.0 1.16 V
1)
0.79 1.16 V
1.08 1.15 1.22 V
1)
1.07 1.23 V
0.40 0.55 0.65 V
1)
0.4 0.65 V
5/20
TSA1201
CONDITIONS
AVCC = DVCC = VCCBE = VCCBI = 2.5V,Fs= 50Msps,Fin=2M Hz, Vin@ -1dBFS, VRE FP=1V,
VREFM=0V
Tamb = 25°C (unless otherwise specified)
POWER CONSUMPTION
Symbol Parameter Test conditions Min Typ Max Unit
Power consumption in normal
Pd
operation mode
1)
Tmin= -40°C to Tmax= 85°C
1)
ICCA Analog Supply current
Tmin= -40°C to Tmax= 85°C
1)
ICCD Digital Supply Current
Tmin= -40°C to Tmax= 85°C
1)
ICCBI Digital Buffer Supply Current
Tmin= -40°C to Tmax= 85°C
1)
ICCBE Digital Buffer Supply Current
Tmin= -40°C to Tmax= 85°C
ICCBEZ
Rthja
1. Equivalent lo ad: Rl oad= 470 Ω and Cload= 6pF
2. Not f ul l y tested over the temperat ure range. Guaranted by sampling.
Digital Buffer Supply Current in
High Impedance Mode
Junction-ambient ther ma l resistance (TQFP48)
2)
2)
2)
2)
2)
150 158 mW
165 mW
46 51 mA
55 mA
1.9 2.2 mA
2.2 mA
0.3 0.4 mA
0.4 mA
9.8 10.8 mA
10.8 mA
45mA
80 °C/W
DIGITAL INPUTS AND OUTPUTS
Symbol Parameter Test conditions Min Typ Max Unit
Clock input
VIL Logic "0" voltage 0 0.8 V
VIH Logic "1" voltage 2.0 2.5 V
Digital inputs
VIL Logic "0" voltage 0
VIH Logic "1" voltage
0.75 x
VCCBE
VCCBE V
0.25 x
VCCBE
Digital Outputs
VOL
VOH
Logic "0" voltage
Logic "1" voltage
Iol=10µA
Ioh=10µA 0.9 x
VCCBE
0.1 x
0
VCCBE
VCCBE V
IOZ High Impedance leakage current OEB set to VIH -2.5 2.5 µA
C
Output Load Capacitance 15 pF
L
6/20
V
V
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