SGS Thomson Microelectronics TSA1001IF Datasheet
TSA1001
10-BIT, 25MSPS, 35mW A/D CONVERTER
■ 10-bit A/D converter in deep submicron
CMOS technology
■ Ultra low power consumption: 35mW @
25Msps (10mW @ 5Msps)
■ Single supply voltage: 2.5V
■ Input range: 2Vpp differential
■ 25Msps sampling frequency
■ ENOB=9.7 @ Nyquist
■ SFDR typically up to 72dB @ Nyquist
■ Built-in reference voltage with external bias
capability
■ STMicroelectronics 8, 10, 12 and 14-bits ADC
pinout compatibility
DESCRIPTION
The TSA1001 is a 10-bit, 25Msps sampling frequency Analog to Digital converter using a CMOS
technology combining high performances and
very low power consumption.
The TSA1001 is based on a pipeline structure and
digital error correction to provide excellent static
linearity and go beyond 9.8 effective bits at
Fs=25Msps, and Fin=10MHz .
Especially designed f or portable applications, the
TSA1001 only dissipates 35mW at 25Msps. When
running at lower sampling frequencies, even lower
consumption can be achieved.
A voltage reference is int egrated in the circuit to
simplify the de sign and minimize external c om ponents. It is nevertheless possible to use the circuit
with an external reference.
The output data can be coded into two different
formats. A Data Ready signal is raised as the data
is valid on the output and can be used for synchronization purposes.
The TSA1001 is available in commercial (0 to
+70°C) and extended (-40 t o +85°C) temperat ure
range, in a small 48 pins TQFP package.
ORDER CODE
Part Number
TSA1001CF 0°C to +70°C TQFP48 Tray SA1001C
TSA1001CFT 0°C to +70°C TQFP48 Tape & Reel SA1001C
TSA1001IF -40°C to +85°C TQFP48 Tray SA1001I
TSA1001IFT -40°C to +85°C TQFP48 Tape & Reel SA1001I
EVAL1001/AA Evaluation board
Temperature
Range
Package Conditioning Marking
PIN CONNECTIONS (top view)
AGND
index
corner
IPOL
VREFP
VREFM
AGND
VIN
AGND
VINB
AGND
INCM
AGND
AVCC
AVCC
AVCC
AVCC
DFSB
4748 44 43 42 41 40 39 38
46 45
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22
DVCC
DVCC
TSA1001
CLK
DGND
DGND
OEB
VCCB
GNDB
NC
DGND
VCCB
NC
GNDB
GNDB
VCCBNCOR
DR
23 24
NC
37
NC
36
NC
35
NC
34
33
D0 (LSB)
32
D1
31
D2
30
D3
D4
29
D5
28
D6
27
26
D7
25
D8
D9 (MSB)
PACKAGE
7 × 7 mm TQFP48
APPLICATIONS
■ Portable instrumentation
■ Video processing
■ Medical imaging and ultrasound
■ High resolution fax and scanners
■ Digital communications
October 2000
1/19
TSA1001
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Values Unit
AVCC
DVCC
VCCB
Analog Supply voltage
Digital Supply voltage
Digital buffer Supply voltage
IDout Digital output current -100 to 100 mA
Tstg Storage temperature +150 °C
ESD Electrical Static Discharge:
- HBM
- CDM-JEDEC Standard
1). All voltages values, except di f ferential v ol tage, are with respe ct t o network ground te rm i nal. The m agnitude of i nput and out pu t volt ages
must neve r exceed -0.3V or VCC+0V
OPERATING CONDITIONS
Symbol Parameter Test conditions Min Typ Max Unit
AVCC Analog Supply voltage 2.25 2.5 2.7 V
DVCC Digital Supply voltage 2.25 2.5 2.7 V
VCCB Digital buffer Supply voltage 2.25 2.5 2.7 V
VREFP Forced top voltage reference 1.16 - AVCC V
VREFM Forced bottom reference voltage 0 0 0.5 V
1)
1)
1)
0 to 3.3 V
0 to 3.3 V
0 to 3.3 V
KV
2
1.5
BLOCK DIAGRAM
VIN
INCM
VINB
CLK
+2.5V
stage stage
1 2
Timing
GND
stage
n
Sequencer-pha s e shifting
Digital data correction
Reference
Buffers
VREFP
circuit
GNDA
IPOL
VREFM
DFSB
OEB
DR
DO
TO
D9
OR
2/19
PIN CONNECTIONS (top view)
index
corner
1
IPOL
VREFP
2
AGND
VIN
AGND
VINB
AGND
INCM
AGND
AVCC
3
4
5
6
7
8
9
10
11
12
VREFM
AGND
AVCC
AVCC
DFSB
OEB
4748 44 43 42 41 40 39 38
46 45
NC
NC
VCCB
GNDB
TSA1001
13 14 15 16 17 18 19 20 21 22
DVCC
DVCC
DGND
CLK
DGND
DGND
GNDB
GNDB
VCCB
23 24
VCCBNCOR
DR
TSA1001
NC
37
NC
36
NC
35
NC
34
33
D0 (LSB)
32
D1
31
D2
30
D3
D4
29
D5
28
D6
27
26
D7
25
D8AVCC
D9 (MSB)
PIN DESCRIPTION
Pin No Name Description Observation Pin No Name Description Observation
1 IPOL Analog bias current input 25 D8 Digi tal output CMOS output (2.5V)
2 VREFP Top voltage reference 1V 26 D7 Digital output CMOS output (2.5V)
3 VREFM Bottom voltage reference 0V 27 D6 Digital output CMOS outpu t (2.5V)
4 AGND Analog ground 0V 28 D5 Digital output CMOS output (2.5V)
5 VIN Analog input 1Vpp 29 D4 Digital output CMOS output (2.5V)
6 AGND Analog ground 0V 30 D3 Digital output CMOS output (2.5V)
7 VINB Inverted analog input 1Vpp 31 D2 Digital output CMOS output (2.5V)
8 AGND Analog ground 0V 32 D1 Digital output CMOS output (2.5V)
9 INCM Input common mode 0.5V 33 D0(LSB) Least Significant Bit output CMOS output (2.5V)
10 AGND Analog ground 0V 34 NC Non connected
1 1 AVCC Analog p ower supply 2.5V 35 NC Non connected
12 AVCC Analog power supply 2.5V 36 NC Non conn ected
13 DVCC Digital power s upply 2. 5V 37 NC Non connected
14 DVCC Digital power supply 2.5V 38 DR Data Ready output CMOS out pu t (2.5V)
15 DGND Digital ground 0V 39 VCCB Digital Buffer power supply 2.5V
16 CLK Clock input 2.5V compatible CMOS input 40 GNDB Digital Buffer ground 0V
17 DGND Digital ground 0V 41 VCCB Digital Buffer power supply 2.5V
18 NC Non connected 42 NC Non connected
19 DGN D Digita l ground 0V 43 NC Non connected
20 GND B Digital buffer ground 0V 44 OEB Output Enable i nput 2.5V compatible CMOS input
21 GNDB Digital buffer ground 0V 45 DFSB Data Format Select input 2.5V compatible CMOS input
22 VCCB Digital buffer power supply 2.5V 46 AVCC Analog power supply 2.5V
23 OR Out Of Range output CMOS output (2.5V) 47 AVCC Analog power supply 2.5V
24 D9(MSB) Most Significant Bit output CMOS output (2.5V) 48 AGND Analog ground 0V
3/19
TSA1001
ELECTRICAL CHARACTERISTICS
AVCC = DVCC = VCCB = 2.5V, Fs= 25Msps, Fin=1MHz, Vin@ -1.0dBFS, VREFM = 0V
Tamb = 25°C (unless otherwise specified)
TIMING CHARACTERISTICS
Symbol Parameter Test conditions Min Typ Max Unit
FS Sampling Frequency 0.5 25 MHz
DC Clock Duty Cycle 45 50 55 %
TC1 Clock pulse width (high) 18 20 ns
TC2 Clock pulse width (low) 18 20 ns
Tod
Data Output Delay (Fall of Clock
to Data Valid)
Tpd Data Pipeline delay 6.5 cycles
Ton
Toff
Falling edge of OEB to digital
output valid data
Rising edge of OEB to digital
output tri-state
10pF load capacitance
5ns
1ns
1ns
TIMING DIAGRAM
N-1
CLK
OEB
Tod
DATA
OUT
DR
N-8
N+4
N+3
N+2
N-7
N+1
N-6
N-5
6.5 clk cycles
N-4
N
Toff
N+5
N-2N-3
N+6
N+7
N+8
Ton
N
N+1
HZ state
4/19
TSA1001
CONDITIONS:
AVCC = DVCC = VCCB = 2.5V, Fs= 25Msps, Fin= 1MHz, Vin@ -1.0dBFS, VREFM= 0V
Tamb = 25°C (unless otherwise specified)
ANALOG INPUTS
Symbol Parameter Test conditions Min Typ Max Unit
VIN-VINB Full scale refere nce voltag e 2.0 Vpp
Cin Input capacitance 7. pF
BW Analog Input Bandwitdh Vin@Full Scale, FS=25Msps 100 MHz
ERB
1). See parameters defini t i o n for more information
Effective Resolution Bandwidth
REFERENCE VOLTAGE
Symbol Parameter Test conditions Min Typ Max Unit
1)
60 MHz
VREFP Top internal reference voltage
Tmin= -40°C to Tmax= 85°C
1)
0.90 1.16 V
1.20 1.27 1.35 V
0.91 1.03 1.15 V
Vpol Analog bias voltage
Tmin= -40°C to Tmax= 85°C
1)
1.19 1.36 V
Ipol Analog bias current Normal operating mode 25 50 70 µA
Ipol Analog bias current Shutdown mode 0 µA
0.48 0.57 0.65 V
VINCM Input common mode voltage
Tmin= -40°C to Tmax= 85°C
1). Not fully tes ted over the te m perature range. Guaranted by sampling.
1)
0.48 0.66 V
5/19
TSA1001
CONDITIONS:
AVCC = DVCC = VCCB = 2.5V, Fs= 25Msps, Fin= 1MHz, Vin@ -1.0dBFS, VREFP=1V, VREFM= 0V
Tamb = 25°C (unless otherwise specified)
POWER CONSUMPTION
Symbol Parameter Test conditions Min Typ Max Unit
1)
ICCA Analog Supply current
Tmin= -40°C to Tmax= 85°C
1)
ICCD Digital Supply Current
Tmin= -40°C to Tmax= 85°C
1)
ICCB Digital Buffer Supply Current
Tmin= -40°C to Tmax= 85°C
ICCBZ
PdZ
Rthja
Rthjc
1).Rpol= 25KΩ. E quiva l en t l oad: Rloa d= 470Ω and Cload= 6pF
2). Not fully tes ted over the te m perature range. Guaranted by sampling.
Digital Buffer Supply Current in
High Impedance Mode
Power consumption in normal
Pd
operation mode
Power consumption in High
Impedance mode
Junction-ambient thermal resistor (TQFP48)
Junction-case thermal resistor
(TQFP48)
1)
1)
Tmin= -40°C to Tmax= 85°C
1)
DIGITAL INPUTS AND OUTPUTS
1 1.8 14 mA
2)
14 mA
12mA
2)
2mA
1.4 5 mA
2)
5mA
40 100 µA
35 47 mW
2)
47 mW
32 37 mW
80 °C/W
18 °C/W
Symbol Parameter Test conditions Min Typ Max Unit
Digital inputs
VIL Logic "0" voltage 0.8 V
VIH Logic "1" voltage 2.0 V
Digital Outputs
VOL Logic "0" voltage Iol=10µA 0.4 V
VOH Logic "1" voltage Ioh=10µA 2.4 V
IOZ High Impedance leakage current OEB set to VIH -1.5 1.5 µA
C
Output Load Capacitance 15 pF
L
ACCURACY
Symbol Parameter Test conditions Min Typ Max Unit
OE Offset Error -5 ±0.1 +5 %
DNL Differential Non Linearity -0.7 ±0.3 +0.7 LSB
INL Integral Non Linear ity -0.8 ±0.3 +0.8 LSB
Monotonicity and no missing
6/19
codes
Guaranted
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