The TS487 2 i s an Audio Pow er Amplifier capable
of delivering 1W of continuous RMS Ouput Power
into 8
Ω load @ 5V.
This Audio Am plifier is exhibiting 0.1% distortion
level (THD) from a 5V supply for a Pout = 250mW
RMS. An external standby mode cont rol reduces
the supply current to less than 10n A. An internal
shutdown protection is provided.
PIN CONNECTIONS (Top View)
TS4872IJT - FLIP CHIP
8
Vout1
76
+
Vin
Vin
12
Vcc
GND
5
STDBY
Vout2
BYPASS
3
4
The TS4872 has been designed for high quality
audio applications such as m obile phones and t o
minimize the number of external components.
The unity-gain stable amplifier can be configured
by external gain setting resistors.
APPLICATIONS
■Mobile Phones (Cellular / Cordless)
■PDAs
■Laptop/Notebook computers
■Portable Audio Devices
ORDER CODE
Part
Number
Temperature
Range
TS4872IJT-40, +85°C●YW4872
J = Flip Chip Package - only available in Tape & Reel (JT)
October 2002
Package
Marking
J
TYPICAL APPLICATION SCHEMATIC
Cfeed
Vcc
Rfeed
6
Audio
Input
Vcc
Rstb
Rin
1
Vin-
Cin
Vin+
7
Bypass
3
Standby
5
Cb
Vcc
-
+
Bias
GND
2
Av=-1
+
Vout1
Vout2
TS4872
Cs
8
RL
8 Ohm
4
1/29
TS4872
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
T
T
R
Supply voltage
CC
V
Input Voltage
i
Operating Free Air Temperature Range-40 to + 85°C
oper
Storage Temperature-65 to +150°C
stg
T
Maximum Junction Temperature150°C
j
Flip Chip Thermal Resistance Junction to Ambient
thja
PdPower DissipationInternally Limited
ESDHuman Body Model2kV
ESDMachine Model200V
Latch-up Latch-up ImmunityClass A
Lead Te mpera ture (solde ring, 10sec )250°C
1. All voltages values are measured with respect to the ground pin.
2. The magnitude of input signal must never exceed V
3. Device is protected in cas e of over temperature by a thermal shutdown active @ 150°C
1. Standby mode i s actived when Vstdby is tied to Vcc
2. Dynamic measurements - 20*log(r m s(Vout)/rms(Vripple)). Vripple is the surim posed sinus signal to Vc c @ f = 217Hz
V
= +3.3V, GND = 0V, T
CC
Supply Current
CC
No input signal, no load
Standby Current
No input signal, Vstdby = Vcc, RL = 8
Output Offset Voltage
No input signal, RL = 8
Output Power
THD = 1% Max, f = 1kHz, RL = 8
Total Harmonic Distortion + Noise
Po = 250mW rms, Gv = 2, 20Hz < f < 20kHz, RL = 8
Power Supply Rejection Ratio
f = 217Hz, RL = 8
Phase Margin at Unity Gain
M
R
= 8Ω, CL = 500pF
L
Gain Margin
R
= 8Ω, CL = 500pF
L
Gain Bandwidth Product
R
= 8
Ω
L
1)
Ω
Ω
Ω
2)
RFeed = 22K
Ω,
= 25°C (unless otherwise specified)
amb
Vripple = 200mV rms
Ω,
68mA
101000nA
520mV
1W
Ω
0.1%
75dB
70Degrees
20dB
2MHz
3)
SymbolParameterMin.Typ.Max.Unit
I
I
STANDBY
Voo
Po
THD + N
PSRR
Φ
GM
GBP
1. Standby mode i s actived when Vstdby is tied to Vcc
2. Dynamic measurements - 20*log(r m s(Vout)/rms(Vripple)). Vripple is the surim posed sinus signal to Vc c @ f = 217Hz
All electrical values are made by correlatio n bet ween 2.6v and 5v measurem ents
3
Supply Current
CC
No input signal, no load
Standby Current
No input signal, Vstdby = Vcc, RL = 8
Output Offset Voltage
No input signal, RL = 8
Output Power
THD = 1% Max, f = 1kHz, RL = 8
Total Harmonic Distortion + Noise
Po = 250mW rms, Gv = 2, 20Hz < f < 20kHz, RL = 8
Power Supply Rejection Ratio
f = 217Hz, RL = 8
Phase Margin at Unity Gain
M
R
= 8Ω, CL = 500pF
L
Gain Margin
= 8Ω, CL = 500pF
R
L
Gain Bandwidth Product
= 8
R
Ω
L
5.58mA
1)
Ω
Ω
Ω
Ω
2)
RFeed = 22KΩs, Vripple = 100mV rms
Ω,
101000nA
520mV
450mW
0.1%
68dB
70Degrees
20dB
2MHz
3/29
TS4872
ELECTRICAL CHARACTERISTICS
V
= 2.6V, GND = 0V, T
CC
SymbolParameterMin.Typ.Max.Unit
= 25°C (unless otherwise specified)
amb
I
CC
I
STANDBY
Voo
Po
THD + N
PSRR
Φ
GM
GBP
1. S ta ndby mode is actived when Vstdby is tied to Vcc
2. Dy namic measurements - 20*log(r m s(Vout)/rms(Vripple)). Vripple is the surim posed sinus signal to Vc c @ f = 217Hz
= 2.2V, GND = 0V, T
V
CC
Supply Current
No input signal, no load
Standby Current
1)
No input signal, Vstdby = Vcc, RL = 8
Output Offset Voltage
No input signal, RL = 8
Output Power
THD = 1% Max, f = 1kHz, RL = 8
Total Harmonic Distortion + Noise
Po = 200mW rms, Gv = 2, 20Hz < f < 20kHz, RL = 8
Power Supply Rejection Ratio
f = 217Hz, RL = 8
Phase Margin at Unity Gain
M
R
= 8Ω, CL = 500pF
L
Gain Margin
R
= 8Ω, CL = 500pF
L
Gain Bandwidth Product
R
= 8
Ω
L
amb
Ω
Ω
Ω
Ω
2)
RFeed = 22K
Ω,
Vripple = 200mV rms
Ω,
= 25°C (unless otherwise specified)
5.58mA
101000nA
520mV
260mW
0.1%
75dB
70Degrees
20dB
2MHz
SymbolParameterMin.Typ.Max.Unit
I
CC
I
STANDBY
Voo
Po
THD + N
PSRR
Φ
GM
GBP
1. S ta ndby mode is actived when Vstdby is tied to Vcc
2. Dy namic measurements - 20*log(r m s(Vout)/rms(Vripple)). Vripple is the surim posed sinus signal to Vc c @ f = 217Hz
Supply Current
No input signal, no load
Standby Current
1)
No input signal, Vstdby = Vcc, RL = 8
Output Offset Voltage
No input signal, RL = 8
Output Power
THD = 1% Max, f = 1kHz, RL = 8
Total Harmonic Distortion + Noise
Po = 200mW rms, Gv = 2, 20Hz < f < 20kHz, RL = 8
Power Supply Rejection Ratio
f = 217Hz, RL = 8
Phase Margin at Unity Gain
M
R
= 8Ω, CL = 500pF
L
Gain Margin
R
= 8Ω, CL = 500pF
L
Gain Bandwidth Product
R
= 8
Ω
L
Ω
2)
RFeed = 22K
Ω,
Ω
Ω
Vripple = 100mVpp
Ω,
4.5mA
10nA
2mV
180mW
Ω
0.1%
75dB
70Degrees
20dB
2MHz
4/29
ComponentsFunctional Description
TS4872
Rin
Cin
RfeedFeed back resistor which sets the closed loop gain in conjunction with Rin
CsSupply Bypass capacitor which provides power supply filtering
CbBypass pin capacitor which provides half supply filtering
Cfeed
RstbPull-up resistor which fixes the right supply level on the standby pin
GvClosed loop gain in BTL configuration = 2 x (Rfeed / Rin)
Inverting input resistor which sets the closed loop gain in conjunction with Rfeed. This resistor also
forms a high pass filter with Cin (fc = 1 / (2 x Pi x Rin x Cin))
Input coupling capacitor which blocks the DC voltage at the amplifier input terminal
Low pass filter capacitor allowing to cut the high frequency
(low pass filter cut-off frequency 1 / (2 x Pi x Rfeed x Cfeed))
REMARKS
1. All measurements, except PSRR measurements, are made with a supply bypass capacitor Cs = 100µF.
2. External resistors are not needed for having better stability when supply @ Vcc down to 3V. By the