The TS487 1 i s an Audio Pow er Amplifier capable
of delivering 1W of continuous RMS Ouput Power
into 8
Ω load @ 5V.
This Audio Am plifier is exhibiting 0.1% distortion
level (THD) from a 5V supply for a Pout = 250mW
RMS. An external standby mode cont rol reduces
the supply current to less than 10n A. An internal
thermal shutdown protection is also provided.
The TS4871 has been designed for high quality
audio applications such as m obile phones and t o
minimize the number of external components.
The unity-gain stable amplifier can be configured
by external gain setting resistors.
PIN CONNECTIONS (Top View)
TS4871IST - MiniSO8
8
7
6
5
8
7
6
5
V
V
8
8
OUT 2
OUT 2
7
7
GND
GND
6
6
Vcc
Vcc
V
V
5
5
IN
VIN-
1
2
3
4
Standby
Bypass
V+
TS4871ID-TS4871IDT - SO8
V+
IN
VIN-
1
2
3
4
Standby
Bypass
TS4871IQT - DFN8
STANDBY
STANDBY
BYPASS
BYPASS
V
V
V
V
1
1
2
2
3
3
IN+
IN+
4
4
IN-
IN-
V2OUT
GND
CC
V
VOUT1
V2OUT
GND
V
VOUT1
OUT 1
OUT 1
CC
APPLICATIONS
■Mobile Phones (Cellular / Cordless)
■Laptop / Notebook Computers
■PDAs
■Portable Audio Devices
ORDER CODE
Part
Number
Temperature
Range: I
TS4871-40, +85°C
MiniSO & DFN only available in Tape & Reel with T suffix(IST & IQT)
D = Small Outline Package (SO) - also available in Tape & Reel (DT)
June 2003
Package
DSQ
•
••
Marking
4871I
4871
TYPICAL APPLICATION SCHEMATIC
Cfeed
Vcc
Rfeed
6
Audio
Input
Vcc
Rstb
Rin
4
Vin-
Cin
Vin+
3
Bypass
2
Standby
1
Cb
Vcc
-
+
Av=-1
+
Bias
GND
7
Vout1
Vout2
TS4871
Cs
5
RL
8 Ohms
8
1/28
TS4871
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
T
T
R
Supply voltage
CC
V
iInput Voltage
Operating Free Air Temperature Range-40 to + 85°C
oper
Storage Temperature-65 to +150°C
stg
T
Maximum Junction Temperature150°C
j
Thermal Resistance Junction to Ambient
thja
SO8
MiniSO8
QNF8
PdPower Dissipation
ESDHuman Body Model2kV
ESDMachine Model200V
Latch-up Latch-up ImmunityClass A
Lead Temperature (soldering, 10sec)260°C
1. All voltages values are measured with respect to the ground pin.
2. The magnitude of input signal must never exceed V
3. Device is protected in case of over temperature by a thermal shutdown active @ 150°C.
4. Exceeding the power derating curves during a long period, involves abnormal operating condition.
1)
2)
3)
6V
GND to V
CC
175
215
70
4)
+ 0.3V / GND - 0.3V
CC
Internally Limited
V
°C/W
OPERATING CONDITIONS
SymbolParameterValueUnit
V
V
V
R
1. This thermal resistance can be reduced with a suitable PCB layout (see Power Derating Curves Fig. 20)
2. When mounted o n a 4 l ayers PCB
Supply Voltage2.5 to 5.5V
CC
to VCC - 1.2V
Common Mode Input Voltage Range
ICM
G
ND
Standby Voltage Input :
≤ V
STB
Device ON
Device OFF
R
Load Resistor4 - 32
L
Thermal Resistance Junction to Ambient
thja
SO8
1)
MiniSO8
2)
DFN8
G
V
- 0.5V ≤ V
CC
ND
STB
150
190
41
≤ 0.5V
STB
≤ V
CC
V
V
Ω
°C/W
2/28
TS4871
ELECTRICAL CHARACTERISTICS
= +5V, GND = 0V, T
V
CC
SymbolParameterMin.Typ.Max.Unit
= 25°C (unless otherwise specified)
amb
I
CC
I
STANDBY
Voo
Po
THD + N
PSRR
Φ
GM
GBP
1. Standby mode i s actived when Vstdby is tied to Vcc
2. Dynamic measurements - 20*log(r m s(Vout)/rms(Vripple)). Vripple is the surim posed sinus signal to Vc c @ f = 217Hz
= +3.3V, GND = 0V, T
V
CC
Supply Current
No input signal, no load
Standby Current
1)
No input signal, Vstdby = Vcc, RL = 8
Output Offset Voltage
No input signal, RL = 8
Output Power
THD = 1% Max, f = 1kHz, RL = 8
Total Harmonic Distortion + Noise
Po = 250mW rms, Gv = 2, 20Hz < f < 20kHz, RL = 8
Power Supply Rejection Ratio
f = 217Hz, RL = 8
Phase Margin at Unity Gain
M
R
= 8Ω, CL = 500pF
L
Gain Margin
R
= 8Ω, CL = 500pF
L
Gain Bandwidth Product
R
= 8
Ω
L
amb
Ω
Ω
Ω
Ω
2)
RFeed = 22K
Ω,
Vripple = 200mV rms
Ω,
= 25°C (unless otherwise specified)3)
68mA
101000nA
520mV
1W
0.15%
75dB
70Degrees
20dB
2MHz
SymbolParameterMin.Typ.Max.Unit
I
CC
I
STANDBY
Voo
Po
THD + N
PSRR
Φ
GM
GBP
1. Standby mode i s actived when Vstdby is tied to Vcc
2. Dynamic measurements - 20*log(r m s(Vout)/rms(Vripple)). Vripple is the surim posed sinus signal to Vc c @ f = 217Hz
3. All electrical values are made by correlation between 2.6V and 5V measurement s
Supply Current
No input signal, no load
Standby Current
1)
No input signal, Vstdby = Vcc, RL = 8
Output Offset Voltage
No input signal, RL = 8
Output Power
THD = 1% Max, f = 1kHz, RL = 8
Total Harmonic Distortion + Noise
Po = 250mW rms, Gv = 2, 20Hz < f < 20kHz, RL = 8
Power Supply Rejection Ratio
f = 217Hz, RL = 8
Phase Margin at Unity Gain
M
R
= 8Ω, CL = 500pF
L
Gain Margin
R
= 8Ω, CL = 500pF
L
Gain Bandwidth Product
R
= 8
Ω
L
Ω
2)
RFeed = 22K
Ω,
Ω
Ω
Vripple = 200mV rms
Ω,
5.58mA
101000nA
520mV
450mW
Ω
0.15%
75dB
70Degrees
20dB
2MHz
3/28
TS4871
ELECTRICAL CHARACTERISTICS
= 2.6V, GND = 0V, T
V
CC
SymbolParameterMin.Typ.Max.Unit
= 25°C (unless otherwise specified)
amb
I
CC
I
STANDBY
Voo
Po
THD + N
PSRR
Φ
GM
GBP
1. Standby mode i s actived when Vstdby is tied to Vcc
2. Dynamic measurements - 20*log(r m s(Vout)/rms(Vripple)). Vripple is the surim posed sinus signal to Vc c @ f = 217Hz
Supply Current
No input signal, no load
Standby Current
1)
No input signal, Vstdby = Vcc, RL = 8
Output Offset Voltage
No input signal, RL = 8
Output Power
THD = 1% Max, f = 1kHz, RL = 8
Total Harmonic Distortion + Noise
Po = 200mW rms, Gv = 2, 20Hz < f < 20kHz, RL = 8
Power Supply Rejection Ratio
f = 217Hz, RL = 8
Phase Margin at Unity Gain
M
R
= 8Ω, CL = 500pF
L
Gain Margin
R
= 8Ω, CL = 500pF
L
Gain Bandwidth Product
R
= 8
Ω
L
Ω
2)
RFeed = 22K
Ω,
Ω
Ω
Vripple = 200mV rms
Ω,
5.58mA
101000nA
520mV
260mW
Ω
0.15%
75dB
70Degrees
20dB
2MHz
ComponentsFunctional Description
Rin
Inverting input resistor which sets the closed loop gain in conjunction with Rfeed. This resistor also
forms a high pass filter with Cin (fc = 1 / (2 x Pi x Rin x Cin))
CinInput coupling capacitor which blocks the DC voltage at the amplifier input terminal
RfeedFeed back resistor which sets the closed loop gain in conjunction with Rin
CsSupply Bypass capacitor which provides power supply filtering
CbBypass pin capacitor which provides half supply filtering
Cfeed
Low pass filter capacitor allowing to cut the high frequency
(low pass filter cut-off frequency 1 / (2 x Pi x Rfeed x Cfeed))
RstbPull-up resistor which fixes the right supply level on the standby pin
GvClosed loop gain in BTL configuration = 2 x (Rfeed / Rin)
REMARKS
1. All measurements, except PSRR measurements, are made with a supply bypass capacitor Cs = 100µF.
2. External resistors are not needed for having better stability when supply @ Vcc down to 3V. By the way,
Fig. 69 : Signal to Noise Ratio vs Power Supply
with Unweighted Filter (20Hz to 20kHz)
100
90
RL=4
RL=8
RL=16
80
70
SNR (dB)
60
50
2.53.03.54.04.55.0
Ω
Ω
Vcc (V)
Ω
Gv = 2
Cb = Cin = 1µF
THD+N < 0.4%
Tamb = 25°C
Fig. 71 : Signal to Noise Ratio vs Power Supply
with Weig h t e d Filt e r t y p e A
110
100
RL=4
RL=8
RL=16
90
Ω
Ω
Ω
Fig. 70 : Signal to Noise Ratio vs Power Supply
with Weighted Filter Type A
Fig. 72 : Current Consum ption vs Power
Supply Voltage
80
SNR (dB)
70
60
2.53 .03.54.04.55.0
Vcc (V)
Fig. 73 : Signa l to Nois e Ratio Vs Power Supply
with Unweighted Filter (20Hz to 20kHz)
90
80
70
SNR (dB)
60
50
RL=16
2.53 .03.54.04.55.0
RL=4
Ω
Ω
Vcc (V)
Gv = 2
Cb = Cin = 1µF
THD+N < 0.4%
Tamb = 25°C
RL=8
Ω
Gv = 10
Cb = Cin = 1µF
THD+N < 0.7%
Tamb = 25°C
Fig. 74 : C urrent Consumption vs Standby
Voltage @ Vcc = 5V
17/28
TS4871
0.00.51.01.52.02.53.0
0
1
2
3
4
5
6
Vcc = 3.3V
Tamb = 25°C
Icc (mA)
Vstandby (V)
2.53.03.54.04.55.0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Tamb = 25°C
RL = 16
Ω
RL = 8
Ω
RL = 4
Ω
Vout1 & Vout2
Clipping Voltage Low side (V)
Power supply Voltage (V)
Fig. 75 : C urrent Consumption vs Standby
Voltage @ Vcc = 2.6V
6
5
4
3
Icc (mA)
2
1
0
0.00.51.01.52.02.5
Vstandby (V)
Vcc = 2.6V
Tamb = 25°C
Fig. 77 : Clipping Voltage vs Power Supply
Voltage and Load Resistor
1.0
0.9
Tamb = 25°C
0.8
0.7
0.6
0.5
0.4
Vout1 & Vout2
0.3
0.2
Clipping Voltage High side (V)
0.1
0.0
2.53.03.54.04.55.0
RL = 8
Ω
Power supply Voltage (V)
RL = 4
RL = 16
Ω
Ω
Fig. 76 : C urrent Consumption vs Standby
Voltage @ Vcc = 3.3V
Fig. 78 : Clipping Voltage vs Power Supply
Voltage and Load Resistor
Fig. 79 : Vout1+Vout2 Unweighted Noise Floor
120
Vcc = 2.5V to 5V, Tamb = 25 C
Cb = Cin = 1 F
100
Input Grounded
BW = 20Hz to 20kHz (Unweighted)
80
60
40
Output Noise Voltage ( V)
20
0
18/28
20
Standby mode
100100010000
Frequency (Hz)
Fig. 80 : V out1+Vout2 A-weighted Noise Floor
120
Vcc = 2.5V to 5V, Tamb = 25 C
Cb = Cin = 1 F
100
Input Grounded
Av = 10
Av = 2
BW = 20Hz to 20kHz (A-Weighted)
80
60
40
20
Standby mode
100100010000
Output Noise Voltage ( V)
20
0
Av = 10
Av = 2
Frequency (Hz)
APPLICA TI ON INFORMATION
Fig. 81 : Demoboard Schematic
TS4871
C1
R2
C2
R1
Vcc
C6
100µ
6
4
Vin-
Vin+
3
R6
Bypass
2
Standby
1
+
C12
C8
1u
Vcc
-
+
Bias
GND
7
Vcc
GND
Neg. input
P1
Pos input
P2
Vcc
S1
S2
C3
R3
C5
C11
Vcc
R8
D1
PW ON
S8
Standby
R4
C4R5
S5
PositiveInput mode
Vcc
R7
330k
Fig. 82 : SO8 & MiniSO8 Demoboard Components Side
C7
+
100n
S6
OUT1
S3
GND
S4
GND
S7
Av=-1
+
Vout1
Vout2
TS4871
5
8
C9
+
470µ
C10
+
470µ
19/28
TS4871
Fig. 83 : SO8 & MiniSO8 Demoboard Top
Solder Layer
Fig. 84 :
Layer
SO8 & MiniSO8 Demoboard Bottom Solder
The output power is:
2
)Vout2(
Pout
=
RMS
R
L
)W(
For the same power supply voltage, the output
power in BTL configuration is four times higher
than the output power in single ended
configuration.
■Gain In Typical Application Schematic
(see page 1)
In flat region (no effect of Cin), the output voltage
of the first stage i s:
Vout1 = Vin –
For the second stage : Vout2 = -Vout1 (V)
The differential output voltage is:
Vout2
V o ut 1 = 2Vin –
Rfeed
------------------- - (V)
Rin
Rfeed
------------------- - (V)
Rin
■BTL Configuration Principle
The TS4871 is a monolithic power amplifier with a
BTL output type. BTL (Bridge Tied Load) means
that each end of the load is connected to two
single ended output amplifiers. Thus, we have :
Single ended output 1 = Vout1 = Vout (V)
Single ended output 2 = Vout2 = -Vo ut (V)
And Vout1 - Vout2 = 2Vout (V)
The differential gain named gain (Gv) for more
convenient usage is:
Vout2Vout1–
Gv =
--------------------------------------- = 2
Vin
Rfeed
------------------- Rin
Remark : Vout2 is in phase with Vin and Vout1 is
180 phased with Vin. It means that the positive
terminal of the l oudspeaker should be connected
to Vout2 and the negative to Vout1.
■Low and high frequency response
In low frequency region, the effect of Cin starts.
Cin with Rin forms a high pass filter with a -3dB cut
off frequency.
CL =
F
In high frequency region, you can limit the
bandwidth by adding a capacitor (Cfeed) in
parallel on Rfeed. Its form a l ow pass filter with a
• Supply voltage is a pure DC source (Vcc)
Regarding the load we have:
OUT = V
V
and
OUT =
I
and
P
OUT =
Then, the average current delivered by the supply
voltage is:
CC
I
AVG
= 2
sinωt (V)
PEAK
OUT
V
---------------- - (A)
L
R
2
PEAK
V
---------------------- (W)
L
2R
PEAK
V
-------------------- (A)
L
πR
The maximum theoret ical value is reached when
Vpeak = Vcc, so
π
----- = 78. 5%
4
■Decoupl i ng of the ci rc u it
Two capacitors are needed to bypass properly the
TS4871, a power supply bypass capacitor Cs and
a bias voltage bypass capacitor Cb.
Cs has especially an influence on the THD+N in
high frequency (above 7kHz) and indirectly on the
power supply disturbances.
With 100µF, you can expect similar THD+N
performances like shown in the datasheet.
If Cs is lower than 100µF, in high frequency
increases, THD+N and disturbances on the power
supply rail are less filtered.
To the contrary, if Cs is higher than 100µF, those
disturbances on the power supply rail are more
filtered.
Cb has an influence on THD+N in lower frequency,
but its function is critical on the final result of PSRR
with input grounded in lower frequency.
The power delivered by the supply voltage is
Psupply = Vcc Icc
AVG
(W)
Then, the po wer dissip ated by the amplifier is
Pdiss = Psupply - Pout (W)
22Vcc
diss =
P
---------------------- P OUTPOUT (W)–
πR
L
and the maximum value is obtained when:
∂Pdiss
--------------------- - = 0
OUT
∂P
and its value is:
Remark : This maximum valu e is only depending
on power supply voltage and load values.
The efficiency is the ratio between the output
power and the power supply
η =
P
OUT
----------------------- - =
Psupply
πV
PEAK
----------------------4VCC
If Cb is lower than 1µF, T HD+N increase in lower
frequency (see THD+N vs frequency curves) and
the PSRR worsens up
If Cb is higher than 1µF, the benefit on THD+N in
lower frequency is small but the ben efit on PSRR
is substantial (see PSRR vs. Cb curve : fig.12).
Note that Cin has a non-negligible effect on PSRR
in lower frequency. Lower is its value, higher is the
PSRR (see fig. 13).
■Pop and Click performance
Pop and Click performance is intimately linked
with the size of the input capacitor Cin and the bias
voltage bypass capacitor Cb.
Size of Cin is du e to the lower cut-off frequency
and PSRR value requested. Size of Cb is due to
THD+N and PSRR requested always in lower
frequency.
Moreover, Cb determines the speed that the
amplifier turns ON. The slower th e speed is, the
softer the turn ON noise is.
The charge time of Cb is directly proportional to
21/28
TS4871
the internal generator resistance 50kΩ.
Then, the charge time constant for Cb is
τb = 50kΩxCb (s)
As Cb is directly connected to the non-inverting
input (pin 2 & 3) and if we want to minimize, i n
amplitude and duration, the output spike on Vout1
(pin 5), Cin must be charged faster than Cb. T he
charge time constant of Cin is
τin = (Rin+Rfeed)xCin (s)
Thus we have the relation
τin << τb (s)
The respect of this relation permits to minimize the
pop and click noise.
Remark
: Minimize Cin and Cb has a benefit on
pop and click phenomena but also on cost and
size of the application.
Example
: your target for the -3dB cut off
frequency is 100 Hz. With Rin=Rfeed=22 kΩ,
Cin=72nF (in fact 82nF or 100nF).
With Cb=1µF, if you choose the one of the latest
two values of Cin, the pop and click phenomena at
power supply ON or standby function ON/OFF will
be very small
50 kΩx1µF >> 44kΩx100nF (50ms >> 4.4ms).
Increasing Cin value increas es the pop and click
phenomena to an unpleasant sound at power
supply ON and standby function ON/OFF .
t
DischCs =
5Cs
------------- - = 83 ms
Icc
Now, we must consider the discharge time of Cb.
At power OFF or standby ON, Cb is discharged by
a 100kΩ resistor. So the discharge time i s about
τb
≈ 3xCbx100kΩ (s).
Disch
In the majority of application, Cb=1µF, then
τb
Disch
≈300ms >> t
dischCs
.
■Power amplifier design examples
Given :
• Load impedance : 8Ω
• Output power @ 1% THD+N : 0.5W
• Input impedance : 10kΩ min.
• Input voltage peak to peak : 1Vpp
• Bandwidth frequency : 20Hz to 20kHz (0, -3dB)
• Ambient temperature max = 50°C
• SO8 package
First of all, we must cal culate t he m inimum p ower
supply voltage to obtain 0.5W into 8Ω. With curves
in fig. 15, we can read 3.5V. Thus, the power
supply voltage value min. will be 3.5V.
Following the maximum power dissipation
equation
2
Vcc2
=
maxPdiss
2
π
R
)W(
L
Why Cs is not important in pop and click
consideration ?
Hypothesis :
• Cs = 100µF
• Supply voltage = 5V
• Supply voltage internal resistor = 0.1Ω
• Supply current of the amplifier Icc = 6mA
At power ON of the supply, the supply capacitor is
charged through the internal power supply
resistor. So, to reach 5V you need about five to ten
times the charging time constant of Cs (τs =
0.1xCs (s)).
Then, this time equal 50µs to 100µs << τb in the
majority of application.
At power OFF of the supply, Cs is discharged by a
constant current Icc. The di scharge time from 5V
to 0V of Cs is:
22/28
with 3.5V we have Pdissmax=0.31W.
Refer to power derating curves (fig. 20), with
0.31W the maxim um ambien t temperature will be
100°C. This last value could be higher if you follow
the example layout shown on the demoboard
(better dissipation).
We have Rin > 10kΩ. Let's take Rin = 10kΩ, then
Rfeed = 28.25kΩ. We could use for Rfeed = 30kΩ
in normalized value and th e gain will be Gv = 6.
In lower frequency we want 20 Hz (-3dB cut off
frequency). Then:
So, we cou ld use for Cin a 1µF capacitor value
TS4871
C
IN =
1
------------------------------ = 795nF
2π
RinFCL
which gives 16Hz.
In Higher frequency we want 20k Hz (-3dB cut off
frequency). The Gain Bandwidth Product of the
TS4871 is 2MHz typical and doesn’t change when
the amplifier delivers power into the load.
The first amplifier has a gain of:
Rfeed
----------------- = 3
Rin
and the theoretical value of the -3dB cut-off higher
frequency is 2MHz/3 = 660kHz.
We can keep this value or limit the bandwidth by
adding a capacitor Cfeed, in parallel on Rfeed.
Then:
C
FEED =
1
-------------------------------------- - = 265pF
FEEDFCH
2π R
So, we could use for Cfeed a 220pF capacitor
value that gives 24kHz.
Now, we can calculate the value of Cb with the
formula τb = 50kΩxCb >> τin = (Rin+Rfee d)xCin
which permits to redu ce t he po p and click effects.
Then Cb >> 0.8µF.
We can choose for Cb a normalized value of 2.2µF
that gives good results in THD+N and PSRR.
In the following tables, you could find three
another examples with values required for the
demoboard.
Remark : components with (*) marking are
optional.
Application n°1 : 20Hz to 20kHz bandwidth and
6dB gain BTL power amplifier.
We have finished a design and we have ch osen
the components values :
• Rin=Rfeed=22kΩ
• Cin=100nF
• Cb=1µF
Now, on fig. 13, we can see the PSRR (input
grounded) vs frequency curves. At 217Hz we have
a PSRR value of -36dB.
In reality we want a value about -70dB. So, we
need a gain of 34dB !
Now, on fig. 12 we can see the effect of Cb on the
PSRR (input grounded) vs. frequency. With
Cb=100µF, we can reach the -70dB value.
The process to obtain the final curve (Cb=100µF,
Cin=100nF, Rin=Rfeed=22kΩ) is a simple transfer
point by point on each frequency of the curve on
fig. 13 to the curve on fig. 12. The measurement
result is shown on the next figure.
Fig. 86 : PSRR measurement schematic
Rfeed
Vripple
Vcc
Cin
Rg
100 Ohms
4
Vin-
Vin+
3
Rin
Bypass
2
Standby
1
Cb
6
Vcc
-
+
Av=-1
+
Bias
GND
7
Vout1
Vout2
TS4871
5
Vs-
RL
8
Vs+
■Principle of operation
• We fixed the DC voltage supply (Vcc), the AC
sinusoidal ripple voltage (Vripple) and no supply
capacitor Cs is used
The PSRR is the Power Suppl y Rejection Ratio.
It's a kind of SVR in a determined frequency range.
The PSRR of a device, is the ratio between a
power supply disturbance and the result on the
output. We can say that the PSRR is the ability of
a device to m inimize the impact o f power supply
disturbances to the output.
How do we measure the PSRR
?
PSRR d B() = 20 x Log10
Rms V
---------------------------------------- ----Rms Vs
ripple()
- Vs
()
+
-
Remark : The measure of the Rms voltage is not a
Rms selective measure but a full range (2 Hz to
125 kHz) Rms measure. It means that we
measure the effective Rms signal + the noise.
■High/low cut-off frequencies
For their calculation, please check this "Frequency
Response Gain vs Cin, & Cfeed" graph:
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