SGS Thomson Microelectronics TDA9206 Datasheet
I2C BUS CONTROLLED 130MHz RGB PREAMPLIFIER
.
130MHz TYPICAL BANDWIDTH AT 2V
OUTPUTWITH12pF CAPACITIVELOAD
.
2.8ns TYPICAL RISE/FALL TIME AT 2V
OUTPUTWITH12pF CAPACITIVELOAD
.
POWERFULLOUTPUTDRIVE CAPABILITY
.
BRT, CONT, DRIVE, OUTPUT DC LEVEL,
OSD CONTRAST, BACK-PORCH CLAMPING
PULSE WIDTH ARE I
.
INTERNAL BACK-PORCH CLAMPING
PULSE GENERATOR
.
OSD WHITE BALANCETRACKING
.
INTERNAL OSD SWITCHES
.
BLANKINGAND FAST-BLANKING INPUTS
.
VERY LARGE DRIVE ADJUSTMENT RANGE
(48dB)
.
SEMI-TRANSPARENT BACKGROUND ON
OSDPICTURE
2
C BUS CONTROLLED
TDA9206
PP
PP
DIP24
(Plastic Package)
ORDER CODE : TDA9206
DESCRIPTION
The TDA9206 is a digitaly controlled wideband
video preamplifier intendedfor use in high resolution colormonitor.All controlsand adjustmentsare
digitaly performed thanks to I
trast, brightness and DC output level of RGB signals are common to the 3 channels and drive
adjustmentisseparateforeachchannel.ThreeI
gain controlled OSD inputs can be switched with
RGB signalsusingfastblankingcommand.Clamping of RGBsignalsis performedthanksto a flexible
integrated system. The white balance adjustment
is effectiveon brightness, videoand OSDsignals.
TheTDA9206works forapplicationusingACorDC
coupledCRTdriver.
Because of its features and due to component
savingtheTDA9206leadstoaveryperformantand
cost effectiveapplication.
2
C serial bus. Con-
2
C
PIN CONNECTIONS
IN1
OSD1
AV
IN2
OSD2
AGND
IN3
OSD3
LV
LGND
SDA
SCL
DD
DD
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
HSYNC
PV
CC1
OUT1
PGND1
PV
CC2
OUT2
PGND2
PV
CC3
OUT3
PGND3
BLK
FBLK
9206-01.EPS
September 1996
1/12
TDA9206
PIN DESCRIPTION
Name Pin Type Function
IN1 1 I 1
OSD1 2 I 1
AV
3 I 12V Analog V
DD
IN2 4 I 2ndChannel Main Picture Input
OSD2 5 I 2
AGND 6 I/O Analog Ground
IN3 7 I 3
OSD3 8 I 3
LV
9 I 12V Logic V
DD
LGND 10 I/O Logic Ground
SDA 11 I/O Serial Data Line
SCL 12 I Serial Clock Line
BLOCK DIAGRAM
st
Channel Main Picture Input
st
Channel OSD Input
DD
nd
Channel OSD Input
rd
Channel Main Picture Input
rd
Channel OSD Input
DD
Name Pin Type Function
FBLK 13 I Fast Blanking Input
BLK 14 I Blanking Input
rd
PGND3 15 I/O 3
OUT3 16 O 3
PV
17 I 3rdChannel Power V
CC3
Channel Power Ground
rd
Channel Output
CC
PGND2 18 I/O 2ndChannel Power Ground
nd
OUT2 19 O 2
PV
20 I 2ndChannel Power V
CC2
Channel Output
CC
PGND1 21 I/O 1stChannel Power Ground
st
OUT1 22 O 1
PV
23 I 1stChannel Power V
CC1
Channel Output
CC
HSYNC 24 I Horizontal Synch Input
9206-01.TBL
AV
IN1
AGND
IN2
IN3
LV
LGND
DD
DD
3
1
6
4
7
9
10
TDA9206
V
REF
BLUE CHANNEL
GREEN CHANNEL
BPCP
24
LATCHES
I
BUS
DECODER
11 12
CLAMP
2
C
SCLSDAHSYNC
FBLKBLK
CO NTRAST
D/A
OSD
CONT
1314
BRIGHTNESS
2
OSD1 OSD2 OSD3
5
DRIVE
8 bits
8
2
C
I
BPCP
OUTPUT
STAGE
V
REF
PV
CC1
23
OUTPUT
DC LEVEL
ADJUS T
22
21
20
19
18
16
17
15
OUT1
PGND1
PV
CC2
OUT2
PGND2
OUT3
PV
CC3
PGND3
9206-02.EPS
2/12
FUNCTIONAL DESCRIPTION
Input Stage
The R, G and B signals must be fed to the three
inputs through coupling capacitors (100nF).
The maximuminput peak-to-peakvideo amplitude
is 1V.
The inputstage includes a clampingfunction. This
clamp is using the input serialcapacitoras”memory capacitor”and is gatedby an internally generated ”Back-Porch-Clamping-Pulse(BPCP)”.
The synchronizationedge ofthe BPCP is selected
according bit 0 of registerR8.
When B0R8 is set to 1, the BPCP is synchronized
on the leading edge of the blanking pulse BLK
inputs on Pin 14 (see Figure1).
Figure1
BLK
HSYNC
BPCP
Internal pulse width is controlledby I2C
WhenB0R8isclearto0, the BPCPissynchronized
on the secondedgeofthehorizontalpulseHSYNC
inputs on Pin 24. An automatic function allows to
use positiveor negativehorizontal pulse on Pin 24
(see Figure2).
Figure2
HSYNC
BPCP
Internalpulse width is controlled by I2C
2
In both caseBPCP width is adjustable by I
C, B1
and B2 of register R8 (see R8 Table P8).
ContrastAdjustment (8 bits)
The contrast adjustment is made by controlling
simultaneously the gain of three internal variable
gain amplifiers through the I
2
C bus interface.
The contrast adjustment allows to cover a typical
range of 48dB.
BrightnessAdjustment (8 bits)
As for the contrast adjustment, the brightness is
controlledby I
2
C.
The brightness function consists to add the same
DC offsetto the threeR, G,Bsignals after contrast
amplification.
TDA9206
ThisDC-Offsetis presentonly outsidethe blanking
pulse (see Figure 3).
The DC output level during the blanking pulse, is
forced to ”INFRA-BLACK” level (V
Drive Adjustment (3 x 8 bits)
In orderto adjustthe white balance , the TDA9206
offersthe possibilityto adjustseparatelytheoverall
gain of each complete video channel.
The gainof each channelis controlledby I
each).
The verylargedriveadjustmentrange(48dB) allows
differentstandardor customcolortemperature.
It can also be used to adjust the output voltagesat
the optimum amplitude to drive the C.R.T drivers,
keepingthewholecontrastcontrolforend-useronly.
The drive adjustment is located after the CONTRAST, BRIGHTNESSandOSDswitch blocks,so
that the white balance will remains correct when
BRT is adjusted, and will also be correct on OSD
portion of the signal.
OSD Inputs
The TDA9206 includes all the circuitry necessary
9206-04.EPS
tomixOSDsignalsintotheRGBmain-picture.Four
pins are dedicatedto this function as follow.
Three TTL RGB On Screen Display inputs
(Pin 2, 5and 8). Thesethree inputs areconnected
to the three outputs of the corresponding ONSCREEN-DISPLAYprocessor(ex : STV942x).
One Fast Blanking Input (FBLK, Pin 13) which is
also connected to the FBLK output of the same
ON-SCREEN-DISPLAYprocessor.
When a high level is present on FBLK, the IC will
actsas follow :
- The three main picture RGB input signals are
internally switched to the internal input clamp
referencevoltage.
- The three output signals are set to voltages
9206-05.EPS
corresponding to the state (0 or 1) on the three
OSD inputs (see Figure 3).
Example:
If FBLK = 1 and OSD1, OSD2, OSD3) = 1, 0, 1
respectively.
Then OUT1, OUT2, OUT3 will be equal to V
V
BRT,VOSD
where : V
,
BRT=VBLACK
V
OSD=VBRT
+BRT
+OSD
BRTis the brightness DC level I
OSD is the On-Screen Display signal value I
adjustablefrom 0V to 4.68V
PP
Semi-transparent function is controlled thanks to
Bit6 of R8 register(see Table1).
When semi-transparent mode is activated, video
signalis dividedby 2 (CONT).
).
DC
2
2
C adjustable.
by step of 0.312V.
C (8bits
OSD
2
C
3/12
,
TDA9206
FUNCTIONAL DESCRIPTION(continued)
Table1
FBLK OSD1 OSD2 OSD3 B6R8
0 x x x 0 Video
1 x x x 0 OSD (1)
0 x x x 1 Video
10xx1 OSD
1 x 1 x 1 OSD
1 x x 0 1 OSD
1 1 0 1 1 Semi-trans-
Notes : 1. AllOSD colors are displayed.
2. One OSD color is displayed as semi-transparent video
without effect on brightnessand DC level adjustment.
Output Stage
Thethreeoutputstagesincorporatethreefunctions
which are :
- The blankingstage : When high level is applied
to the BLK input (Pin 14), the threeoutputs are
switchedtoa voltagewhichis 400mV lower than
the BLACK level. The black level is the output
voltage with minimum brightness when input
signalvideo amplitudeis equal to ”0”.
- The output stage itself : It is a large bandwidth
output amplifierwhich allow to deliver up to 5V
on the three outputs(for0.7V videosignal on the
inputs).Thetypicalbandwidth is 100MHzat -3dB
measuredwith 4V
output signalon 12pF load.
PP
Figure 3 : WaveformsVOUT, BRT, CONT, OSD
Output
Signal (OUTn)
parent (2)
PP
- The output CLAMP : The IC also incorporates
three internal output clamp (sample and hold
system) which allow to DC shift the three output
signals. The DC output voltage is adjustable
through I
2
C with 4 bits. Practicaly, the DC output
level allow to adjustthe BLKlevel
= 400mV under V
(V
DC
) from 0.9V to 2.9V
BLACK
with 12 x 165mV.
The overall waveforms of the output signal according to the different adjustment are shown in
Figures3 and 4.
Serial Interface
The 2-wiresserial interface is an I
2
C interface.
The slaveaddressof the TDA9206 is DC (in hexadecimal).
A6 A5 A4 A3 A2 A1 A0 W
11011100
Data Transfer
The host MCU can write data into the TDA9206
registers.Read mode is not available.
To write data into the TDA9206, after a start, the
MCU must send (see Figure 5) :
2
- TheI
Caddressslavebytewitha lowlevelfor the
R/W bit.
- The byte of the internal register address where
the MCU wants to write data(s).
- The data.
All bytes are sent MSB bit first and the write data
transteris closedby a stop.
4/12
HSYNC
BPCP
BLK
Video IN
FBLK
OSD IN
V
OUT1,VOUT2,VOUT3
(4)
V
CONT
(5)
V
OSD
(3)
V
BRT
(2)
V
BLACK
(1)
V
DC
Notes : 1. VDC= 0.5 to 2.5V
2. V
BLACK=VDC
3. V
BRT=VBLACK
4. V
CONT=VBRT
5. V
OSD=VBRT
CONT
OSD
BRT
0.4V fixed
+ 0.4V
+ BRT (with BRT= 0 to 2.5V)
+ CONT with CONT = k x Video IN (CONT = 5VPPmax. for VIN= 0.7VPP)
+ OSD with OSD = k1 x OSDIN (OSD max. = 5VPP, OSD min. = 312mVPP)
9206-06.EPS
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