SGS Thomson Microelectronics TDA9109-SN Datasheet

TDA9109/SN

LOW-COST DEFLECTIONPROCESSOR

FOR MULTISYNC MONITORS

June 1998

PRELIMINARY DATA

SHRINK32

(Plastic Package)

ORDER CODE : TDA9109/SN

HORIZONTAL

SELF-ADAPTATIVE

DUALPLLCONCEPT

150kHzMAXIMUM FREQUENCY

X-RAYPROTECTIONINPUT

I2C CONTROLS : H-POSITION, FREQUENCY GENERATORFOR BURN-IN MODE

VERTICAL

VERTICALRAMP GENERATOR

50 TO185Hz AGC LOOP

GEOMETRYTRACKINGWITHVPOS& VAMP

I2C CONTROLS: VAMP, VPOS, S-CORR, C-CORR

DC BREATHING COMPENSATION

C GEOMETRYCORRECTIONS

VERTICALPARABOLAGENERATOR (PinCushion - E/W,Keystone, Corner)

HORIZONTALDYNAMICPHASE (SidePin Balance& Parallelogram)

VERTICALDYNAMIC FOCUS (VerticalFocus Amplitude)

GENERAL

SYNCPROCESSOR

12V SUPPLYVOLTAGE

8V REFERENCEVOLTAGE

HOR.& VERT. LOCK/UNLOCK OUTPUTS

READ/WRITEI2C INTERFACE

HORIZONTALAND VERTICALMOIRE

B+REGULATOR

- INTERNAL PWM GENERATOR FOR B+ CURRENT MODE STEP-UP CONVERTER

- SOFTSTART

-I

CADJUSTABLEB+REFERENCE VOLTAGE

- OUTPUT PULSES SYNCHRONIZED ON HORIZONTALFREQUENCY

- INTERNALMAXIMUMCURRENTLIMITATION

COMPARED WITH THE TDA9109, THE TDA9109/SNHAS :

- CORNER CORRECTION,

- HORIZONTAL MOIRÉ,

- B+ SOFT START,

- INCREASEDMAX.VERTICALFREQUENCY,

- NO HORIZONTAL FOCUS,

- NOSTEPDOWNOPTIONFORDC/DCCONVERTER,

-NOI

C FREE RUNNINGADJUSTMENT,

- FIXED HORIZONTAL DUTYCYCLE (48%),

- INCREASED MAXIMUM STORAGE TIME OF THE HORIZONTAL SCANNING TRANSISTOR.

DESCRIPTION

The TDA9109/SNis a monolithicintegratedcircuit assembledin 32-pinshrinkdual in lineplasticpackage.This IC controlsall the functionsrelatedto the horizontal and vertical deflection in multimode or multi-frequencycomputerdisplaymonitors.

Theinternalsyncprocessor,combinedwiththevery powerful geometry correction block make the TDA9109/SN suitable for very high performance monitors, using veryfew externalcomponents.

Thehorizontaljitter levelisverylow.Itisparticularly well suited forhigh-end 15” and 17” monitors.

Combined with the ST7275 Microcontroller family, TDA9206 (Video preamplifier) and STV942x (On-Screen Display controller) the TDA9109/SN allows fully I

C bus controlled computer display monitors to be built with a reduced number of external components.

This isadvance information on a new productnow indevelopment or undergoing evaluatio n. Detailsare subject to change withoutnotice.

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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

21 20 19 18 17

5V SDA SCL V

GND HOUT XRAY EWOUT VOUT VCAP V

REF

VAGCCAP VGND BREATH B+GNDI

SENSE

REGIN

COMP

HREF

HFLY

HGND

FOCUS-OUT

HMOIRE

HPOSITION

PLL1F

PLL2C

HLOCKOUT

H/HVIN

VSYNCIN

32 31 30 29 28 27

BOUT

9109SN01.EPS

PIN CONNECTIONS

TDA9109/SN

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PIN CONNECTIONS

Pin Name Function

1 H/HVIN TTL compatible Horizontal sync Input (separate or composite) 2 VSYNCIN TTL compatible Vertical sync Input (for separated H&V) 3 HLOCKOUT First PLL Lock/Unlock Output (0V unlocked - 5V locked) 4 PLL2C Second PLL LoopFilter 5 C0 Horizontal Oscillator Capacitor 6 R0 Horizontal Oscillator Resistor 7 PLL1F First PLL Loop Filter 8 HPOSITION HorizontalPosition Filter (capacitor to be connected to HGND)

9 HMOIRE Horizontal Moiré Output (to be connected to PLL2C through a resistor divider) 10 FOCUSOUT Vertical Dynamic Focus Output 11 HGND Horizontal Section Ground 12 HFLY Horizontal Flyback Input (positivepolarity) 13 HREF Horizontal Section ReferenceVoltage (to be filtered) 14 COMP B+ Error Amplifier Output for frequency compensation and gain setting 15 REGIN Regulation Input of B+ control loop 16 I

SENSE

Sensing ofexternal B+ switching transistor current 17 B+GND Ground (related to B+ reference adjustment) 18 BREATH DC Breathing Input Control (compensation of vertical amplitude against EHV variation) 19 VGND Vertical Section Ground 20 VAGCCAP Memory Capacitor for Automatic Gain Control Loop in Vertical Ramp Generator 21 V

REF

Vertical Section Reference Voltage (to be filtered) 22 VCAP Vertical Sawtooth Generator Capacitor 23 VOUT Vertical Ramp Output(withfrequencyindependantamplitude and S or C Correctionsif any).

It is mixed with vertical position voltage and vertical moiré. 24 EWOUT Pin Cushion - E/W Correction Parabola Output 26 HOUT Horizontal Drive Output (internal transistor, open collector) 25 XRAY X-RAY protection input (with internal latch function) 27 GND General Ground (referenced to V

) 28 BOUT B+ PWMRegulator Output 29 V

Supply Voltage (12V typ)

30 SCL I

C Clock Input

31 SDA I

C Data Input

32 5V Supply Voltage (5V typ.)

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QUICK REFERENCE DATA

Parameter Value Unit

Horizontal Frequency 15 to 150 kHz Autosynch Frequency (for given R0 and C0) 1 to 4.5 f0 ± Horizontal Sync Polarity Input YES Polarity Detection (on bothHorizontal and Vertical Sections) YES TTL Composite Sync YES Lock/Unlock Identification (on both Horizontal 1st PLL and Vertical Section) YES I

C Control for H-Position

10 % XRAY Protection YES I

C Horizontal Duty Fixed 48 %

C Free Running Frequency Adjustment NO Stand-by Function YES Dual Polarity H-Drive Outputs NO Supply Voltage Monitoring YES PLL1 Inhibition Possibility NO Blanking Outputs NO Vertical Frequency 35 to 200 Hz Vertical Autosync (for 150nF on Pin 22 and 470nF on Pin 20) 50 to 185 Hz Vertical S-Correction YES Vertical C-Correction YES Vertical Amplitude Adjustment YES DC Breathing Control on VerticalAmplitude YES Vertical Position Adjustment YES East/West (E/W) Parabola Output (also known as Pin Cushion Output) YES E/W Correction Amplitude Adjustment YES Keystone Adjustment YES Corner Correction YES Internal Dynamic Horizontal Phase Control YES Side Pin Balance Amplitude Adjustment YES Parallelogram Adjustment YES Tracking of Geometric Corrections with Vertical Amplitude and Position YES Reference Voltage (both on Horizontal and Vertical) YES Vertical Dynamic Focus YES I

C Horizontal Dynamic Focus Amplitude Adjustment NO I

C Horizontal Dynamic Focus Symmetry Adjustment NO I

C Vertical Dynamic Focus Amplitude Adjustment YES Detection of Input Sync Type YES Vertical Moiré Output YES Horizontal Moiré Output YES I

C Controlled Moiré Amplitude YES Frequency Generator for Burn-in YES Fast I

C Read/Write 400 kHz

B+ Regulation adjustable by I

C YES

B+ Soft Start YES

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REF

131211

67 26

HSYNC

HORIZONTAL

MOIRE CANCEL

5 BITS+ON/OFF

9 HMOIRE

HREF

HGND

SYNC

PROCESSOR

SYNC INPUT

SELECT

(1 bit)

B+

CONTROLLER

LOCK/UNLOCK

IDENTIFICATION

PHASE

COMPARATOR

PHASE

SHIFTER

H-DUTY

(48%)

HOUT

BUFFER

VCO

Forced

Frequency

2 bits

VAMP

7 bits

22 23

192432

REF

VGND

SDA

SCL

GND

REF

S AND C

CORRECTION

VERTICAL

OSCILLATOR

RAMP GENERATOR

GEOMETRY

TRACKING

6 bits 6 bits

Keyst.

6 bits

E/W

7 bits

PLL1F

HLOCKOUT

HPOSITION

HFLY

PLL2C

HOUT

CAP

AGCCAP

OUT

VSYNCIN

H/HVIN

EWOUT

XRAY

RESET

GENERATOR

C INTERFACE

VPOS

7 bits

AMPVDF

6 bits

FOCUS

Parallelogram

6 bits

Spin Bal

6 bits

VSYNC

SAFETY

PROCESSOR

XRAY

17 BGND

16 I

SENSE

15 REGIN

28 B+OUT

14 COMP

B+ Adjust

7 bits

BREATH

PHASE/FREQUENCY

COMPARATOR

H-PHASE (7 bits)

VERTICAL

MOIRE

CANCEL

5 BITS+ON/OFF

Corner

7 bits

TDA9109/SN

9109SN02.EPS

BLOCKDIAGRAM

TDA9109/SN

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ABSOLUTE MAXIMUMRATINGS

Symbol Parameter Value Unit

Supply Voltage (Pin 29) 13.5 V

Supply Voltage (Pin 32) 5.7 V

Max Voltage on Pin4

Pin 5 Pins 6, 7, 8, 14, 15, 16, 20, 22 Pins 9, 10, 18, 23, 24, 25, 26, 28 Pins 1, 2, 3, 30, 31

4.0

6.4

8.0

V V V V V

VESD ESD susceptibility Human Body Model,100pF Discharge through 1.5kΩ

EIAJ Norm, 200pF Discharge through 0Ω

300

stg

Storage Temperature -40, +150

Junction Temperature +150

oper

Operating Temperature 0, +70

9109SN03.TBL

THERMAL DATA

Symbol Parameter Value Unit

th (j-a)

Junction-Ambient Thermal Resistance Max. 65

C/W

9109SN04.TBL

SYNC PROCESSOR OperatingConditions (V

=5V,T

amb

=25oC)

Symbol Parameter Test Conditions Min. Typ. Max. Unit

HsVR Voltage on H/HVIN Input Pin 1 0 5 V

MinD Minimum Horizontal Input Pulses Duration Pin 1 0.7

Mduty Maximum Horizontal Input Signal Duty Cycle Pin 1 25 %

VsVR Voltage on VSYNCIN Pin2 0 5 V

VSW Minimum Vertical Sync Pulse Width Pin 2 5 µs VSmD Maximum Vertical SyncInput Duty Cycle Pin 2 15 % VextM Maximum VerticalSync Widthon TTL H/Vcomposite Pin 1 750

HLOCKOUT

Sink and Source Current Pin3 250

ElectricalCharacteristics(VDD=5V,T

amb

=25oC)

Symbol Parameter Test Conditions Min. Typ. Max. Unit

VINTH Horizontal and Vertical Input Logic Level

(Pins 1, 2)

Low Level High Level 2.2

0.8 V V

RIN Horizontal and Vertical Pull-Up Resistor Pins 1, 2 200 k

Ω

TfrOut Fall and Rise Time, Output CMOS Buffer Pin 3, C

OUT

= 20pF 200 ns

VHlock Horizontal1st PLLLock Output Status (Pin 3) Locked, I

LOCKOUT

= -250µA

Unlocked, I

LOCKOUT

= +250µA 4.405

0.5 V V

VoutT Extracted Vsync Integration Time (% of T

)

on H/V Composite (see Note 1)

C0 = 820pF 26 35 %

Note 1 : THis the horizontal period.

I2C READ/WRITE (see Note 2) ElectricalCharacteristics(V

=5V,T

amb

=25oC)

Symbol Parameter Test Conditions Min. Typ. Max. Unit

C PROCESSOR

Fscl Maximum Clock Frequency Pin 30 400 kHz

Tlow Low period of the SCL Clock Pin30 1.3 µs

Thigh High period of the SCL Clock Pin30 0.6 µs

Vinth SDA and SCL Input Threshold Pins 30,31 2.2 V

VACK Acknowledge Output Voltage on SDA input with 3mA Pin 31 0.4 V

Note 2 : See also I2C Table Control and I2C Sub Address Control.

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HORIZONTAL SECTION OperatingConditions

Symbol Parameter TestConditions Min. Typ. Max. Unit

VCO

0(Min.)

Minimum Oscillator Resistor Pin 6 6 kΩ

0(Min.)

Minimum Oscillator Capacitor Pin 5 390 pF

(Max.)

Maximum Oscillator Frequency 150 kHz

OUTPUT SECTION

I12m Maximum Input Peak Current Pin 12 5 mA

HOI Horizontal Drive Output Maximum Current Pin 26, Sunk current 30 mA

ElectricalCharacteristics(VCC=12V,T

amb

=25oC)

Symbol Parameter Test Conditions Min. Typ. Max. Unit

SUPPLY AND REFERENCE VOLTAGES

Supply Voltage Pin 29 10.8 12 13.2 V

Supply Voltage Pin 32 4.5 5 5.5 V

Supply Current Pin 29 50 mA

Supply Current Pin 32 5 mA

REF-H

Horizontal Reference Voltage Pin 13, I = -2mA 7.4 8 8.6 V

REF-V

Vertical Reference Voltage Pin 21, I = -2mA 7.4 8 8.6 V

REF-H

Max. Sourced Current on V

REF-H

Pin 13 5 mA

REF-V

Max. Sourced Current on V

REF-V

Pin 21 5 mA

1st PLL SECTION

HpolT Delay Time for detecting polarity change

(see Note 3)

Pin 1 0.75 ms

VCO

VCO Control Voltage (Pin 7) V

REF-H

=8V f

fH(Max.)

1.3

6.2

V V

Vcog VCO Gain (Pin7) R

= 6.49kΩ,C0= 820pF,

dF/dV = 1/11R

0C0

17.1 kHz/V

Hph HorizontalPhase Adjustment(see Note 4) % of Horizontal Period ±10 %

Vbmin

Vbtyp

Vbmax

HorizontalPhaseSetting Value (Pin8) (seeNote4)

Minimum Value Typical Value Maximum Value

Sub-Address 01

Byte x1111111 Byte x1000000 Byte x0000000

2.8

3.4

4.0

V V V

IPll1U

IPll1L

PLL1 Filter Current Charge PLL1 is Unlocked

PLL1 is Locked

140

Free Running Frequency R0= 6.49kΩ,C0= 820pF,

= 0.97/8R0C

22.8 kHz

df0/dT Free RunningFrequency Thermal Drift

(No drift on external components) (see Note 5)

-150 ppm/C

CR PLL1 Capture Range R

= 6.49kΩ,C0= 820pF,

from f

+0.5kHz to 4.5f

fH(Min.) f

(Max.) 90

25 kHz

kHz

FF Forced Frequency FF1 Byte 11xxxxxx

FF2 Byte 10xxxxxx

Sub-Address 02 2f0

3f0

Notes : 3. This delay is mandatory to avoid a wrong detection of polarity change in the case of a composite sync.

4. See Figure 10 for explanation of referencephase.

5. These parameters are not tested on each unit. They are measured during our internal qualification.

6. This PLLcapturerange may be obtained only if f0 is captured(for instance bu adjusting R0). Ifnot, more margin must be provided between fH (Min.) and f0, to copewith the components spread.

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HORIZONTAL SECTION (continued) ElectricalCharacteristics(V

=12V,T

amb

=25oC) (continued)

Symbol Parameter Test Conditions Min. Typ. Max. Unit

2nd PLL SECTION AND HORIZONTAL OUTPUT SECTION

FBth Flyback Input Threshold Voltage (Pin 12) 0.65 0.75 V

Hjit Horizontal Jitter At 31.4kHz 70 ppm HD Horizontal Drive OutputDuty-Cycle

(Pin 26) (see Note 7)

48 %

XRAYth X-RAY Protection Input ThresholdVoltage Pin 25, see Note 8 8 V

Vphi2 Internal Clamping Levels on 2nd PLL

Loop Filter (Pin 4)

Low Level High Level

1.6

4.0

V V

VSCinh Threshold Voltage to Stop H-Out,V-Out,

B-Out and Reset XRAY when V

< VSCinh (see Note 8)

Pin 29 7.5 V

VSDinh Threshold Voltage to Stop H-Out,V-Out,

B-Out and Reset XRAY when V

< VSDinh

Pin 32 4.0 V

HDvd Horizontal Drive Output (low level) Pin 26, I

OUT

= 30mA 0.4 V

VERTICAL DYNAMIC FOCUS FUNCTION (positiveparabola)

HDFDC Bottom DC Output Level R

LOAD

= 10kΩ, Pin 10 2 V

TDHDF DC Output Voltage Thermal Drift (see

Note 5)

200 ppm/C

AMPVDF Vertical Dynamic Focus Parabola

Amplitude with VAMP and VPOS Typical

Min. Byte 000000 Typ. Byte 100000 Max. Byte 111111

Sub-Address 0F

0.5 1

VDFAMP Parabola Amplitude Function of VAMP

(tracking between VAMP and VDF) with VPOS Typ. (see Figure 1 andNote 9)

Sub-Address 05

Byte 10000000 Byte 11000000 Byte 11111111

0.6 1

1.5

VHDFKeyt Parabola Asymetry Function of VPOS

Control(tracking between VPOS andVDF) with VAMP Max.

Sub-Address 06

Byte x0000000 Byte x1111111

0.52

Notes : 5. These parameters are not tested on each unit. They are measured during our internal qualification.

7. Duty Cycle is the ratio between the output transistor OFF time and the period. The power transistor is controlled OFF when the output transistor is OFF.

7. Initial Conditionfor Safe Operation Start Up

8. See Figure 14.

9. S and C correction are inhibited so the output sawtooth has a linearshape.

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VERTICALSECTION OperatingConditions

Symbol Parameter Test Conditions Min. Typ. Max. Unit

OUTPUTS SECTION

VEWM Maximum E/W OutputVoltage Pin 24 6.5 V VEWm Minimum E/W Output Voltage Pin 24 1.8 V

LOAD

Minimum Load for less than 1% VerticalAmplitude Drift Pin 20 65 M

Ω

ElectricalCharacteristics(VCC=12V,T

amb

=25oC)

Symbol Parameter Test Conditions Min. Typ. Max. Unit

VERTICAL RAMP SECTION

VRB Voltage at Ramp Bottom Point V

REF-V

= 8V, Pin 22 2 V

VRT Voltage at Ramp Top Point (with Sync) V

REF-V

= 8V, Pin 22 5 V VRTF Voltage at Ramp Top Point (without Sync) Pin 22 VRT-0.1 V VSTD Vertical Sawtooth Discharge Time Pin 22, C

= 150nF 70 µs

VFRF Vertical Free Running Frequency

(see Note 10)

OSC (Pin 22)

= 150nF

Measured on Pin22

100 Hz

ASFR AUTO-SYNC Frequency (see Note 11) C

= 150nF ±5% 50 185 Hz

RAFD Ramp Amplitude Drift Versus Frequency at

Maximum Vertical Amplitude (see Note 5)

= 150nF

50Hz < f and f < 185Hz

200 ppm/Hz

Rlin Ramp Linearity on Pin 22 (see Note 10) 2.5V < V

and V27< 4.5V 0.5 %

VPOS Vertical Position Adjustment Voltage

(Pin 23 - VOUT mean value)

Sub Address 06

Byte x0000000 Byte x1000000 Byte x1111111 3.65

3.2

3.5

3.8

3.3 V V V

VOR Vertical Output Voltage

(peak-to-peak on Pin 23)

Sub Address 05

Byte x0000000 Byte x1000000 Byte x1111111 3.5

2.25 3

3.75

2.5 V V V

VOI Vertical Output Maximum Current (Pin 23) ±5mA

dVS Max Vertical S-Correction Amplitude

(see Note 12)

x0xxxxxx inhibitsS-CORR x1111111 givesmax S-CORR

Sub Address 07

∆V/V

at TV/4

∆V/V

at 3TV/4

-4

% %

Ccorr Vertical C-Corr Amplitude

x0xxxxxx inhibits C-CORR

Sub Address 08 ∆V/V

@ TV/2 Byte x1000000 Byte x1100000 Byte x1111111

-3 0 3

% % %

Notes : 5. These parameters are not testedon each unit. They are measured during our internal qualification.

10. With Register 07 at Byte x0xxxxxx (S correctionis inhibited) and withRegister 08 at Bytex0xxxxxx (C correction is inhibited),the sawtooth has a linear shape.

11. This is the frequencyrangefor which thevertical oscillatorwill automaticallysynchronize,using a single capacitorvalue on Pin22 and with a constant ramp amplitude.

12. TV is thevertical period.

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