SGS Thomson Microelectronics TDA9109A Datasheet
TDA9109A
LOW-COST I2C CONTROLLED DEFLECTION PROCESSOR
FOR MULTISYNC MONITOR
FEATURES
General
■ SYNC PROCESSOR
■ 12V SUPPLY VOLTAGE
■ 8V REFERENCE VOLTAGE
■ HORIZONTAL LOCK/UNLOCK OUTPUT
■ READ/WRITE I
■ VERTICAL MOIRE
■ B+ REGULATOR
- Internal PWM generator for B+ current mode
step-up converter
- Switchable to step-down converter
-I2C adjustable B+ reference voltage
- Output Pulses Synchronized on Horizontal
Frequency
- Internal Maximum Current Limitation
Horizontal
■ Self-adaptative
■ Dual PLL concept
■ 150kHz maximum frequency
■ X-ray protection input
2
■ I
C controls:
Horizontal duty-cycle, H-position
2
C INTERFACE
DESCRIPTION
The TDA9109A is a monolithic integrated circuit
assembled in a 32-pin shrink dual in line plastic
package. This IC controls all the functions related
to the horizontal and vertical deflection in multimode or multi-frequency computer display monitors.
The internal sync processor, combined with the
very powerful geometry correction block, make
the TDA9109A suitable for very high performance
monitors, using very few external components.
The horizontal jitter level is very low. It is particularly well-suited to high-end 15” and 17” monitors.
Combined with the ST7275 Microcontroller family,
TDA9206 (Video preamplifier) and STV942x (OnScreen Display controller), the TDA9109A allows
fully I2C bus-controlled computer display monitors
to be built with a reduced number of external components
.
Vertical
■ Vertical ramp generator
■ 50 to 185Hz AGC loop
■ Geometry tracking with Vpos & Vamp
2
■ I
C controls:
SHRINK32 (Plastic Package)
ORDER CODE: TDA9109A
Vamp, Vpos, S-corr, C-corr
■ DC breathing compensation
I2C Geometry corrections
■ Vertical parabola generator
(Pin Cushion - E/W, Keystone, Corner
Correction)
■ Horizontal dynamic phase
(Side Pin Balance & Parallelogram)
■ Horizontal and vertical dynamic focus
(Horizontal focus amplitude, Horizontal focus
symmetry, Vertical focus amplitude)
Version 4.2
June 2000 1/47
1
TABLE OF CONTENTS
PIN CONNECTIONS 4
PIN CONNECTIONS 5
QUICK REFERENCE DATA 6
BLOCK DIAGRAM 8
ABSOLUTE MAXIMUM RATINGS 9
THERMAL DATA 9
I2C READ/WRITE 10
SYNC PROCESSOR 10
HORIZONTAL SECTION 11
VERTICAL SECTION 13
DYNAMIC FOCUS SECTION 15
GEOMETRY CONTROL SECTION 16
B+ SECTION 18
TYPICAL OUTPUT WAVEFORMS 20
I2C BUS ADDRESS TABLE 24
I2C BUS ADDRESS TABLE 25
OPERATING DESCRIPTION 27
1 GENERAL CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.1Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........................... 27
1.2I2C Control . . . . . . . . . . . . . . . . . . . . . . . . . . . ................................. 27
1.3Write Mode . . . . . . . . . . . . ...............................................27
1.4Read Mode . .. . . . . . . . . . . . . . . . . ........................................ 27
1.5Sync Processor . . . . . . . . . . . . . . . . . . . . . . . ................................. 27
1.6Sync Identification Status ................................................ 28
1.7IC status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................................28
1.8Sync Inputs .. . . . . . . . . . . ...............................................28
1.9Sync Processor Output . . . . . . . . . . ........................................28
2 HORIZONTALPART . . . .................................................... 28
2.1Internal Input Conditions . . ............................................... 28
2.2PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................................. 29
2.3PLL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................................. 31
2.4Output Section . . . . . ....................................................32
2.5X-RAY Protection . . . . . . . . . . . . . . . ........................................32
2.6Horizontal and Vertical Dynamic Focus . . . . .................................. 33
3 VERTICAL PART . . . . . . .................................................... 34
3.1Function . .............................................................34
3.2I2C Control Adjustments . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 34
3.3Vertical Moiré . . . . . . . ................................................... 34
3.4Basic Equations . . . . . . . . . . . . . ........................................... 35
3.5E/W ................................................................. 36
3.6Dynamic Horizontal Phase Control . . . . . . . . . . . . . . . . . . . . . .................... 36
3
2/47
2
TABLE OF CONTENTS
4 DC/DC CONVERTER PART . . ............................................... 37
4.1Step-up Mode . . . ...................................................... 37
4.2Step-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . .............................. 37
4.3Step-up and Step-down Mode Comparison . . ................................. 37
INTERNAL SCHEMATICS 39
PACKAGE MECHANICAL DATA 46
3/47
3
TDA9109A
PIN CONNECTIONS
H/HVIN
VSYNCIN
HLOCKOUT
PLL2C
C0
R0
PLL1F
HPOSITION
HFOCUSCAP
FOCUS-OUT
HGND
HFLY
HREF
COMP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
32
31
30
29
28
27
26
25
24
23
22
21
20
19
5V
SDA
SCL
V
CC
BOUT
GND
HOUT
XRAY
EWOUT
VOUT
VCAP
VREF
VAGCCAP
VGND
4/47
REGIN
I
SENSE
15
16
18
BREATH
B+GND17
TDA9109A
PIN CONNECTIONS
Pin Name Function
1 H/HVIN TTL compatible Horizontal sync Input (separate or composite)
2 VSYNCIN TTL compatible Vertical sync Input (for separated H&V)
3 HLOCKOUT First PLL Lock/Unlock Output (0 V: Unlocked - 5 V: Locked)
4 PLL2C Second PLL Loop Filter
5 C0 Horizontal Oscillator Capacitor
6 R0 Horizontal Oscillator Resistor
7 PLL1F First PLL Loop Filter
8 HPOSITION Horizontal Position Filter (capacitor to be connected to HGND)
9 HFOCUSCAP Horizontal Dynamic Focus Oscillator Capacitor
10 FOCUS OUT Mixed Horizontal and Vertical Dynamic Focus Output
11 HGND Horizontal Section Ground
12 HFLY Horizontal Flyback Input (positive polarity)
13 HREF Horizontal Section Reference Voltage (to be filtered)
14 COMP B+ Error Amplifier Output for frequency compensation and gain setting
15 REGIN Regulation Input of B+ control loop
16 I
SENSE
17 B+GND Ground (related to B+ reference adjustment)
18 BREATH DC Breathing Input Control (compensation of vertical amplitude against EHV variation)
19 VGND Vertical Section Ground
20 VAGCCAP Memory Capacitor for Automatic Gain Control Loop in Vertical Ramp Generator
21 V
REF
22 VCAP Vertical Sawtooth Generator Capacitor
23 VOUT
24 EWOUT Pin Cushion - E/W Correction Parabola Output
25 XRAY X-RAY protection input (with internal latch function)
26 HOUT Horizontal Drive Output (NPN open collector)
27 GND General Ground (referenced to V
28 BOUT B+ PWM Regulator Output
29 V
CC
30 SCL I
31 SDA I
32 5V Supply Voltage (5V typ.)
Sensing of external B+ switching transistor current,or switch for step-down converter
Vertical Section Reference Voltage (to be filtered)
Vertical Ramp Output (with frequency independant amplitude and S or C Corrections if
any). It is mixed with vertical position voltage and vertical moiré.
)
CC
Supply Voltage(12V typ)
2
C Clock Input
2
C Data Input
5/47
TDA9109A
QUICK REFERENCE DATA
Parameter Value Unit
Horizontal Frequency 15 to 150 kHz
Autosynch Frequency (for given R0 and C0. Can be easily increased by application) 1 to 4.5 f0
± Horizontal Sync Polarity Input YES
Polarity Detection (on both Horizontal and Vertical Sections) YES
TTL Composite Sync YES
Lock/Unlock Identification (on both Horizontal 1st PLL and Vertical Section) YES
2
C Control for H-Position ±10 %
I
XRAY Protection YES
2
C Horizontal Duty Cycle Adjustment 30 to 65 %
I
2
C Free Running Frequency Adjustment NO
I
Stand-by Function YES
Dual Polarity H-Drive Outputs NO
Supply Voltage Monitoring YES
PLL1 Inhibition Possibility NO
Blanking Outputs NO
Vertical Frequency 35 to 200 Hz
Vertical Autosync (for 150nF on Pin 22 and 470nF on Pin 20) 50 to 185 Hz
Vertical S-Correction (optimized for super flat tube) YES
Vertical C-Correction YES
Vertical Amplitude Adjustment YES
DC Breathing Control on Vertical Amplitude YES
Vertical Position Adjustment YES
East/West (E/W) Parabola Output (also known as Pin Cushion Output) YES
E/W Correction Amplitude Adjustment YES
Keystone Adjustment YES
Corner Correction with Amplitude Adjustment YES
Internal Dynamic Horizontal Phase Control YES
Side Pin Balance Amplitude Adjustment YES
Parallelogram Adjustment YES
Tracking of Geometric Corrections with Vertical Amplitude and Position YES
Reference Voltage (both on Horizontal and Vertical) YES
Dynamic Focus (both Horizontal and Vertical) YES
2
C Horizontal Dynamic Focus Amplitude Adjustment YES
I
2
C Horizontal Dynamic Focus Symmetry Adjustment YES
I
2
C Vertical Dynamic Focus Amplitude Adjustment YES
I
6/47
Parameter Value Unit
Detection of Input Sync (biased from 5V alone) YES
Vertical Moiré YES
Controlled V-Moiré Amplitude YES
Frequency Generator for Burn-in NO
2
C Read/Write 400 kHz
Fast I
2
B+ Regulation adjustable by I
CYES
Horizontal Size Control NO
TDA9109A
7/47
8/47
H/HVIN
SYNCIN
V
HLOCKOUT
SDA
SCL
GND
5V
1
2
3
31
30
27
32
SyncInput
Select
(1bit)
2
I
C Interface
PLL1F POSITION R0 C0 HFLY PLL2C HOUT
7 8 6 5 12 4 26
Phase/Frequency
Comparator
H-Phase(7bits)
Sync
Processor
VCO
Lock/Unlock
Identification
Phase
Comparator
SPinbal
7bits
2
x
Phase
Shifter
H-Duty
(7bits)
Safety
Processor
B+
Controller
x
Paral
7bits
VDFAMP
7bits
2
4
2
x
x
Amp
Symmetry
2x7bits
7 bits7 bits
S andC
Correction
Vertical
Oscillator
RampGenerator
VAMP
7bits
Geometry
Tracking
E/Wpcc
7bits
Keyst.
7 bits
Corner
7bits
x
x
Hout
Buffer
+
5V
Internal
reference
(7bits)
2
x
11
19
17
29
25
28
16
14
15
10
9
24
HGND
VGND
BGND
VCC
XRAY
BOUT
I
SENSE
COMP
REGIN
FOCUS
HFOCUSCAP
EWOUT
BLOCK DIAGRAM
TDA9109A
HREF
VREF
13
21
OUT
VerticalMoire
Cancel
7bits+ON/OFF
VSYNC
TDA9109A
H
ref
V
ref
VPOS
7bits
23182022
BREATHVAGCCAPVCAP
V
TDA9109A
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
V
DD
V
IN
Supply Voltage (Pin 29) 13.5 V
Supply Voltage (Pin 32) 5.7 V
Max Voltage on Pin 4
Pin 9
Pin 5
Pins 6, 7, 8, 14, 15, 16, 20, 22
Pins 10, 18, 23, 24, 25, 26, 28
Pins 1, 2, 3, 30, 31
4.0
5.5
6.4
8.0
V
V
CC
DD
ESD susceptibility Human Body Model, 100pF Discharge
VESD
T
stg
T
j
T
oper
through 1.5kΩ
EIAJ Norm, 200pF Discharge through 0Ω
2
300
Storage Temperature -40, +150 °C
Junction Temperature +150 °C
Operating Temperature 0, +70 °C
THERMAL DATA
Symbol Parameter Value Unit
R
th(j-a)
Max. Junction-Ambient Thermal Resistance 65 °C/W
V
V
V
V
V
V
kV
V
9/47
TDA9109A
I2C READ/WRITE
Electrical Characteristics (VDD= 5V, T
Symbol Parameter Test Conditions Min. Typ. Max. Units
2
C PROCESSOR (See1)
I
Fscl Maximum Clock Frequency Pin 30 400 kHz
Tlow Low period of the SCLClock Pin 30 1.3 µs
Thigh High period of the SCL Clock Pin 30 0.6 µs
Vinth SDA and SCL Input Threshold Pins 30, 31 2.2 V
VACK
2
C leak
I
Note: 1 See also I2C Bus Address Table.
Acknowledge Output Voltage on SDA
input with 3mA
Leakage current into SDA and SCL
with no logic supply
amb
=25°C)
Pin 31 0.4 V
V
=0
DD
Pins 30, 31 = 5 V
20 µA
SYNC PROCESSOR
Operating Conditions (VDD= 5V, T
Symbol Parameter Test Conditions Min. Typ. Max. Units
HsVR Voltage on H/HVIN Input Pin 1 0 5 V
MinD
Mduty
VsVR Voltage on VSYNCIN Pin 2 0 5 V
VSW Minimum Vertical Sync Pulse Width Pin 2 5 µs
VSmD
VextM
Minimum Horizontal Input Pulses Duration
Maximum Horizontal Input Signal Duty
Cycle
Maximum Vertical Sync Input Duty Cycle
Maximum Vertical Sync Width on TTL
H/Vcomposite
amb
=25°C)
Pin 1 0.7 µs
Pin 1 25 %
Pin 2 15 %
Pin 1 750 µs
Electrical Characteristics (VDD= 5V, T
Symbol Parameter Test Conditions Min. Typ. Max. Units
VINTH
RIN
VoutT
Note: 2 THis the Horizontal period.
10/47
Horizontal and Vertical Input Logic
Level (Pins 1, 2)
Horizontal and Vertical Pull-Up Resistor
Extracted Vsync Integration Time (%
) on H/V Composite (see2)
of T
H
amb
=25°C)
High Level
Low Level
Pins 1, 2 250 kΩ
C0 = 820pF 26 35 %
2.2
0.8
V
V
TDA9109A
HORIZONTALSECTION
Operating Conditions
Symbol Parameter Test Conditions Min. Typ. Max. Units
VCO
I
0max
F(max.) Maximum Oscillator Frequency 150 kHz
OUTPUT SECTION
I12m Maximum Input Peak Current Pin 12 5 mA
HOI
Max Current from Pin 6 Pin 6 1.5 mA
Horizontal Drive Output Maximum
Current
Pin 26, Sunk current 30 mA
Electrical Characteristics (VDD= 12V, T
amb
=25°C))
Symbol Parameter Test Conditions Min. Typ. Max. Units
SUPPLY AND REFERENCE VOLTAGES
V
V
I
I
V
REF-H
V
REF-V
I
REF-H
I
REF-V
CC
DD
CC
DD
Supply Voltage Pin 29 10.8 12 13.2 V
Supply Voltage Pin 32 4.5 5 5.5 V
Supply Current Pin 29 50 mA
Supply Current Pin 32 5 mA
Horizontal Reference Voltage Pin 13, I = -2mA 7.6 8.2 8.8 V
Vertical Reference Voltage Pin 21, I = -2mA 7.6 8.2 8.8 V
Max. Sourced Current on V
Max. Sourced Current on V
REF-H
REF-V
Pin 13 5 mA
Pin 21 5 mA
1st PLL SECTION
HpoIT
Delay Time for detecting polarity
change (see
3
)
Vvco VCO Control Voltage (Pin 7)
Vcog VCO Gain (Pin 7)
Hph
Vbmi
Vbtyp
Vbmax
IPII1U
IPII1L
f
o
Horizontal Phase Adjustment
4
)
(see
Horizontal Phase Setting Value (Pin 8)
4
)
(see
Minimum Value
Typical Value
Maximum Value
PLL1 Filter Current Charge
Free Running Frequency
Pin 1 0.75 ms
= 8.2V f
V
REF-H
fH(Max.)
= 6.49kΩ,
R
0
=820pF
C
0
% of Horizontal
Period
o
1.4
6.4
15.9 kHz/V
±10 %
Sub-Address 01
Byte x1111111
Byte x1000000
Byte x0000000
PLL1 is Unlocked
PLL1 is Locked
R
= 6.49kΩ,
0
= 820pF
C
0
2.9
3.5
4.2
±140
±1
22.8 kHz
Free Running Frequency Thermal Drift
dfo/dT
(No drift on external components)
5
)
(see
CR PLL1 Capture Range
fH(Min.)
fH(Max.) (See Note 6)
-150
f
o
4.5f
+0.5
o
HUnlock DC level pin 3 when PLL1 is locked 5 V
V
V
V
V
V
µA
mA
ppm/
C
kHz
kHz
11/47
TDA9109A
Symbol Parameter Test Conditions Min. Typ. Max. Units
2nd PLL SECTION AND HORIZONTAL OUTPUT SECTION
FBth
Hjit Horizontal Jitter (See
HDmin
HDmax
XRAYth
Vphi2
VSCinh
HDvd Horizontal Drive Output (low level) Pin 26, I
Note: 3 This delay is mandatory to avoid a wrong detection of polarity change in the case of a composite sync.
Note: 4 See Figure 10 for explanation of reference phase.
Note: 5 These parameters are not tested on each unit. They are measured during our internal qualification.
Note: 6 A larger range may be obtained by application.
Note: 7 Hjit = 10
Note: 8 Duty Cycle is the ratio between the output transistor OFF time and the period. The power transistor is
Note: 9 Initial Condition for Safe Operation Start Up.
Flyback Input Threshold Voltage (Pin
12)
7
) At 31.4kHz 70 ppm
Horizontal Drive Output Duty-Cycle
(Pin 26) (see
8
)
Sub-Address 00
Byte x1111111
Byte x0000000 (see
X-RAY Protection Input Threshold
Voltage,
Internal Clamping Levels on 2nd PLL
Loop Filter (Pin 4)
Pin 25, see Figure 14 7.6 8.2 8.8 V
Low Level
High Level
Threshold Voltage to Stop H-Out, VOut, B-Out and Reset XRAY when V
Pin 29 7.5 V
CC
< VSCinh(see Figure14)
6
x (Standard deviation/Horizontal period)
controlled OFF when the output transistor is OFF.
0.65 0.75 V
9
)
30
65
1.6
4.2
= 30mA 0.4 V
OUT
%
%
V
V
12/47
TDA9109A
VERTICAL SECTION
Operating Conditions
Symbol Parameter Test Conditions Min. Typ. Max. Units
OUTPUTS SECTION
R
LOAD
Minimum Load for less than 1% Vertical Amplitude Drift
Pin 20 65 MΩ
Electrical Characteristics (VCC= 12V, T
amb
=25°C)
Symbol Parameter Test Conditions Min. Typ. Max. Units
VERTICAL RAMP SECTION
VRB Voltage at Ramp Bottom Point Pin 22 2.1 V
VRT Voltage atRamp Top Point (with Sync) Pin 22 5.1 V
VRTF
Voltage at Ramp Top Point (without
Sync)
Pin 22
VSTD Vertical Sawtooth Discharge Time Pin 22, C
VFRF
Vertical Free Running Frequency
11
)
(See
ASFR AUTO-SYNC Frequency (See
Ramp Amplitude Drift Versus
RAFD
Frequency at Maximum Vertical
Amplitude (see
10
)
Rlin Ramp Linearity on Pin 22 (See
12
)C
11
) 2.5V < V27< 4.5V 0.5 %
C
= 150nF 100 Hz
22
= 150nF ±5% 50 185 Hz
22
C
= 150nF
22
50Hz< f < 185Hz
= 150nF 70 µs
22
VRT-
0.1
200
Sub Address 06
VPOS
Vertical Position Adjustment Voltage
(Pin 23 - VOUT mean value)
Byte 00000000
Byte 01000000
Byte 01111111
3.2
3.6
4.0
Sub Address 05
VOR
VOI
dVS
Vertical Output Voltage
(peak-to-peak on Pin 23)
Vertical Output Maximum Current
(Pin 23)
Max Vertical S-Correction Amplitude
13
)
(See
0xxxxxxx inhibits S-CORR
11111111 gives max S-CORR
Byte 10000000
Byte 11000000
Byte 11111111
Sub Address 07
Byte 11111111
∆V/V
∆V/V
at TV/4
PP
at 3TV/4
PP
2.15
3.0
3.9
±5mA
-3.5
3.5
Sub Address 08
Ccorr
Vertical C-Corr Amplitude
0xxxxxxx inhibits C-CORR
VMOIRE Vertical Moiré
∆V/V
Byte 10000000
Byte 11000000
Byte 11111111
Sub Address 0C
Byte 01X11111
PP
at TV/2
-3
0
3
6mV
V
ppm/
Hz
V
V
V
V
V
V
%
%
%
%
%
13/47
TDA9109A
Symbol Parameter Test Conditions Min. Typ. Max. Units
BREATHING COMPENSATION
BRRANG
BRADj
DC Breathing Voltage Range
14
)
(See
Vertical Output Variation versus DC
Breathing Control (Pin 23)
Note: 10 These parameters are not tested on each unit. They are measured during our internal qualification procedure.
Note: 11 With Register 07 at Byte 0xxxxxxx (S correction is inhibited) and Register 08 at Byte 0xxxxxxx (C correction
is inhibited), the vertical sawtooth has a linear shape.
Note: 12 This is the frequency range for which the vertical oscillator will automatically synchronize, using a single
capacitor value on Pin22 and Pin 20, and with a constant ramp amplitude.
Note: 13 TV is the vertical period.
Note: 14 When not used, the DC breathing control pin must be connected to 12V.
V
18
V
18>VREF-V
1V<V18< V
REF-V
112V
0
-2.5
%/V
%/V
14/47
DYNAMIC FOCUS SECTION
TDA9109A
Electrical Characteristics (VCC= 12V, T
amb
=25°C)
Symbol Parameter Test Conditions Min. Typ. Max. Units
HORIZONTAL DYNAMIC FOCUS FUNCTION
Horizontal Dynamic Focus Sawtooth
HDFst
Minimum Level
Maximum Level
HDFdis
HDFstart
Horizontal Dynamic Focus Sawtooth
Discharge Width
Internal Fixed Phase Advance versus
HFLY middle
HDFDC Bottom DC OutputLevel R
TDFHD
DC Output Voltage Thermal Drift
15
)
(see
Horizontal Dynamic Focus Amplitude
HDFamp
Min Byte xxx11111
Typ Byte xxx10000
Max Byte xxx00000
Horizontal Dynamic Focus Position
HDFKeyst
Advance for Byte xxx11111
Delay for Byte xxx00000
Pin 9, capacitor on
HFOCUSCAP and
C0 = 820pF, T
=
H
20µs
2.2
4.9
Start by HDFstart 400 ns
Independent of
frequency
=10kΩ, Pin 10 2.1 V
LOAD
1 µs
200
Sub-Address 03,
Pin 10, fH = 50kHz,
Symmetric Wave
Form
1
1.5
3.5
Sub-address 04
For time reference
see Figure 15
16
16
VERTICAL DYNAMIC FOCUS FUNCTION (positive parabola)
Vertical Dynamic Focus Parabola
Sub-Address 0F
(added to horizontal) Amplitude with
AMPVDF
VDFAMP
VAMP and VPOS Typical
Min. Byte xx000000
Typ. Byte xx100000
Max. Byte xx111111
Parabola Amplitude Function of VAMP
(tracking between VAMP and VDF)
with VPOS Typ. (see Figure 1 and
16
Parabola Asymmetry Function of
Sub-Address 05
Byte x0000000
Byte x1000000
)
Byte x1111111
Sub-Address 06
0
0.5
1
0.6
1
1.5
VPOS Control (tracking between
VHDFKeyt
VPOS and VDF) with VAMP Max.
A/B Ratio
B/A Ratio
Byte x0000000
Byte x1111111
0.52
0.52
V
V
ppm/
C
V
PP
V
PP
V
PP
%
%
V
PP
V
PP
V
PP
V
PP
V
PP
V
PP
Note: 15 These parameters are not tested on each unit. They are measured during our internal qualification.
Note: 16 S and C correction are inhibited so the vertical output sawtooth has a linear shape.
15/47
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