SGS Thomson Microelectronics TDA9106A Datasheet

TDA9106A

LOW COST DEFLECTION PROCESSOR

FOR MULTISYNCMONITORS

PRELIMINARY DATA

HORIZONTAL

.

SELF-ADAPTATIVE

.

DUALPLL CONCEPT

.

150kHzMAXIMUM FREQUENCY

.

X-RAYPROTECTION INPUT

.

I2C CONTROLS : HORIZONTAL POSITION,
FREQUENCY GENERATOR FOR BURN-IN
MODE

VERTICAL

.

VERTICALRAMPGENERATOR

.

50 TO 165Hz AGC LOOP

.

GEOMETRYTRACKINGWITHV-POS & AMP

.

I2C CONTROLS:
V-AMP,V-POS,S-CORR, C-CORR

2

C GEOMETRYCORRECTIONS

I

.

VERTICALPARABOLAGENERATOR
(Pincushion, Keystone, Corner Correction,
Top/bottomCorner Correction Balance)

.

HORIZONTALDYNAMICPHASE
(SidePin Balance & Parallelogram)

.

HORIZONTALAND VERTICALDYNAMIC FO­CUS (Horizontal Focus Amplitude, Horizontal
FocusSymmetry)

GENERAL

.

SYNCPROCESSOR

.

HOR.& VERT.SYNC OUTPUTFOR MCU

.

HOR.& VERT.BLANKING OUTPUTS

.

12V SUPPLYVOLTAGE

.

8V REFERENCE VOLTAGE

.

HOR.& VERT.LOCKUNLOCK OUTPUTS

.

READ/WRITEI2C INTERFACE

.

HORIZONTALMOIREOR DAC OUTPUT

DESCRIPTION

The TDA9106A is a monolithic integrated circuit
assembled in 42 pins shrunk dual in line plastic
package.ThisICcontrolsallthe functionsrelatedto
the horizontaland vertical deflectionin multimodes
or multi-frequencycomputerdisplay monitors.
Theinternalsyncprocessor,combinedwiththevery
powerfulgeometrycorrectionblock aremakingthe
TDA9106Asuitableforveryhighperformancemoni­torswith very few externalcomponents.
Itisparticularlywellsuitedfor high-end15” and17”
monitors.

Combined with ST7275 Microcontroller family,
TDA9206 (Video preamplifier) and STV942x
(On-Screen Display controller) the TDA9106A
allows to built fully I
display monitors, thus reducingthe number of
external components to a minimum value.

ORDER CODE :

PIN CONNECTIONS

S/G

MOIRE

PLL1INHIB

PLL2C

HREF

HFLY

HGND

FC2
FC1

C0
R0

PLL1F

HLOCKCAP

HPOS

XRAY

HFOCUSCAP

HFOCUS

V

CC

GND

HOUTEM

HOUTCOL

2

C buscontrolledcomputer

SHRINK42

(Plastic Package)

TDA9106A

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21 22

42 GND
41

SDA

40

SCL

39

5V

38

H/HVIN

37

HLOCKOUT

36

HOUT

35

VSYNCOUT

34

TEST

33

VSYNCIN

32

VFOCUS

31

EWOUT

30

VFLY

29

VOUT

28

VDCOUT

27

VCAP

26

V

REF

VAGCCAP

25

VGND

24

VBLKOUT

23

HBLKOUT

9106A-01.EPS

November 1997

This is advance information on a newproduct now in developmentor undergoing evaluation. Detailsaresubject to change without notice.

1/30

TDA9106A

PIN CONNECTIONS

Pin Name Function

1 S/G Sync on green input
2 MOIRE Moire output
3 PLL1 INHIB TTL-Compatible input for PLL1 inhibition
4 PLL2C Second PLL Loop Filter
5 HREF Horizontal Section ReferenceVoltage (to filter)
6 HFLY Horizontal Flyback Input (positivepolarity)
7 HGND Horizontal Section Ground
8 FC2 VCO Low Threshold filtering Capacitor

9 FC1 VCO High Threshold filtering Capacitor
10 C0 Horizontal Oscillator Capacitor
11 R0 Horizontal Oscillator Resistor
12 PLL1F First PLL Loop Filter
13 HLOCKCAP First PLL Lock/Unlock Time Constant Capacitor
14 HPOS Horizontal Centering Output (to filter)
15 XRAY X-RAY protection input (with internal latch function)
16 HFOCUSCAP Horizontal Dynamic Focus Oscillator Capacitor
17 HFOCUS Horizontal Dynamic Focus Output
18 V

CC

19 GND General Ground (related to V
20 HOUTEM Horizontal Drive Output (internaltransistor emitter)
21 HOUTCOL Horizontal Drive Output (int. trans.open collector)
22 HBLKOUT Horizontal Blanking Output (see activation table)
23 VBLKOUT Vertical Blanking Output (see activationtable)
24 VGND Vertical Section Ground
25 VAGCCAP Memory Capacitor for Automatic Gain Control Loop in Vertical Ramp Generator
26 V

REF

27 VCAP Vertical Sawtooth Generator Capacitor
28 V

DCOUT

29 VOUT Vertical Ramp Output(with frequency independant amplitude and S orC Corrections if any)
30 VFLY Vertical Flyback Input (positive polarity)
31 EWOUT East/West PincushionCorrection Parabola Output (with Corner corrections if any)
32 VFOCUS Vertical Dynamic Focus Output
33 VSYNCIN TTL-compatible Vertical Sync Input (for separated H&V)
34 TEST Not to be used - Test pin
35 VSYNCOUT TTL Vertical Sync Output (Extracted VSYNC in case of S/G or TTL Composite HV Inputs)
36 HOUT TTL Horizontal Sync Output (To beused for frequency measurement)
37 HLOCKOUT First PLL Lock/Unlock Output (5V unlocked - 0V locked)
38 H/HVIN TTL-compatible Horizontal Sync Input
39 5V Supply Voltage (5V Typ.)
40 SCL I
41 SDA I
42 GND Ground (Related to 5V)

Supply Voltage (12V Typ)

)

CC

Vertical Section Reference Voltage (to filter)

Vertical Position ReferenceVoltage Output

2

C-Clock input

2

C-Data input

9106A-01.TBL

2/30

TDA9106A

QUICK REFERENCEDATA

Parameter Value Unit

Horizontal Frequency 15 to 150 kHz
Autosynch Frequency (forgiven R0 and C0) 1 to 4.5 FH
± Horizontal Sync Polarity Input YES
Polarity Detection (on both Horizontal and Vertical Sections) YES
TTL Composite Synch or Sync on Green YES
Lock/Unlock Identification (on both Horizontal1st PLL and Vertical Section) YES

2

C Control for H-Position ± 10 %

I
XRay Protection YES
Fixed Horizontal Duty Cycle 48 %

2

C Free Running Adjustment NO F0

I
Stand-by Function YES
Two Polarities H-Drive Outputs YES
Supply Voltage Monitoring YES
PLL1 Inhibition Possibility YES
Blanking Outputs (both Horizontal and Vertical) YES
Vertical Frequency 35 to 200 Hz
Vertical Autosync (for 150nF) 50 to 165 Hz
Vertical S-Correction YES
Vertical C-Correction YES
Vertical Amplitude Adjustment YES
Vertical Position Adjustment YES
East/West Parabola Output YES
Pin Cushion Correction Amplitude Adjustment YES
Keystone Adjustment YES
Corner and Corner Balance Adjustments YES
Internal Dynamic HorizontalPhase Control YES
Side Pin Balance Amplitude Adjustment YES
Parallelogram Adjustment YES
Tracking of Geometric Corrections YES
Reference Voltage (both on Horizontal and Vertical) YES
Dynamic Focus (both Horizontal and Vertical) YES

2

C Horizontal Dynamic Focus Amplitude Adjustment YES

I

2

C Horizontal Dynamic Focus Keystone Adjustment YES

I
Type of Input Sync Detection (supplied by 5V Digital Supply) YES
Horizontal Moiré Output YES

2

C Controlled H-Moiré Amplitude YES

I
Frequency Generator for Burn-in YES

2

C Read/Write 400 kHz

Fast I

9106A-02.TBL

3/30

TDA9106A

BLOCKDIAGRAM

HOUTEM
HOUTCOL

PLL2C

HFLY

FC2
FC1
C0
R0

HLOCKCAP
HLOCKOUT

20
21

8910

1112 1314

37

HOUT

BUFFER

PHASE

SHIFTER

PHASE

COMPARATOR

VCO

VCCX-RAY

HFOCUS

18

15

SAFETY

PROCESSOR

H-SAWTOOTH

2 bits

SafeFreq.

CAP

16

2

X

2 x 5 bits

Amp & Keyst

GENERATOR

Spin Bal

6 bits

HFOCUS

2 MOIRE

17

5 BITS

MOIRE

PROCESSOR

2

X

Key Bal

6 bits

CORNER

H-FLY VSYNC

X

SYNC

PROCESSOR

2

X

6 bits

(2 x 6 bits)

CORRECTION

TRACKING

GEOMETRY

7 bits

VPOS

EWOUT

31

X

7 bits

2

X

VERTICAL

OSCILLATOR

RAMP GENERATOR

TDA9106

7 bits

VAMP

32

25

27 28 29

OUT

CAP

V

DCOUT

AGCCAP

V

VFOCUS

V

V

4/30

HPOSFILTER

PLL1F

PLL1INHIB

PHASE/FREQUENCY

3 4

19

GND

COMPARATOR

H-PHASE(7 bits)

REF

V

567

HREF

HGND

LOCK
HFLY
VSYNC
VFLY

LOCK/UNLOCK

IDENTIFICATION

BLANKING

GENERATOR

30

22

233335

VFLY

VBLKOUT

HBLKOUT

1

36

S/G

HOUT

VSYNCOUT

SELECT

SYNC INPUT

38

H/HVIN

(2 bits)

VSYNCIN

V

26

V

REF

REF

24

VGND

6 bits 6 bits

RESET GENERATOR

34

39

5V

TEST

S AND C

CORRECTION

C INTERFACE

2

I

40

41

SCL

SDA

42

GND

9106A-02.EPS

TDA9106A

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V
V

V

VESD ESD susceptibility

T

T

THERMAL DATA

Symbol Parameter Value Unit

R

th (j-a)

Supply Voltage (Pin 18) 13.5 V

CC

Supply Voltage (Pin 39) 5.7 V

DD

Max Voltage on Pin6

IN

Pins 15, 21, 22, 23
Pin 1
Pin 4
Pins 3, 33,34,37,38,40,41
Pin 16
Pins 8, 9, 10, 11, 12, 13, 14, 25, 27, 30

1.8
12

3.6

4
5
6
8

2
Human Body Model,100pF Discharge through 1.5kΩ
EIAJ Norm,200pF Dischargethrough 0Ω

Storage Temperature -40, +150

stg

Junction Temperature +150

T

j

Operating Temperature 0, +70

oper

300

Junction-ambient Thermal Resistance Max. 65

kV

o
o
o

o

C/W

V
V
V
V
V
V
V

V

C
C
C

9106A-03.TBL

9106A-04.TBL

SYNCHROPROCESSOR
OperatingConditions

Symbol Parameter Test Conditions Min. Typ. Max. Unit

HsVR Horizontal Sync Input Voltage Pin 38 0 5 V

MinD Minimum Horizontal Input Pulses Duration Pin 38 0.7 µs

Mduty Maximum HorizontalInput Signal Duty Cycle Pin 38 25 %

VsVR Vertical Sync Input Voltage Pin 33 0 5 V

VSW Minimum Vertical Sync Pulse Width Pin 33 5 µs
VSmD Maximum Vertical Sync Input Duty Cycle Pin 33 15 %
VextM Maximum Vertical Sync Width on TTL

H/Vcomposite or S/G

ElectricalCharacteristics

(V

DD

=5V,T

amb

=25oC)

Symbol Parameter Test Conditions Min. Typ. Max. Unit

VSGDC S/G Clamped DC Level Pin 1, I
ISGbias Internal Diode Bias Current Pin 1, V

VSGTh SlicingLevel (see application design choice) Pin 1 0.2 V

VINTH Horizontal and Vertical Input Voltage

(Pins 33,38)

RIN Horizontaland Vertical Pull-Up Resistor Pins 33,38 200 kΩ

VOut Output Voltage (Pins 35,36,37) Low level

TfrOut Falling and Rising Output CMOS Buffer Pins 35,36,37

VHlock Horizontal 1st PLLLock Output Status (Pin 37) Locked

VoutT Extracted Vsync Integration Time (% of TH) on

H/V Composite or S/G

Pins 1, 38 750 µs

=-1µA1V

1

= 1.6V 10 µA

1

Low Level

0.8 V

High Level 2.2

0

High Level

5

100 ns

Cout = 20pF

0

Unlocked

5

Pin 35, C0 = 820pF 26 35 %

V

V
V

V
V

9106A-05.TBL

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TDA9106A

I2C READ/WRITE
ElectricalCharacteristics

Symbol Parameter Test Conditions Min. Typ. Max. Unit

2

I

C PROCESSOR

Fscl Maximum Clock Frequency Pin 40 400 kHz

Tlow Low period of the SCL Clock Pin 40 1.3 µs

Thigh High period of the SCL Clock Pin 40 0.6 µs

Vinth SDA and SCL Input Threshold Pins 40,41 2.2 V

VACK AcknowledgeOutput Voltage onSDA inputwith3mA Pin 41 0.4 V

See also I2CTable Control and I2C Sub Address Control

HORIZONTAL SECTION
OperatingConditions

Symbol Parameter Test Conditions Min. Typ. Max. Unit

VCO

R

0(Min.)

C

0(Min.)

F

(Max.)

OUTPUT SECTION

I6m Maximum Input Peak Current Pin 6 2 mA

HOI1
HOI2

Minimum Oscillator Resistor Pin 11 6 kΩ
Minimum Oscillator Capacitor Pin 10 390 pF
Maximum Oscillator Frequency 150 kHz

Horizontal Drive Output Maximum Current

Pin 20
Pin 21

(V

DD

=5V,T

amb

=25oC)

Sourced current
Sunk current

2020mA

mA

ElectricalCharacteristics (VCC=12V,T

amb

=25oC)

Symbol Parameter Test Conditions Min. Typ. Max. Unit

SUPPLY AND REFERENCE VOLTAGES

V
V

I
I

V

REF-H

V

REF-V

I

REF-H

I

REF-V

Supply Voltage Pin 18 10.8 12 13.2 V

CC

Supply Voltage Pin 39 4.5 5 5.5 V

DD

Supply Current Pin 18 50 mA

CC

Supply Current Pin 39 5 mA

DD

Horizontal Reference Voltage Pin 5, I = 5mA 7.4 8 8.6 V
Vertical Reference Voltage Pin 5, I = 5mA 7.4 8 8.6 V
Max. SourcedCurrent on V
Max. SourcedCurrent on V

REF-H
REF-V

Pin 5 5 mA
Pin 26 5 mA

9106A-05.TBL

6/30

TDA9106A

HORIZONTAL SECTION (continued)
ElectricalCharacteristics

Symbol Parameter Test Conditions Min. Typ. Max. Unit

1st PLL SECTION

HpolT Polarity Integration Delay 0.75 ms

V

Vcog VCO Gain (Pin 12) R

Hph Horizontal Phase Adjustment % of Horizontal Period ±10 %

Hphmin

Hphtyp

Hphmax

dF0/dT FreeRunning Frequency Thermal Drift

CR PLL1 Capture Range R

PLLinh PLL1 Inhibition (Pin3) Typ Threshold = 1.6V

SFF Safe Forced Frequency

FC1
FC2

2nd PLL SECTION AND HORIZONTAL OUTPUT SECTION

FBth Flyback Input Threshold Voltage (Pin 6) 0.65 0.75 V

Hjit Horizontal Jitter (see Pins 8-9 filtering) TBD ppm

XRAYth X-RAY Protection Input Threshold Voltage Pin 15 8 V

Vphi2 Internal Clamping Levels on 2nd PLL Loop

VSCinh Threshold Voltage To Stop H-Out,V-Out

IHblk Maximum Horizontal Blanking Output

VHblk Horizontal Blanking Output Low Level

HDvd

HDem

Notes :

VCO Control Voltage (Pin12) V

VCO

Horizontal Phase Decoupling Output

Minimum Value
Typical Value
Maximum Value

Free Running Frequency R0= 6.49kΩ,C0= 820pF,

f

0

(No drift on external components)

SF1 Byte 11xxxxxx
SF2 Byte 10xxxxxx

VCO Sawtooth Level

High FC1=(4.V
Low FC2=(V

REF-H

Horizontal Drive Output Duty-Cycle
(Pin 20 or 21) (see Note 1)

Filter (Pin 4)

when V

< VSCinh

CC

Current

(Blanking ON)
Horizontal Drive Output

Low Level (Pin 20 to GND)
High Level (Pin 21 to V

1. Duty Cycle is the ratio of power transistorOFF time to period.Power transistor is OFF when output transistor is OFF.

2. Initial Condition for Safe Operation Start Up (Max. duty cycle).

(V

REF-H

)/5

CC

)/5

=12V,T

=12V)

CC

=25oC) (continued)

amb

REF-H

f

0

fH(Max.)

= 6.49kΩ,C0= 820pF,

0

dF/dV = 1/11R

Sub-Address 01, Pin 14

Byte x1111111
Byte x1000000
Byte x0000000

= 0.97/8R0C

f

0

= 6.49kΩ,C0= 820pF,

0

from f

fH(Min.)
f

H

PLL ON
PLL OFF 2

Sub-Address 02

Pin 9 To filter
Pin 8 To filter

Low Level
High Level

Pin 18 7.5 V

I

22

V

with I22= 10mA 0.25 0.5 V

22

V

21-V20,IOUT

V

20,IOUT

=8V

0C0

0

+0.5kHz to 4.5F

0

0

(Max.) 100

= 20mA

= 20mA 9.5

V

/6

REF-H

6.2
17 kHz/V

2.8

3.4

4.0

22.3 kHz

-150 ppm/C

23.5 kHz

0.8 V

2F0
3F0

6.4

1.6

48 %

1.6

4.0

10 mA

1.1

1.7 V

10

V
V

V
V
V

kHz

V

V
V

V
V

V

9106A-05.TBL

7/30

TDA9106A

HORIZONTAL SECTION (continued)
ElectricalCharacteristics

Symbol Parameter Test Conditions Min. Typ. Max. Unit

HORIZONTAL DYNAMIC FOCUS SECTION

HDFst Horizontal Dynamic Focus Sawtooth

HDFdis Horizontal Dynamic Focus Sawtooth

HDFDC Bottom DC Output Level R
TDHDF DC Output Voltage Thermal Drift 200 ppm/C

HDFamp Horizontal Dynamic Focus Amplitude

HDFKeyst Horizontal Dynamic Focus Keystone

MOIRE OUTPUT

R

MOIRE

V

MOIRE

Minimum Level
Maximum Level

Discharge Width

Min Byte xxx11111
Typ Byte xxx10000
Max Byte xxx00000

Min A/B Byte xxx11111
Typ Byte xxx10000
Max A/B Byte xxx00000

Minimum Output Resistor Pin 2 2 kΩ
Output Voltage (moire off),

Subaddress 0F

(V

CC

=12V,T

=25oC) (continued)

amb

HfocusCap = C

= 90kHz, Pin 16 2

f

H

Driven by Hfly 500 ns

= 10kΩ, Pin 17 2 V

LOAD

Sub-Address 03, Pin 17,

= 90kHz, Keystone Typ 1

f

H

Sub-Address 04,

= 90kHz, Typ Amp

f

H

B/A
A/B
A/B

Pin 2, R

Byte 0xx00000
Byte 0xx10000
Byte 0xx11111

MOIRE

= 820pF,

0

=2kΩ

4.7

1.5
3

3.5

1.0

3.5

0.2

1.1

2.0

V
V

V

PP

V

PP

V

PP

V
V
V

9106A-05.TBL

8/30

TDA9106A

VERTICALSECTION
OperatingConditions

Symbol Parameter Test Conditions Min. Typ. Max. Unit

OUTPUTS SECTION

VEWM Maximum EW OutputVoltage Pin 31 6.5 V
VEWm Minimum EW Output Voltage Pin 31 1.8 V

VDFm Minimum Vertical DynamicFocus Output Voltage Pin 32 1.8 V

R

LOAD

Minimum Load for less than 1% Vertical Amplitude Drift Pin 25 65 MΩ

ElectricalCharacteristics

(V

CC

=12V,T

amb

=25oC)

Symbol Parameter Test Conditions Min. Typ. Max. Unit

VERTICAL RAMP SECTION

VRB Voltage at Ramp BottomPoint V
VRT Voltage at Ramp Top Point (with Sync) V

REF-V

VRTF Voltage at Ramp Top Point (withoutSync) Pin 27 VRT-

=8V, Pin 27 2 V

REF-V

Pin 27 5 V

V

0.1

VSTD Vertical Sawtooth Discharge Time Duration

With 150nF Cap 80 µs

(Pin 27)

VFRF Vertical FreeRunning Frequency

(see Notes 3 & 4)

ASFR AUTO-SYNC Frequency C

RAFD Ramp Amplitude Drift Versus Frequency at

Maximum Vertical Amplitude

Rlin Ramp Linearity on Pin 27 (see Notes 3 & 4) 2.5 < V

C

OSC (Pin 27)

Measured on Pin27,

27

See Note 5
C

27

50Hz < f and f < 165Hz

= 150nF

= 150nF ±5%

= 150nF

and V27< 4.5V 0.5 %

27

100 Hz

50 165 Hz

200 TBD ppm/Hz

Vpos Vertical Position Adjustment Voltage (Pin28) Sub Address 06

I

VPOS

Max Current on Vertical Position Output Pin 28 ±2mA

VOR Vertical Output Voltage

(peak-to-peak on Pin 29)

Byte x0000000
Byte x1000000
Byte x1111111 3.65

Sub Address 05

Byte x0000000
Byte x1000000
Byte x1111111 3.5

3.2

3.5

3.8

2.25

3

3.75

3.3 V
V
V

2.5 V
V
V

VoutDC DC Voltage on Vertical Output See Note 6, Pin 29 3.5 V

VOI Vertical Output Maximum Current (Pin29) ±5mA

dVS Max Vertical S-Correction Amplitude

x0xxxxxx inhibits S-CORR
x1111111 gives max S-CORR

Ccorr Vertical C-Corr Amplitude

x0xxxxxx inhibits C-CORR

Subaddress 07

PP
PP

at T/4
at 3T/4

∆V/V
∆V/V

SubAddress 08

Byte x1000000
Byte x1100000
Byte x1111111

-4

+4

-3
0
3

%
%

%
%
%

VflyTh Vertical Flyback Threshold Pin 30 1 V

VflyInh Inhibition of Vertical Flyback Input See Note 7, Pin 30 7.5 V

Notes : 3. WithRegister 07 at Byte x0xxxxxx (VerticalS-Correction Control) thenthe S correction is inhibited, consequentlythesawtooth has

a linear shape.

4. With Register 08 at Byte x0xxxxxx (Vertical C - Correction Control) then the C correction is inhibited,consequently the sawtooth
has a linear shape.

5. It is the frequency range for which the VERTICAL OSCILLATOR will automaticallysynchronize, using a single capacitor value on
Pin 27 and with a constantramp amplitude.

OUTDC = (7/16).VREF-V. Typically 3.5V for Vertical reference voltage typical value (8V).

6. V

7. WhenPin30 ( V
discharge time.

) - 0.5V, Vflyinput is inhibited and vertical blanking on vertical blanking outputis replacedby vertical sawtooth

REF-V

9106A-05.TBL

9/30