SGS Thomson Microelectronics TDA8205 Datasheet

.

HIGHLY INTEGRATED TWO CHIP SOLU­TION FOR NICAM DEMODULATION (using
TDA8204 decoder)

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AUTOMATIC DUAL STANDARD DE MOD ULA­TION 6.552MHz FOR I SYSTEM

5.85MHz FOR B/G SYSTEM

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40dB RANGE A GC

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SINGLE CRYSTAL OPERATION

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NICAM 728 DATA AND CLOCK RECOVERY

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LOW PASS FILTER FOR PWM CODED
AUDIO SIGNALS AND J-17 DE-EMPHA SI S

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AUTOMATIC FM MONO SELECTION BY RE­SERVE SOUND SWITCH FUNCTION

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VERSATILE A UDI O SWI T CHING MATRI X

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AUTOM ATIC MUTE FUNCTION

TDA8205

NICAM QPSK DEMODULATOR

SHRINK 42

(Plastic Package)

ORDER CODE : TDA8205

PIN CONNECTIONS

DESCRIP TION

The TDA8205 is es sentially divided into two s ignal
processing sections. The first section handles all
the NICAM signal acquisition, the QPSK demodu­lator and clock and data recovery circuits. The key
point to note about this section is the dual fre­quency synthesiser. By use of only one quartz
crystal, the IC is able to demodulate QPSK signals
from either system I or system B/G in an automatic
way . The second section of the TDA8205 manages
the analog parts of the twin digital-to-analog con­verters (DA Cs) and all filter ing and audio switc hing
downstream of the DACs. A simple serial bus from
the TDA8204 allows control of the s witch f unctions
by the CTV system microcontroller.

GND

XC1
XC2
DF2
DF1

BG

AGC

V
V

LFIL1

RG

GND

RFIL1

RESET

V

SERI

DACDL

DACDR

GND

CK11648 CK728

I

CC

DD

DD

1
2
3
4
5
6

IN

7

IN

8
9
10
11
12
13
14
15
16
17
18
19
20
21

LF1

42

LF2

41

XK1

40

V

39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

CC

EAIR
EAIL
SAIR
SAIL
MAI
CAP
AMOR
AMOL
DC2
DC1
AOR
AOL

GND
MMO

TEST
NDO

8205-01.EPS

October 1993

1/8

TDA8205

PIN AS SIG MENT

Pin No Pin Name Function Pin No Pin Name Function

1 GND Ground 22 CK728 728kHz Clock Intput
2 XC1 Optional Crystal 23 NDO NICAM Data Output
3 XC2 Optional Crystal 24 TEST To be connected to GND
4 DF2 Data Filter 2 (eye monitor) 25 MMO Matrix Mute Out
5 DF1 Data Filter 1 (eye monitor) 26 GND Ground
6BG
7I

IN

8 AGC AGC Filter Capacitor 29 DC1 Decoupling 1
9V

10 V

CC
DD

11 LFIL1 Left Filter 1 (J-17 De-emphasis) 32 AMOR Audio Mutable Output Right
12 RG Gain Setting Resistor for DAC 33 CAP Decoupling Capacitor
13 GND Ground 34 MAI Mono Audio Input
14 RFIL1 Right Filter 1 (J-17 De-emphasis) 35 SAIL Stereo Audio Input Left
15 RESET Reset Chip 36 SAIR Stereo Audio Input Right
16 V

DD

17 SERI Interchip Serial Bus Input 38 EAIR External Audio Input Right
18 DACDL DAC Data Left Input 39 V
19 DACDR DAC Data Right Input 40 XK1 11.648MHz Crystal
20 GND Ground 41 LF2 Loop Filter 2
21 CK11648 11.648MHz Clock Output 42 LF1 Loop Filter 1

System B/G Input 27 AOL Audio Output Left

IN

System I Input 28 AOR Audio Output Right

+12V Supply 30 DC2 Decoupling 2
+5V Supply 31 AMOL Audio Mutable Output Left

+5V Supply 37 EAIL External Audio Input Left

CC

+12V Supply

8205-01.TBL

BLOCK DIAG RAM

DD

DD

CC

V

V

V

39 8 5 4 42 23 22211918 11 343536 31 32 37 38

16

10

AGC

AGC

1

GND

DF1

DF2

QSPSK

DEMOD

DUAL FREQ

SYNTHESISER

20 17331412

GND GND GND

LF1

RECOVERY

2613

LF2

419

CLOCK
& DATA

2 340

XC1

NDO

XC2

CK728

XK1

BG

TEST

RESET

7

I

IN

6

IN

24

15

CC

V

SWITCH

TDA8205

BLOCK DIAG RAM DES CRI PTI ON

The QPSK signal enters the IC via two inputs after
passing through two external bandpass filters at
the relevant frequencies of 6.552MHz and

5.85MHz for system I and B/G respectively. The
two inputs enter a source selection switch and pass
immediately to an AGC block which has a total
range of 40dB. The resulting levelled signal passes

CK11648

DACDR

DACDL

DAC

DAC

RG RFIL1 CAP

LPF

LPF

MAI

SAIR

LFIL1

SAIL

MUTE

SWITC H

SERI AL

INTERFACE

SERI

EAIL

AMOR

AMOL

MATRIX
SWITCH

to the QPSK demodulator which recovers the NI­CAM 728Kb/s data stream by means of carr ier and
clock recovery circuits.
Carrier recovery is achieved with a baseband re­modulator which consists of a phase locked loop
with a switchable phase detector. This allows it to
lock to one of four possible phases of the QPSK

EAIR

27

AOL
AOR

28

DC1

29

DC2

30

MMO

25

8205-02.EPS

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TDA8205

carrier without disruption due to the modulation.
Dual frequency operation is made pos sible by syn­thesising the carrier reference fre quency thus sav­ing the need for two extra crys tals. Dual VCXO ca n
also be software selected (SYN bit of CR3 in
TDA8204) with external crystal (Pin XC1/XC2) for
new standards. Selection between XC1 and XC2
is done with bit "IBG" in CR3 register of TDA8204
(IBG = 0 XC1 selected, IBG = 1 XC2 selected).

The standards switch controls operation of the
QSPK demodulator at either 6.552MHz or

5.85MHz. This can be controlled via the I

2

C bus or
the decoder set into automatic mode in which it
determines the standard by alternately trying to
lock to the two system s.

On chip low pass filters recover the in-phase and
quadrature data channels which are then sliced by
comparators. The symbol clock is recovered from
this data and used to sample and re-time it. The
two data channels are then decoded and serialized
to obtain the NICAM -728 data which is then pass ed
on to the NICAM decoder in the TDA8204.

After proces sing the NICAM into a digital bit-stream
in the TDA8204, the data is passed back to the
TDA8205 for the analog functions of the DACs to
be performed.

Conversion of the pulse width modulated bit
streams to analog takes place and is followed by
low pass filtering which removes high frequency
quantising noise and performs J-17 de-emphasis.
The DACs signal level can be adjusted to match
the reserve sound signal level.

1V

maximum on Pins LFIL1/RFIL1 can be ob-

RMS

tained by selection of appropriate resistor on
Pin RG.

Once the analog audio has been recovered, certa in
source switch functions are performed. If the NI­CAM signal fails and if the reserve sound flag (C4),
of SRO register, is set the reserve sound switch

automatically selects Mono Audio Input. If the re­serve sound flag (C4) is reset, the reserve sound
switch will not change and the audio outputs will b e
muted (DAC outputs muted).

If the NICAM signal only carries data, Mono Audio
Input is selected. The reserve sound switch can b e
forced to select Mono Audio Input via I

2

C bus , us ing

Bit FS0 = 1 and FS1 =0 of CR3 Register.
This can be used in the case of NICAM marginal

reception. To select Stereo Left and Right Audio
Input Bit FS0 = 0 and FS1 = 1 of CR3 Regis ter must
be selected. The outputs from this reserve sound
switch are available on Audio mutable output left
and right, and are internaly connected to the audio
matrix.

A simple audio switching matrix is provided inter­nally for flexible control over the audio source and
destination sel ection.

Audio signal left and right com ing f rom the reserv e
sound switch and the external audio input left and
right can be switched to the audio outputs left and
right .

DAC and auxiliary audio outputs can be muted. An
additional +6dB gain can be applied to raise the
output levels to 2V

maximum. For more infor-

RMS

mation see Software Specification chap­ter (III.5.3/TDA8204).

The DAC outputs are automatically muted under
the following conditions

- loss of frame alignement

- the bit error rate (Ber) is > error rat e limit

- NICAM signal is conveying M1 only. The right
DAC is muted unless M1 has been selected t o be
on both DAC outputs.

- NICAM signal is conveying data only.

For test purposes, the DAC outputs can be un­muted by forcing the bi-directional mute Pin 25 of
TDA8204 or via I

2

C bus.

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V

CC

V

DD

P

tot

T

oper

T

stg

Supply Voltage 15 V
Supply Voltage 7 V
Total Power Dissipation 1.2 W
Operating Temperature Range 0, + 70
Storage Temperature Range -20, + 150

THERMAL DATA

Symbol Parameter Value Unit

R

th (j-a)

Thermal Resistance Junction-Ambient Max. 67

o

C/W

o

C

o

C

8205-02.TBL

8205-03.TBL

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