SGS Thomson Microelectronics TDA7580 Datasheet

FM/AM DIGITAL IF SAMPLING PROCESSOR

■

FM/AM IF SAMPLING DSP

■

ON-CHIP ANALOGUE TO DIGITAL
CONVERTER FOR 10.7MHz IF SIGNAL
CONVERSION

■

SOFTWARE BASED CHANNEL EQUALIZATION

■

FM ADJACENT CHANNEL SUPPRESSION

■

RECEPTION ENHANCEMENT IN MULTIPATH
CONDITION

■

STEREO DECODER AND WEAK SIGNAL
PROCESSING

■

2 CHANNELS SERIAL AUDIO INTERFACE
(SAI) WITH SAMPLE RATE CONVERTER

■

I2C AND BUFFER-SPI CONTROL INTERFACES

■

RDS FILTER, DEMODULATOR & DECODER

■

INTER PROCESSOR TRA NS PO RT
INTERFACE FOR ANTENNA AND TUNER
DIVERSITY

■

FRONT-END AGC FEEDBACK

TDA7580

PRODUCT PREVIEW

TQFP64

ORDERING NUMBER: TDA7580

DESCRIPTION

The TDA7580 is an integrated circuit implementing
an advanced mixed analogue and digital solution to
perform the signal processing of a AM/FM channel.
The HW&SW architecture has been devised so to
have a digital equalization of the FM/AM channel;
hence a real rejection of adjacent channels and any
other signals interfering with the listening of the de­sired station. In severe Multipl e Paths conditi ons, the
reception is improved to get the audi o with hi gh qual­ity.

BLOCK DIAGRAM

Oscillator

HS3I

CGU

A/D

DAC

RDS

I2C/SPI

IF Digital

Signal Processor

I2C/SPI

SAI1

SAI0

SRC

July 2002

This is preliminary information on a new product now in development. Details are subject to change without notice.

1/31

TDA7580

DESCRIPTION

(continued)
The algorithm is self-adaptive, thus it requires no “on-the-field” adjustments after the parameters optimization.
The chip embeds a

Band Pass Sigma Delta Analogue to Digital Converter

for 10.7MHz IF conversion from a

“tuner device” (it is highly recommended the TDA7515).
The internal 24bit-DSP allows some flexibility in the algorithm implementation, thus giving some freedom for

customer required features. The total processing power offers a significant headroom for customer’s software
requirement, even when the channel equalization and the decoding software is running. The Program and Data
Memory space can be loaded from an external non volatile memory via I

2

C or SPI.

The oscillator module works with an external 74.1MHz quartz crystal. It has very low Electro Magnetic Interfer­ence, as it introduces very low distortion, and in any case any harmonics fall outside the Radio bandwidth.

The companion tuner device receives the reference clock through a differential ended interface, which works
off the Oscillator module by properly dividing down the master clock frequency. That allows the overall system
saving an additional crystal for the tuner.

After the IF convers ion, the digitiz ed baseband signal pass es through th e B ase Band pr oces sing section, either
FM or AM, depending on the listener selection. The FM Base Band processing comprises of Stereo Decoder,
Spike Detection and Noise Blanking. The AM Noise Blanking is fully software implemented.

The internal RDS filter, de modulator and dec oder featur es com plete functi ons to hav e the output data avail able
through either I

2

C or SPI interface. No DSP support is needed but at start-up, so that RDS can work in back­ground and in parallel with other DSP pr ocess ing. Thi s mode (RDS-onl y) all ows cur rent c onsumption savi ng for
low power application modes.

2

An I

C/SPI interface is available for any control and communication with the main micro, as well as RDS data
interface. The DSP SPI block embeds a 10 words FIFO for both transmit and receive channels, to lighten the
DSP task and frequently respond to the interrupt from the control interface.

Serial Audio Interface (SAI) is the ideal solution for the audio data transfer, both transmit and receive: either
master or slave. The flexibility of this module gives a wide choice of different protocols, including I

2

S. Two fully
independent bidirectional data channels, with separate clocks allows the use of TDA7580 as general purpose
digital audio processor.

A fully Asynchronous Sample Rate Converter (ASR C) is available as a peripheral prior to sending audio data
out via the SAI, so that internal audio sampling rate (~36kHz and FM/AM mode) can be adapted by upconver­sion to any external rate.

An Inter Processor Transport Interface (HS
modular system which implements

Dual Tuner Diversity

3

I, High Speed Synchronous Serial Interface) is also available for a

, thus enhancing the overall system performance. It is
about a Synchronous Serial Interfac e which exchan ges data up to the MPX rate. It has been designed to reduce
the Electro Magnetic Interference toward the sensitive analogue signal from the Tuner.

General Purpose I/O registers are connected to and controlled by the DSP, by means of memory map.
A Debug and Test Interface is available for on-chip software debug as well as for internal registers read/write

operation.

2/31

TDA7580

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

VDD

VDD3

Power supplies

Analog Input or Output Voltage belonging to 3.3V IO ring (V
V

DDOSC

Digital Input or Output Voltage, 5V tolerant

All remaining Digital Input or Output Voltage Nom. 1.8V

T

T

stg

Warning: Operat ion at or be yo nd thes e limi ts ma y resu lt in p erma ne nt dam age t o the d evic e. No rma l oper ation is not guara nt eed at these
Note: 1. V

2. During N orm al Mode operation VDD3 is al ways available as specified

3. During Fail-safe Mode operation VDD3 may be not available.

Operating Junction Temperature Range -40 to 125 °C

j

Storage Temperature -55 to 150 °C

extremes.

refers to all of the nom i nal 3.3V power supplies (V

DD3

, V

MTR

).

(V

DD

(1)

Nom. 1.8V
Nom. 3.3V

DDSD

-0.5 to 2.5

-0.5 to 4.0

,

-0.5 to 4.0 V

V
V

)

DDH

, V

OSC

Normal

Fail-safe

Nom. 3.3V

, V

DDSD

(2)
(3)

). V

refers to all of the nominal 1.8V power supplies

DD

-0.5 to 6.50

-0.5 to 3.80

-0.5 to (VDD+0.5)

-0.5 to (VDD3+0.5)

V
V

V

THERMAL DATA

Symbol Parameter Value Unit

R

th j-amb

Thermal resistance junction to ambient 68 °C/W

3/31

TDA7580

PIN CONNECTION

VHI

VCM

VLO

INP

INN
VCMOP
GNDSD

GNDOSC

XTI

XTO
VDDOSC
VDDMTR

CKREFP
CKREFN

AGCKEY

GNDMTR

(Top view)

VDDSD63VDDH62GNDH61VDDISO60GND59VDD58DBOUT157DBRQ156DBIN155DBCK154VDDH53GNDH52DBOUT051DBRQ050DBIN049DBCK0

64

1
2

DEBUG1

DEBUG0

3
4
5

IFADC

6
7
8
9
10

OSC.Tuner

11
12
13
14
15
16

17

C/SPI

2

DSP/RDS

I

19

18

20

21

22

HS3I

23

24

25

26

27

28

RDS

29

30

SAI

31

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

32

GND
VDD
TST3_LRCKR
TST2_SCKR
LRCK_LRCKT
SCLK_SCKT
SDO0
VDDH
GNDH
TST1_SDI1
TST4_SDI0
GPIO_SDO1
TESTN
GND
VDD
RESETN

4/31

VDD

SCL_SCK

GND

IQSYNC

IQCH1

IQCH2

IQCH3

VDDH

GNDH

RDS_INT

RDS_CS

MISO

SDA_MOSI

PROTSEL_SS

IFADC Modulator Power Supply pins pair
Oscillator Power Supply pins pair

Tuner Clock Out and AGC Keying DAC Power Supply pins pair
Core Logic 1.8V Power Supply pins pair

I/O Ring 3.3V Power Supply pins pair

INT

ADDR_SD

PIN DESCRIPTION

N° Name Type Description Notes

TDA7580

After

Reset

1 VHI A Internally generated IFADC Opamps

2.65V (@VDD=3.3V) Reference Voltage
Pin for external filtering

2 VCM A Internally generated Common Mode

1.65V (@VDD=3.3V) Reference Voltage
Pin for external filtering

3 VLO A Internally generated IFADC Opamps

0.65V (@VDD=3.3V) Reference Voltage

Pin for external filtering
4 INP A Positive IF signal input from Tuner 2.0Vpp @VDD=3.3V
5 INN A Negative IF signal input from Tuner 2.0Vpp @VDD=3.3V
6 VCMOP A Internally generated Modulator Opamps

Common Mode 2.65V (@VDD=3.3V)

Reference Voltage Pin for external

filtering
7 GNDSD G IFADC Modulator Analogue Ground Clean Ground, to be

8 GNDOSC G Oscillator Ground Clean Ground, to be

9 XTI I High impedance oscillator input (quartz

connection) or clock input when in

Antenna Diversity slave mode

It needs external 22µF
and 220nF ceramic
capacitors

It needs external 22µF
and 220nF ceramic
capacitors

It needs external 22µF
and 220nF ceramic
capacitors

It needs external 22µF
and 220nF ceramic
capacitors

star-connected to
voltage regulator ground

star-connected to
voltage regulator ground

Maximum voltage swing
is VDD

10 XTO O Low impedance oscillator output (quartz

11 VDDOSC P Oscillator Power Supply 3.3V
12 VDDMTR P Tuner reference clock and AGCKeying

13 CKREFP B Tuner reference clock positive output. FM 100kHz

14 CKREFN B Tuner reference clock negative output. FM 100kHz

15 AGCKEY A DAC output for Tuner AGCKeying 1.5kohm ±30% output

16 GNDMTR G Tuner reference clock and AGC keying

connection)

DAC Power Supply

DAC Ground

1.8V

18kHz

AM

EU

With internal pull_up, on
at reset

AM

18kHz

EU

With internal pull_up, on
at reset

impedance. 1Vpp ±1%
output dynamic range

Output

Output

5/31

TDA7580

PIN DESCRIPTION

(continued)

N° Name Type Description Notes

17 PROTSEL_SS B DSP0 GPIO for Control Serial Interface

2

(Low: SPI or High: I

C) selection at
device Bootstrap.
In SPI protocol mode, after Boot

DSP0 GPIO0
5V tolerant
With internal pull_up, on
at reset

procedure, SPI Slave Select, otherwise
DSP0 GPIO0

18 SDA_MOSI B Control Serial Interface and RDS IO:

- SPI mode: slave data in or master data
out for main SPI and RDS SPI data in

2

C mode: data for main I2C or RDS I2C

- I

19 MISO B SPI slave data out or master data in for

main SPI and RDS SPI data out

5V tolerant
With internal pull_up, on
at reset

DSP0 GPIO1
5V tolerant
With internal pull_up, on
at reset

20 SCL_SCK B Bit clock for Control Serial Interface and

RDS

5V tolerant
With internal pull_up, on

at reset
21 GND G Digital Core Power Ground
22 VDD P Digital Core Power Supply 1.8V

After

Reset

Input

Input

Input

Input

23 IQSYNC B High Speed Synchronous Serial

3

Interface (HS

I) clock if HS3I master
mode, else DSP1 GPIO or DSP1 Debug
Port Clock (DBOUT1)

24 IQCH1 B High Speed Synchronous Serial

3

Interface (HS

I) Channel 1 Data if HS3I
master mode, else DSP1 GPIO or DSP1
Debug Port Request (DBRQ1)

25 IQCH2 B High Speed Synchronous Serial

3

Interface (HS

I) Channel 2 Data if HS3I
master mode, else DSP1 GPIO or DSP1
Debug Port Data In (DBIN1)

26 IQCH3 B High Speed Synchronous Serial

3

Interface (HS

I) Channel 3 Data if HS3I
master mode, else DSP1 GPIO or DSP1
Debug Port Data Out (DBCK1)

27 VDDH P

3.3V IO Ring Power Supply (HS
SPI, RDS, INT)

28 GNDH G

3.3V IO Ring Power Ground (HS
SPI, RDS, INT)

29 RDS_INT B RDS interrupt to external main

microprocessor in case of traffic
information

3

I, I2C/

3

I, I2C/

DSP1 GPIO0
5V tolerant
With internal pull_up, on
at reset

DSP1 GPIO1
5V tolerant
With internal pull_up, on
at reset

DSP1 GPIO2
5V tolerant
With internal pull_down,
on at reset

DSP1 GPIO3
5V tolerant
With internal pull_down,
on at reset

DSP1 GPIO4
5V tolerant
With internal pull_up, on
at reset

Input

Input

Input

Input

Input

6/31

TDA7580

PIN DESCRIPTION

N° Name Type Description Notes

30 RDS_CS B RDS chip select. When RESETN rising,

31 INT I DSP0 External Interrupt 5V tolerantWith internal

32 ADDR_SD B IFS chip master (Low) or slave (High)

33 RESETN I Chip Hardware reset, active Low 5V tolerant

34 VDD P Digital Power Supply 1.8V
35 GND G Digital Power Ground
36 TESTN I Test Enable pin, active Low With internal pull_up
37 GPIO_SDO1 B DSP0 GPIO for Boot selection or Audio

(continued)

If RDS_CS 0, the RDS’s SPI is selected;
else RDS’s I

mode selection, latched in upon
RESETN release. It selects the LSB of

2

the I
Station Detector output

SAI0 output.

2

C

C addresses.

DSP1 GPIO5
5V tolerant
With internal pull_up, on
at reset

pull_up, on at reset
DSP0 GPIO2

5V tolerantWith internal
pull_down, on at reset

With internal pull_up

5V tolerant
DSP0 GPIO3
With internal pull_up, on
at reset

After

Reset

Input

Input

Input

38 TST4_SDI0 B Audio SAI0 Data input or test selection

pin in Test Mode

39 TST1_SDI1 B DSP0 GPIO for Boot selection or Audio

SAI1 input. Test selection pin in Test
Mode.

40 GNDH G 3.3V IO Ring Power Ground (Audio SAI,

ResetN, Test Pins)

41 VDDH P 3.3V IO Ring Power Supply (Audio SAI,

ResetN, Test Pins)

42 SDO0 B Radio or Audio SAI0 data output 5V tolerant

43 SCLK_SCKT B SAI0 Receive and Transmit bit clock

(master or slave with ASRC); SAI1
Transmit bit clock

44 LRCK_LRCKT B SAI0 Receive and Transmit LeftRight

clock (master or slave with ASRC); SAI1
Transmit LeftRight clock

5V tolerant
DSP0 GPIO5With
internal pull_up, on at
reset

5V tolerant
DSP0 GPIO4With
internal pull_up, on at
reset

With internal pull_up, on
at reset

5V tolerant
With internal pull_up, on
at reset

5V tolerant
With internal pull_up, on
at reset

Input

Input

Output

Input

Input

7/31

TDA7580

PIN DESCRIPTION

(continued)

N° Name Type Description Notes

45 TST2_SCKR B SAI0 Transmit bit clock; SAI1 Receive

and Transmit bit clock. Or Test selection
pin in Test Mode

5V tolerant
DSP0 GPIO6
With internal pull_up, on
at reset

46 TST3_LRCKR B SAI0 Transmit LeftRight clock; SAI1

Receive and Transmit bit clock. Or Test
selection pin in Test Mode

DSP0 GPIO7
5V tolerant
With internal pull_up, on

at reset
47 VDD P Digital Core Power Supply 1.8V
48 GND G Digital Core Power Ground
49 DBCK0 B Debug Port Clock of DSP0 (DBCK0) DSP0 GPIO9

5V tolerant

With internal pull_down,

on at reset
50 DBIN0 B Debug Port Data Input of DSP0 (DBIN0) DSP0 GPIO11

5V tolerant

With internal pull_down,

on at reset
51 DBRQ0 B Debug Port Request of DSP0 (DBRQ0) DSP0 GPIO

5V tolerant

With internal pull_up, on

at reset

After

Reset

Input

Input

Input

Input

Input

52 DBOUT0 B Debug Port Data Output of DSP0

(DBOUT0)

53 GNDH G 3.3V IO Ring Power Ground (Debug

Interface, GPIO)

54 VDDH P 3.3V IO Ring Power Supply (Debug

Interface, GPIO)

55 DBCK1 B

DSP1 Debug Port Clock (DBCK1) if HS
master mode, else High Speed

3

Synchronous Serial Interface (HS

I)

Channel3 Data

56 DBIN1 B DSP1 GPIO or DSP1 Debug Port Data

3

In (DBIN1) if HS

I master mode, else

High Speed Synchronous Serial
Interface (HS

3

I) Channel2 Data i

57 DBRQ1 B DSP1 GPIO or DSP1 Debug Port

3

Request (DBRQ1) if HS

I master mode,

else High Speed Synchronous Serial
Interface (HS

3

I) Channel1 Data

DSP0 GPIO10

5V tolerant

With internal pull_up, on

at reset

3

DSP1 GPIO9

I

5V tolerant

With internal pull_down,

on at reset

DSP1 GPIO11

5V tolerant

With internal pull_down,

on at reset

5V tolerant

With internal pull_up, on

at reset

Input

Input

Input

Input

8/31

TDA7580

PIN DESCRIPTION

N° Name Type Description Notes

58 DBOUT1 B DSP1 GPIO or DSP1 Debug Port Data

VDD

59

GND

60
61 VDDISO P 3.3V N-isolation biasing supply Clean 3.3V supply to be

GNDH

62

VDDH

63

VDDSD

64

(continued)

3

Out (DBOUT1) if HS
else High Speed Synchronous Serial

Interface (HS

P Digital Core Power Supply 1.8V
G Digital Core Power Ground

G 3.3V IO Ring Power Ground (Modulator

digital section)

P 3.3V IO Ring Power Supply (Modulator

digital section)

P 3.3V IFADC Modulator Analogue Power

Supply

3

I master mode,

I) clock

DSP1 GPIO10

5V tolerant

With internal pull_up, on

at reset

star-connected to

voltage regulator

Clean Power Supply, to

be star-connected to

3.3V voltage regulator

After

Reset

Input

I/O TYPE

P: Power Supply from Voltage regulator
G: Power Ground from Voltage regulator
A: Analogue I/O
I: Digital Input
O: Digital Output
B: Bidirectional I/O

I/O DEFINITION AND STATUS

Z: high impedance (input)
O: logic low output
X: undefined output
1: logic high output
Output

PP

: Push-Pull/ OD: Open-Drain

9/31

TDA7580

RECOMMENDED DC OPERATING CONDITIONS

Symbol Parameter Comment Min. Typ. Max. Unit

V
V
V

V

DDSD

V

Note: 1. V

1.8V Power Supply Voltage Core Power Supply 1.7 1.80 1.9 V

DD

3.3V Power Supply Voltage (1) IO Rings Power Supply (with G

DDH

3.3V Power Supply Voltage (1) Oscillator Power Supply (GND

OSC

3.3V Power Supply Voltage (1) IF ADC Power Supply (with G

1.8V Power Supply Voltage DAC-Keying and Tuner clock

MTR

Power Supply (with GND

, V

, V

DDH

OSC

are also indi cated in this document as V

DDSD

. All othe rs as VDD.

DD3

) 3.15 3.30 3.45 V

NDH

) 3.15 3.30 3.45 V

OSC

) 3.15 3.30 3.45 V

NDSD

1.7 1.80 1.9 V

)

MTR

GENERAL INTERFACE ELECTRICAL CHARACTERISTICS

Symbol Parameter Test Condition Min. Typ. Max. Unit

l

I

ipdh

l

Low Level Input Current

ilh

I/Os@V
High Level Input Current

ihh

I/Os@V
Low Level Input Current

l

il

I/Os@V
High Level Input Current

l

ih

I/Os@V

DD3

DD3

DD

DD

Pull-down current I/Os @ V

(absolute value)

(absolute value)

(absolute value)

(absolute value)

DD3

V

= 0V (notes 1, 2)

i

without pull-up-down device
V

= V

i

(notes 1, 2)

DD3

without pull-up-down device
V

= 0V (notes 1, 3, 4)

i

without pull-up-down device
V

= VDD (notes 1, 3, 4)

i

without pull-up device
Vi = V

DD3

(note 5)

with pull-down device

1 µA

1 µA

1 µA

1 µA

3.2 6.6 10.0 µA

I

opuh

I

opul

I

aihop

I

acm

I

I

ain

I

aik

I

Pull-up current I/Os @ V

Pull-up current I/Os @ V

DD3

DD

Analogue pin sunk/drawn current
on pin1 and pin 6

Analogue pin sunk/drawn current
on pin 2

Analogue pin sunk/drawn current

ail

on pin 3

Analogue pin sunk/drawn current
on pin 4 and pin 5

Analogue pin sunk/drawn current
on pin 15

Tri-state Output leakage Vo = 0V or V

oz

Vi = 0V(note 6)

-10.0 -6.6 -3.2 µA

with pull-up device
Vi = 0V (note 3)

-5.4 -3.6 -1.8 µA

with pull-up device
Vi = V

DD3

0.95 1.25 1.55 mA
Vi = 0V -6.25 -5.0 -3.75 mA
Vi = V

DD3

1.5 2.0 2.5 mA
Vi = 0V -2.5 -2.0 -1.5 mA
Vi = V

DD3

3.75 5.0 6.25 mA
Vi = 0V -1.55 -1.25 -0.95 mA
Vi = V

DD3

24 32 40 µA
Vi = 0V -40 -32 -24 µA
Vi = V

DD

0.8 1.2 1.6 mA

Vi = 0V (spec absolute value) 1 µA

DD3

(note 1)

1 µA

without pull up/down device

10/31