SGS Thomson Microelectronics TDA7522 Datasheet

Digital Servo & Decoder

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BUILT IN 8Bit MICROCONTROLLER (STANDARD ST7) with:

– 24 KByte ROM available for ST7 & Servo-Audio

DSP – 1024Byte RAM, including 128byte stack – 4KByte RAM for CD-Text memory (for 1block) – Built in R-W subcode buffer (Max. 144Byte

8packs) for CD-Text – 24 bit general I/O port (PoartA[7-0], PortB[7-0],

PortC[7-0]) – One External Interrupt (16 IRQ encoder inside) – 16bit free running counter timer – 8bit 1ch general purpose A/D –I

C bus I/F

(14 x 14 x 1.40mm body)

– Watch dog – Kenwood I/F

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STAND-BY MODE (Stop all clocks and Shut down power of Peripheral (PON pin))

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BUILT IN SERVO & AUDIO DIGITAL SIGNAL PROCESSOr (SAC-DSP) inclusive of: – 1024x19bit Program RAM – 512x16bit Coefficient RAM – 1024x20bit Data RAM – 128x6bit Decimation RAM – MAC: 16 bit (Coefficients) x 20 bit (data) multiplier with 38 bit adder – Instruction execution rate as high as 56MIPS

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BUILT IN PROGRAMMABLE CLOCK GENERATOR PLL

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PERIPHERALS for CD PLAYER APPLICATION – Data Acquisition, Erasure correction, CLV&CAV controller – Subcode decoder (CD-Text, CD-Graphic I/F) – Shock proof memory controller, Disturbance detector – Decimation filter

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ACTUATORS DRIVING MODE SELECTABLE between PWM or PDM MODE

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256Fs / 384Fs (16.9344MHz) CLOCK INPUT.

TQFP80

TDA7522

PRODUCT PREVIEW

May 1998

This is preliminary information on a new product now in development. Details are subject to change without notice.

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TDA7522

1.0 DESCRIPTION TDA7522

Audio. Main concept of this IC is that it is based on embedded System Micro Controller which allows customer to develop system software very easil y: just based on provided commands. Further the microcontroller is fully customer dedicated in terms of both software and general purpose Port.

By combination of ST Analog front-end IC ( Controller and CD-Text function can be realized.

The TDA7522 portfolio is constituted by three different versions: – ’development’: which g ives the possibility to have a t disposal the complete sw develo pment environ-

ment, by means of a dedicated package

– ‘in field development’: standard package but with select ion o f program m em ory: on c hip RAM , on c hip

ROM. The program RAM is fully patchable through the stand ard IIC interface, giving the possibility of sw changing while chip is working in the real environment.

– ‘production’: standard package, but with software permanently stored in the on chip ROM.

2.0 TECHNOLOGY

All version are produced using the HCMOS6 0.35um technology which works @3.3Vdc; to avoid interface problem with existing logics, all digital Inputs are 5V tolerant. When interfacing logic on TDA7522 outputs, user should take care of output levels that are at CMOS level @3.3V. Depending on output type the I and Ioh value are guaranteed at 4mA or 8mA; the TDA7522 output driving specification will be included in a next issue of this data sheet.

is a single chip processor consisting of Decoder, Servo and 1bit D/A for 4times CD-ROM / CD-

TDA7521

), all CD functions including Shock Proof Memory

3.0 ADDITIONAL FEATURES

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16Mbit DRAM I/F allows maximum 9 seconds shock proof

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Built-in 1bit Delta Sigma modulation for DAC

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Subcode P,Q and R-W decoding

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Error Correction is capable of Dual C1 and quadruple C2 erasure corrections

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Jitter absorbing capabilit y: +/- 6 frames

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Automatic fine gain/balance/offset adjustme nt for tracking and focus servos

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Built-in Digital Silence detection

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Built-in EFM Demodulation/Sync Rear and Forward protection

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Soft audio mute

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Built-in Digital PLL with large capture range from 0.5 to 4 times speed

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Digital Servo control for all servo loops

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Capable of 2x and 4x speeds for shock proof and CD-ROM applications

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Capable of wide temperature range (-40C to +85C) stable operation

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Fast access times for CD-ROM applications due to wide Capture range and CAV mode run at max 4 times overspeed

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CLV or CAV (lock-to-disk mode) spindle servo operations

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Digital Output SPDIF (DIT CP340)

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Sony LSI Output Interface (for Audio & CD-ROM)

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Pulsate SLED mode support

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Built in 8times Audio Over sampling filter.

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Figure 1. Pin Connection

TDA7522 general ov erview is reported bel ow. REMARK: CONSIDERING THE SELECTION DONE BY CUSTOMER, THE DRAM I/F COULD BE SLIGTHY MODFIED. DETAILS WILL BE GIVEN IN A LATER ISSUE OF DATA SHEET.

TDA7522

PIN_SERDA 1

PIN_SERCK 2 PIN_DGTLIN0_OF 3 PIN_DGTLIN1_UF 4

PIN_DGTLIN2 5 PIN_DGTLIN3 6 PIN_DGTLIN4 7 PIN_DGTLIN5 8

PIN_DGTLIN_6 9

PIN_CORE_VDD_1 10

PIN_CORE_VSS_1 11

PIN_DGTLIN7 12

PIN_DGTSYNC 13

PIN_CLKOUT 14

PIN_BSR_SDK48 15

PIN_BSL_SAK48 16

PIN_LRCK 17

PIN_C2P0 18

PIN_MUTEL 19

PIN_MUTER 20

PIN_SFSR

PIN_KDMPHYS 21

PIN_DRD0

PIN_CORE_VDD_470

PIN_DRA175PIN_DRA274PIN_DRA373PIN_DRA4

PIN_CORE_VSS_471

PIN_DRA0

PIN_SPDL41PIN_TFSR42PIN_FFSR

PIN_DRD380PIN_DRD279PIN_DRD1

TDA7522

80-pin

PIN_XTI 24

PIN_PON 22

PIN_XTO

PIN_AVSS_1

PIN_AVDD_1 23

PIN_KADC_VRL 28

PIN_KADC_VRH 27

PIN_NRESET

PIN_KADC_IN 29

PIN_CORE_VSS_2

PIN_CORE_VDD_2

PIN_TESTEN

PIN_SCK 34

PIN_DRA569PIN_DRA6

PIN_DRA866PIN_DRA9

PIN_DRA7

PIN_SDA 35

PIN_SCANEN 36

60 59 58 57 56 55 54 53 52

49 48 47 46 45 44 43

PIN_KASEL 37

PIN_KTEST 38

PIN_MSTOP 40

PIN_KSEARCH 39

PIN_DRA10 PIN_DRA11 PIN_RAS PIN_CAS

PIN_DWR PIN_DRS PIN_CLK PIN_DATAM PIN_DATAS PIN_CORE_VSS_351 PIN_CORE_VDD_350 PIN_SRQ

PIN_CS

PIN_DOUT PIN_SCOR PIN_SBSO PIN_EXCK PIN_WFCK PIN_K_VER_HOR PIN_SLEDL

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TDA7522

Table 1. Pin Description

Pin Number Name Function Description

01 SERDA I/O Data line for Serial I/F 02 SERCK O Clock line for Serial I/F 03 DGTLIN0_OF I HF bit 0 and Servo overflow 04 DGTLIN1_UF I HF bit 1 and Servo underflow 05 DGTLIN2 I HF bit 2 and Servo bit 0 06 DGTLIN3 I HF bit 3 and Servo bit 1 07 DGTLIN4 I HF bit 4 and Servo bit 2 08 DGTLIN5 I HF bit 5 and Servo bit 3 09 DGTLIN6 I HF bit 6 and Servo bit 4 10 CORE_VDD_1 Vdd Digital Power supply 11 CORE_VSS_1 Gnd Digital Ground 12 DGTLIN7 I HF bit 7 and Servo bit 5 13 DGTSYNC I Sync strobe for Multiplexer 14 CLKOUT O System clock output to TDA7521 15 BSR_SDK48 O LSI I/F clock output or

DAC bit stream right channel output 16 BSL_SAK48 O LSI I/F data output or DAC bit stream left channel output 17 LRCK O LSI I/F L/R signal 18 C2PO O Validity flag output for CD-ROM decoder 19 MUTEL O Mute left signal (active high) 20 MUTER O Mute right signal (Active high) 21 KDMPHYS I/O De-emphasis indication or ST7 GPIO PA2 22 PON I/O System shutdown pin for power saving mode or

23 AVDD_1 Vdd Analog power supply 24 XTI I Crystal input 25 AVSS_1 Gnd Analog ground 26 XTO O Crystal output 27 KADC_VRH I ADC top reference Voltage input 28 KADC_VRL I ADC bottom reference Voltage input

ST7 GPIO PC7

29 KADC_IN I ADC input 30 CORE_VDD_2 Vdd Digital Power supply 31 CORE_VSS_2 Gnd Digital Ground 32 Nreset I Hardware reset

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Pin Number Name Function Description

33 TESTEN I Test enable signal (Active low) 34 SCK I IIC I/F clock signal 35 SDA I/O IIC I/F data 36 SCANEN I Scan enable (active high) or select DRAM outputs as TEST

outputs when TESTEN is inactive 37 KASEL I/O DAC polarity selection pin or ST7 GPIO PA0 38 KTEST I/O User test mode selection or ST7 GPIO PA1 39 KSEARCH I/O Gain change during search or ST7 GPIO PA3 40 MSTOP I/O interrupt request/stand-by pin or ST7 GPIO PC5 41 SLEDL I/O SLED limit switch or ST7 GPIO PC6 42 K_VER_HOR I/O Indication of vertical or horizontal operation

or ST7 GPIO PA4 43 WFCK O Write Frame clock for Subcode P-W output 44 EXCK I SBSO readout clock input

TDA7522

45 SBSO O Subcode P-W serial output 46 SCOR O Subcode sync output 47 DOUT O SPDIF Digital audio output 48 CS I/O ST7 GPIO PC4 49 SRQ I/O ST7 GPIO PC3 50 CORE_VDD_3 Vdd Digital Power supply 51 CORE_VSS_3 Gnd Digital Ground 52 DATAS I/O ST7 GPIO PC2 53 DATAM I/O ST7 GPIO PC1 54 CLK I/O ST7 GPIO PC0 55 DRS I/O Shock proof memory Read control 56 DWR I/O Shock proof memory Write control 57 CAS I/O Shock proof memory Column address select 58 RAS I/O Shock proof memory Row address select 59 DRA11 I/O DRAM Address 11 60 DRA10 I/O DRAM Address 10 61 DRA9 I/O DRAM Address 9 or Mirror signal output 62 DRA8 I/O DRAM Address 8 or TZC (Tracking Zero Cross) signal output 63 DRA7 I/O DRAM Address 7 or FOK (Focus OK) signal output 64 DRA6 I/O DRAM Address 6 or ST7 GPIO PB7 or PLLINF signal output

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TDA7522

Pin Number Name Function Description

65 DRA5 I/O DRAM Address 5 or ST7 GPIO PB6 or OFS (FIFO Overflow) signal

output 66 DRA4 I/O DRAM Address 4 or ST7 GPIO PB5 or WFCK (Write Frame Clock)

signal output 67 DRA3 I/O DRAM Address 3 or ST7 GPIO PB4 or RFCK (Read Frame Clock)

signal output 68 DRA2 I/O DRAM Address 2 or ST7 GPIO PB3 69 DRA1 I/O DRAM Address 1 or ST7 GPIO PB2 70 CORE_VDD_4 Vdd Digital Power supply 71 CORE_GND_4 Gnd Digital Ground 72 DRA0 I/O DRAM Address 0 or ST7 GPIO PB1 73 DRD0 I/O DRAM Data 0 or ST7 GPIO PA5 74 DRD1 I/O DRAM Data 1 or ST7 GPIO PA6 75 DRD2 I/O DRAM Data 2 or ST7 GPIO PA7 76 DRD3 I/O DRAM Data 3 or ST7 GPIO PB0 77 SPDL O PWM/PDM Spindle motor control signal output 78 TFSR O PWM/PDM Tracking actuator control signal output 79 FFSR O PWM/PDM Focusing actuator control signal output 80 SFSR O PWM/PDM SLED motor control signal output

Note: 1. Depending from new DRAM sel ection pin nr.59 could be not used in prod uction versi on.

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Figure 2. Block Diagram

TDA7522

CD TEXT Graphical

4M / 16M bit DRAM

Interface

GPIO

I2C I/F

PDM / PWM

Track Loop filter

Focus Loop filter

SLED Loop filter

ADC

ADC In

4ch Driver IC

ex. TDA7 473

Focus Actuator

Track Actuator

Sled Motor

Spindle Motor

Digital

SPDIF

CLV/CAV

Shock proof

Memory

Subcode

out

controller

decoder

Out

LSI Digital

16Kbit

Cross Inter l eaving

Digital PLL &

Sync protection &

RAM

Reed-Solomon

EFM demodulator

LSI I/F

CD Text Extractor

I2C

bus

ST7

24KB ROM

1kbyte RAM

Delta

Sigma

Modulation

8x Audio OVS

Audio Processing

TDA7522(80pins)

TDA7521(44pins)

TDA7521 I/F Contro l

MPU I/F

Digital

Laser

Servo

Adjustment

Down

sampling

filter

Clock

ADC

1bit DAC

ST7 Clock

Peripherals Clock

DSP Clcok

PLL

Analog

+ filter

PLL

External Qu ar tz

AUDIO out

Slicer

Equalization

control

Disturbance

(Mirror) detector

HFACBDEF

ADC

A+C

DSP

Amp

B+D

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