SGS Thomson Microelectronics TDA7521 Datasheet
TDA7521
Analog Front End
PRODUCT PREVIEW
TDA7521 is a BiCMOS analog front end for CD applications. Four input signals (AC*, BD*, E* and F*),
coming from the pick-up (whose laser diode is driven
and controlled by the device itself), are preamplified
by a programmable voltage-to-voltage or current-tovoltage stage, depending on the used pick-up. The
output signals from the preamplifier stage (AC, BD, E,
F and HF, a radio frequency signal obtained by combining the photo-detector outputs as A+B+C+D) are
fed to an 8-bit HF ADC (for HF, which carries encoded
audio data) and a 6-bit Servo ADC (for AC, BD, E and
F, used for focusing, tracking the laser beam and controlling revolution speed). All these signals are digitized, multiplexed, synchronized with the external
clock (768×Fs or 394×Fs, Fs=44.1KHz) and fed tothe
digital counterpart in one only digital stream (AC/HF/
BD/HF/E/HF/F/HF). Two stereo DACs convert the input bitstreams from TDA7522.
All the clock signals (for ADCs and DACs) are generated by a low-jitter PLL-based clock manager. All
TDA7521’s analog preprocessing is controlled by TDA7522 bymeans of an UART interface (which implements an I2C-like protocol). Housed in a TQFP 44, 10×10mm package, TDA7521 features the functions
shown in figure below.
TDA7521 uses the HF4CMOS technology and is supplied @5Vdc.
(10 x 10 x 1.40 mm body)
TQFP44
May 1998
This is preliminary information on a new product now in development. Details are subject to change without notice.
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TDA7521
Figure 1. TDA7521 Block Diagram
REF IN
PON
AC
BD
E
F
REF
REF OUT
HF MON
CLOCK
REXT
Gen
I/V
I/V
I/V
RF
RF
ADC
ADC
Servo
I/V
Laser
ControlI/F
SDA SCL LD MD DL DR
Driver
ADC
Output MUX
Stereo
DAC
MUTEL MUTER
FILT
CKIN
Mgr
SYNC
d0
d1
d2
d3
d4
d5
d6/OF
d7/UF
OUTL
OUTR
1.0 HARDWARE DESCRIPTION
1.1 Clock source and generation
The master clock to operate the device is 768×Fs (High Frequency mode, HFM) or 384×Fs (Low Frequen-
cy mode, LFM). Fs=44.1KHz for CD applications. In either case, the clock is generated by TDA7522: an
internal low-jitter Charge-Pump PLL (CPPLL) and a Finite State Machine (FSM) synthesize all the needed
clocks for the internal blocks: a 512×Fs for the DAC and three 384×Fs (HFM) or 192×Fs (LFM), with dif-
ferent phases for ADCs and output digital multiplexer. The required loop filter network is made up of a
160pF capacitor from FILT to GND_pll in parallel with the series of a 10nF and a 4KΩ resistor. All clock-
related setups are communicated to TDA7521 via UART interface.
1.2 Voltage references
REFIN is an internal voltage reference generated by a resistor divider between VCC_dac and VSS_dac.
Nominal value (with VCC_dac=5V) is REFIN=2.5V. Careful filtering of this pin is essential; recommended
value of external capacitor is 47µF paralleled with 100nF ceramic. REFOUT is a 2.5V (nominal) buffered
output to bias the pickup. All the internal voltage references for ADCs and DACs are generated by bandgap-based circuits, thus allowing to reduce the noise induced by the power supply.
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TDA7521
1.3 Laser driver section
The laser driver system is composed by the pick-up, the laser driver and the external PNP bipolar transistor. It controls the external pick-up current level (up to 100mA) through its base current in order to maintain
a certain amount of diode power emission, independently from temperature and aging effects. This is done
in a digital way by using a 6-bit DAC to set the monitor diode analog reference voltage at a constant level
(and so the current in the laser diode). Thus, 26-1 different bias currents (with relative monitor voltage between 100 and 300mV) can be selected via UART interface. A negative feedback loop sets both the monitor diode voltage and the laser diode bias current.
1.4 Preamplifier section
The goal of this section is to free the four voltage signals coming from either the CD pickup itself (voltage
inputs) or the internal current-to-voltage converters (current inputs) from their intrinsic DC component and
to amplify them to a level suitable for efficient A/D conversion. In case of current inputs, four transimpedance amplifiers convert the currents from AC (A+C), BD (B+D), E andF inputs intooutput voltages suitable
for the programmable preamplification chain; otherwise, this stage is by-passed and the voltageinputs are
directly connected to the preamplification stage. The two paths (for input current or input voltage) are digitally selected via UART interface. In the same way also the gain of the path and the offset cancellation for
the preamplification chain are controlled (the gain programmability range is spanning from 6 up to 29.5dB
in 48 discrete steps of 0.5dB each, while the offset nulling circuit allows a minimum correction step of about
22mV via a 6-bit DAC). Moreover the preamplification chain generates an HF signal, which carries the encoded audio data and is obtained by combining the photo-detector outputs as A+B+C+D. All these signals
(AC, BD, E, F and HF), which can be evaluated by means of the monitor output, are fed to the ADC section.
1.5 ADC section
The HF and servo (AC, BD, E and F) paths are digitized by means of two ADCs: the former (8-bit resolution, interleaved comparator two step architecture) samples theHF signal at a frequency of 384×Fs (HFM)
or 192×Fs (LFM), the latter (6-bit resolution, interleaved comparator two step architecture) allows to multiplex the data for the servo path (AC, BD, E and F) in an only analog signal AC/BD/E/F and samples this
signal at 384×Fs (HFM) or 192×Fs (LFM); that means each servo signal is sampled at 96×Fs or 48×Fs).
Then both the bitstreams (HF and AC/BD/E/F) are digitally multiplexed in a single bitstream (AC/HF/BD/
HF/E/HF/F/HF). A SYNC signal (high during the period of HF before AC output) is provided in order to
point out the start of a new frame. It is worth noting that output data change on the falling edge of the master clock.
The Table 1 shows the output data format for the ADC section: referring to AC/HF/BD/HF/E/ HF/F, the HF
signal have an
the servo path (AC, BD, E and F) have a different format:
from the preamplifiers plus underflow and overflow
8-bit format which represents the digitized value of the HF analog signal
6 bit for the digitized value of the analog output
(1)
.
, while the data for
Table 1. TDA7521 Output Format
LSB MSB
D0 D1 D2 D3 D4 D5 D6/UF D7/OF
Note: 1. Overflow and Underflow for the HF ADC are latched by a dedicated FSM and read via UART interface.
1.6 DAC section
In TDA7521 are present two 3rd order SC smoothing filters to be used in Digital-to-Analog conversion. Its
input signal is a bitstream created by a 2nd order digitalΣ∆modulator present in TDA7522. From there
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TDA7521
the bitstream is passed to the analog chip and properly processed by the filter. The filter exhibits 96dB
SNR and more than -80dB THD for a full scale input signal.
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