SGS Thomson Microelectronics TDA7503 Datasheet



DUAL DSP PLUS MICRO FOR AUDIO APPLICATIONS

Dual 24-bit40 MIPS DSP Cores 8 bit Microcontroller 4 receive and 5 transmit stereo channels of

Serial Audio Interface Synchronous Serial Interface for communica-

tion with external processor FIFO based mailboxes for inter-processor

communications External Memory Interface to 128Kb SRAM or

1Mb DRAM CORDICco-processor Programmable PLL to suite wide range of ex-

ternalcrystal oscillationfrequencies SPI controlinterface Powerfuldebuginterfaces 1280 words Program Memory for DSP1, 768

words Program Memoryfor DSP0 256 words X and Y Data RAM and Data ROM

for each DSP 256 byte Data RAM for Microcontroller 768 byte Auxiliary RAMfor Microcontroller

BLOCK DIAGRAM

TDA7503

PRODUCT PREVIEW

TQFP100

DESCRIPTION

The device is a high-performance Digital Signal ProcessingIC particularly suitedto Audio applications. The device contains two 24-bit 40 MIPS DSP cores delivering a total of 80 MIPS of DSP processing power. There is also an embedded 8bit Microcontrollerto handle all control functions. All data and program memories for both DSP cores are on-chip. A variety of highly programmable and flexible peripheral blocks for both the Microcontroller and the DSPs have been integrated to form a powerful audio processing system on a single chip.

Host Interface 0

Host Interface1

Serial Audio Interface

XDB0 XAB0

XDB1 XAB1

Synchronous Audio Interface

SRAM/ DRAM Interface

XCHG Interface

Cordic Arithmetic Unit

M8051 CORE

Control

Interface

Peripheral

Micro Memory Interface

Serial

Watchdog Timer

MCLK

PLL Clock Oscillator

AUX-RAM 768 Bytes

AUX-RAM 256 Bytes

DCLK

YAB0

XDB0

XAB0

DSP0 CORE

YDB0

PAB0

PDB0

X-RAM0 X-ROM0

Y-RAM0 Y-ROM0

P-RAM0 P-ROM0

XDB1

XAB1

DSP1 CORE

YAB1

YDB1

PAB1

PDB1

X-RAM1 X-ROM1

Y-RAM1 Y-ROM1

P-RAM1 P-ROM1

DEBUG Interface

July 1999

This is preliminaryinformation on a new product now in development. Details are subject to change without notice.

1/26

TDA7503

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V

DDC

V

DDP

V

I,VIN

T

op

T

stg

PIN CONNECTION

Core DC Supply voltage -0.5 to 5 V Pads DC Supply voltage -0.5 to 6.5 V Digital or analog input voltage -0.5 to (V

+0.5) V

DDP

Operative temperature range -40 to 85 °C Storage temperature range(plastic) -55 to 150 °C

RD(P3.7)

WR(P3.6)

xALE

RAD0(P0.0)

RAD2(P0.2)

RAD1(P0.1)

RAD3(P0.3)

RAD4(P0.4)

RAD5(P0.5)

RAD6(P0.6)

RAD7(P0.7)

RA10(P2.2)

75

VSSI3_CORE4

74

VDDI3_CORE4

73

VSSE5_MI1

72

VDDE5_MI1

71 70

XPSEN

69

RA11(P2.3)

68

RA9(P2.1) RA8(P2.0)

67

RA13(P2.5)

66

RA14(P2.6)

65 64

RA15(P2.7)

63

RA12(P2.4)

62

SRA10/DRA6

61

DRD

60

SRA11/DRA7

59

SRA9/DRA5

58

VDDE5_DR2

57

VSSE5_DR2

56

SRA8/DRA4

55

SRA13/RAS

54

VSSI3_CORE1

53

VDDI3_CORE1

52

DWR

51

ALE/CAS

T1(P3.5)

VDDI3_CORE3

VSSI3_CORE3

RESET

MISO MOSI SCLK

SS/GPIOS

VSSE5_CI1

VDDE5_CI1

LRCKR SCLKR

SDI3 SDI2 SDI1

SDI0 SDO4 SDO3 SDO2 SDO1 SDO0

VSSI3_CORE2

VDDI3_CORE2

SCLKT LRCKT

T0(P3.4)

100 99 98

1 2 3 4 5 6 7 8 9 10

12 13 14 15 16 17 18 19 20

21 22 23

24 25

26 27 28

TXD(P3.1)

RXD(P3.0)

GPIO6(P1.6)

GPIO5(P1.5)

GPIO3(P1.3)

GPIO4(P1.4)

INT0(P3.2)

INT1(P3.3)

97 96 95 94 9293 91 90 89 88 87

29 30 31 32 33

VDDE5_MI2

34 35 36 37 38 39

VSSE5_MI2

GPIO2(P1.2)

GPIO1(P1.1)

GPIO0(P1.0)

86 85 84 83 8182 80 79 78 77 76

40 41 42 43 44

451146 47 48 49 50

XTI

FILT

XTO

VSSE5_SA1

VDDE5_SA1

PGND

PVCC

TESTEN

SCANEN

DBOUT

DBCK/OS1

DBRQN

DBIN/OS0

DBSEL

SRA_D7/DRA3

VDDE5_DR1

SRA_D6/DRA2

SRA_D5/DRA1

SRA_D4/DRA0

VSSE5_DR1

SRA_D3/DRD3

SRA_D2/DRD2

SRA12/DRA8

SRA_D1/DRD1

SRA_D0/DRD0

D97AU693

THERMAL DATA

Symbol Parameter Value Unit

Thermal resistance Junction to Ambient 85 °C/W

2/26

R

th j-amb

PIN DESCRIPTION

TDA7503

N. Name Type

11 LRCKR I – Audio Serial Port Receive Left/Right Frame Sync. The Left/Right select

12 SCLKR I – Audio Serial Port Receive Bit Clock. SCLK clocks receiveddigital audio

16 SDI0 I – StereoDigitalAudioData.SDI0is a stereodigital audiodatainput pin

15 SDI1 I – StereoDigitalAudioData.SDI1is a stereodigital audiodatainput pin

14 SDI2 I – StereoDigitalAudioData.SDI2is a stereodigital audiodatainput pin

13 SDI3 I – Stereo Digital Audio Data / Serial Receive Data. SDI3 is a stereo digital

25 LRCKT I – Audio Serial Port Transmit Left/Right Frame Sync /Frame Sync. The

24 SCLKT I – Audio Serial Port Transmit Bit Clock/SSI SerialBit Clock. SCLK clocks

21 SDO0 O High StereoDigitalAudio Data. SDO0is a stereodigitalaudiodataoutput pin

20 SDO1 O High StereoDigitalAudio Data. SDO1is a stereodigitalaudiodataoutput pin

19 SDO2 O High StereoDigitalAudio Data. SDO2is a stereodigitalaudiodataoutput pin

18 SDO3 O High StereoDigitalAudio Data. SDO3is a stereodigitalaudiodataoutput pin

17 SDO4 O High Stereo Digital Audio Data /Serial Transmit Data. SDO4 is a stereo digital

34 SCANEN I – SCAN Enable.Enable SCAN Path andMUXingofSCANINand SCANOUT

33 TESTEN I – Test Enable. Enable Scan Mode Clocks. An active low signal will enable

49 SRA_D0/DRD0 I/O I DSP SRAM Multiplexed Address/Data Line 0/DSP DRAM Data Line

48 SRA_D1/DRD1 I/O I DSP SRAM Multiplexed Address/Data Line 1/DSP DRAM Data Line

47 SRA_D2/DRD2 I/O I DSP SRAM Multiplexed Address/Data Line 2/DSP DRAM Data Line

46 SRA_D3/DRD3 I/O I DSP SRAM Multiplexed Address/Data Line 3/DSP DRAM Data Line

43 SRA_D4/DRA0 I/O O, High DSP SRAM Multiplexed Address/Data Line 4/DSP DRAM Address Line

Reset

Status (1)

Function

signal for received serial audiodata. This signal has a frequency equal to the audio sample rate.

data into pins SDI0, SDI1, SDI2, and SDI3

channel 0.

channel 1.

channel 2.

audio data input pinand is multiplexed with the SSI’s Serial Receive Data Input channel 3.

Left/Right select signal for transmittedserial audio data. This signal has a frequency equal to the audio sample rate. This signal is multiplexed with the SSI’s Frame Sync Input.

digital audio data out of pinsSDO0, SDO1, SD02, SD03, and SD04. This pin is multiplexed with the SSI’s serial bitclock.

channel0.

channel1.

channel2.

channel3.

audio data output pin and is multiplexed with the SSI’s Serial Transmit Data Output channel4.

Pins.

the same clock to all scan chains. This pin also makes all latches transparent.

0.When in SRAM Mode these pins act as the EMI multiplexed address and data line 0. When in DRAM Mode they act as the EMI data line 0.

1.When in SRAM Mode these pins act as the EMI multiplexed address and data line 1. When in DRAM Mode they act as the EMI data line 1.

2.When in SRAM Mode these pins act as the EMI multiplexed address and data line 2. When in DRAM Mode they act as the EMI data line 2.

3.When in SRAM Mode these pins act as the EMI multiplexed address and data line 3. When in DRAM Mode they act as the EMI data line 3.

0. When in SRAM Mode these pins act as theEMI multiplexed address and data line 4. When in DRAM Mode they act as the EMI address line 0.

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TDA7503

PIN DESCRIPTION

N. Name Type

42 SRA_D5/DRA1 I/O O, High DSP SRAM Multiplexed Address/Data Line 5/DSP DRAM Address Line

41 SRA_D6/DRA2 I/O O, High DSP SRAM Multiplexed Address/Data Line 6/DSP DRAM Address Line

40 SRA_D7/DRA3 I/O O, High DSP SRAM Multiplexed Address/Data Line 7/DSP DRAM Address Line

56 SRA8/DRA4 O High DSP SRAM Address Line 8/DSP DRAM Address Line 4. When in SRAM

59 SRA9/DRA5 O High DSP SRAM Address Line 9/DSP DRAM Address Line 5. When in SRAM

62 SRA10/DRA6 O High DSP SRAM Address Line 10/DSP DRAM Address Line 6. When in

60 SRA11/DRA7 O High DSP SRAM Address Line 11/DSP DRAM Address Line 7. When in

50 SRA12/DRA8 O High DSP SRAM Address Line 12/DSP DRAM Address Line 8. When in

55 SRA13/RAS O High DSP SRAM Address Line 13/DRAM Row Address Strobe. When in

51 ALE/CAS O High DSP SRAM Address latch enable/colomn Address. When in SRAM

52 DWR O High DSP SRAM Write Enable/DRAM WriteEnable. This pin serves as the

61 DRD O High DSP SRAM Read Enable/DRAM Read Enable. This pinserves as the

36 DBCK/OS1 I/O I Debug Port Bit Clock/Chip Status 1. The serial clock for the Debug Port

37 DBIN/OS0 I/O I Debug Port Serial Input/Chip Status 0. The serial data input for the

35 DBOUT I/O I Debug Port Serial Output. The serial data output for the Debug Port. Can

38 DBRQN I – Debug Port Request Input. Means of entering the Debug mode of

39 DBSEL I – Debug Port MUX Selection. Selects either DSP0 or DSP1 to be

67 RA8(P2.0) I/O I Microcontroller High Byte Address Lines.This pin is the address line 8 of

68 RA9(P2.1) I/O I Microcontroller High Byte Address Lines.This pin is the address line 9 of

(continued)

Status (1)

Reset

Function

1. When in SRAM Mode these pins act as theEMI multiplexed address and data line 5. When in DRAM Mode they act as the EMI address line 1.

2. When in SRAM Mode these pins act as theEMI multiplexed address and data line 6. When in DRAM Mode they act as the EMI address line 2.

3. When in SRAM Mode these pins act as theEMI multiplexed address and data line 7. When in DRAM Mode they act as the EMI address line 3.

Mode these pins act as the EMI address line 8.When in DRAM Mode they act as the EMI address line 4.

Mode these pins act as the EMI address line 9.When in DRAM Mode they act as the EMI address line 5.

SRAM Mode these pins act as the EMI address line 10.When in DRAM Mode they act as the EMI address line 6.

SRAM Mode these pins act as the EMI address line 11. When in DRAM Mode they act as the EMI address line 7.

SRAM Mode these pins act as the EMI address line 12. When in DRAM Mode they act as the EMI address line 8.

SRAM Mode this pin acts as the EMI address lines 13. When in DRAM Mode this pin acts as the row address strobe.

Mode this pin acts as the EMI Address Latch Enable. When in DRAM Mode this pin acts as the column address strobe.

write enable for the EMI when in DRAM and SRAM Modes.

read enable for the EMI when in DRAM and SRAM Modes.

is provided when an input. When an output, together with OS0 provides information about the chip status. Can also be used as GPIO for the

8051.

Debug Port is provided when an input. When an output, together with OS1 provides information about the chip status. Can also be used as GPIO for the 8051.

also be used as a GPIO for the 8051.

operation.

connected to the Debug Port pins.

a 16 bit address, for external EPROM and memory mapped devices. It can also actas GPIO using the P2 and P2DIR registers.

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TDA7503

PIN DESCRIPTION

N. Name Type

75 RA10(P2.2) I/O I Microcontroller High Byte Address Lines. This pin is the address line 10

69 RA11(P2.3) I/O I Microcontroller High Byte Address Lines. This pin is the address line 11

63 RA12(P2.4) I/O I Microcontroller High Byte Address Lines. This pin is the address line 12

66 RA13(P2.5) I/O I Microcontroller High Byte Address Lines. This pin is the address line 13

65 RA14(P2.6) I/O I Microcontroller High Byte Address Lines. This pin is the address line 14

64 RA15(P2.7) I/O I Microcontroller High Byte Address Lines. This pin is the address line 15

83 RAD0(P0.0) I/O I Microcontroller Address/Data Pins. This pin is the multiplexed address

82 RAD1(P0.1) I/O I Microcontroller Address/Data Pins. This pin is the multiplexed address

81 RAD2(P0.2) I/O I Microcontroller Address/Data Pins. This pin is the multiplexed address

80 RAD3(P0.3) I/O I Microcontroller Address/Data Pins. This pin is the multiplexed address

79 RAD4(P0.4) I/O I Microcontroller Address/Data Pins. This pin is the multiplexed address

78 RAD5(P0.5) I/O I Microcontroller Address/Data Pins. This pin is the multiplexed address

77 RAD6(P0.6) I/O I Microcontroller Address/Data Pins. This pin is the multiplexed address

76 RAD7(P0.7) I/O I Microcontroller Address/Data Pins. This pin is the multiplexed address

84 xALE I/O I Microcontroller External Address Latch Enable. This pin is the address

85 WR(P3.6) I/O I Microcontroller Write Strobe. External data memory write strobe. This pin

86 RD(P3.7) I/O I Microcontroller Read Strobe. External data memory readstrobe. Active

70 XPSEN I/O I Microcontroller External Program Memory Enable. External program

(continued)

Status (1)

Reset

Function

of a 16 bit address, for external EPROM and memory mapped devices. It can also actas GPIO using the P2 and P2DIR registers.

and data line bit 0 for external EPROM and memory mapped peripherals. It can also actas GPIO using the P0 and P0DIR registers.

and data line bit 1 for external EPROM and memory mapped peripherals. It can also actas GPIO using the P0 and P0DIR registers.

and data line bit 2 for external EPROM and memory mapped peripherals. It can also actas GPIO using the P0 and P0DIR registers.

and data line bit 3 for external EPROM and memory mapped peripherals. It can also actas GPIO using the P0 and P0DIR registers.

and data line bit 4 for external EPROM and memory mapped peripherals. It can also actas GPIO using the P0 and P0DIR registers.

and data line bit 5 for external EPROM and memory mapped peripherals. It can also actas GPIO using the P0 and P0DIR registers.

and data line bit 6 for external EPROM and memory mapped peripherals. It can also actas GPIO using the P0 and P0DIR registers.

and data line bit 7 for external EPROM and memory mapped peripherals. It can also actas GPIO using the P0 and P0DIR registers.

latch enable. A logic high indicates that address/data lines 7 through 0 represent an address. Inactive for Program/Data fetches from internal AUX.

can also actas GPIO using the P3 and P3DIR registers.

Low, or GPIO. Thispin can also act as GPIO using the P3 and P3DIR registers. Disabled by setting the RDSEL bit in the PINCTL register.

memory enable pin. Active Low. Changes functionality to RD when Microcontroller is fetching instructions out of internal AUX ram. Controlled by the PSSEL and PSBIT bits in the PINCTL register.

5/26

TDA7503

PIN DESCRIPTION

N. Name Type

4 RESET I/O I System Reset. A logic low level applied to RESET input initializes the

96 RXD(P3.0) I/O I Microcontroller Standard Serial Interface (Asynchronous) Input Data. Or

97 TXD(P3.1) I/O I Microcontroller Standard Serial Interface (Asynchronous) Output Data.

99 INT0(P3.2) I/O I Microcontroller Interrupt 0. When pulled low, INT0 asserts a

98 INT1(P3.3) I/O I Microcontroller Interrupt 1. When pulled low, INT1 asserts a

100 T0(P3.4) I/O I Microcontroller Timer 0 External Input. Input event clock for timer 0, or

1 T1(P3.5) I/O I Microcontroller Timer 1 External Input. Input event clock for timer 1, or

87 GPIO0(P1.0) I/O I Microcontroller General Purpose. This GPIO linecan be configured to be

88 GPIO1(P1.1) I/O I Microcontroller General Purpose. This GPIO linecan be configured to be

89 GPIO2(P1.2) I/O I Microcontroller General Purpose. This GPIO linecan be configured to be

92 GPIO3(P1.3) I/O I Microcontroller General Purpose. This GPIO linecan be configured to be

93 GPIO4(P1.4) I/O I Microcontroller General Purpose. This GPIO linecan be configured to be

94 GPIO5(P1.5) I/O I Microcontroller General Purpose. This GPIO linecan be configured to be

95 GPIO6(P1.6) I/O I Microcontroller General Purpose. This GPIO linecan be configured to be

7 SCLK I/O I Microcontroller General Purpose. Each of the six GPIO lines canbe

6 MOSI I/O I Microcontroller SPI Master Output Slave Input Serial Data . Serial Data

(continued)

Status (1)

Reset

Function

microcontroller. The micro is responsible for initializing the DSPs. If the watchdog timer overflow occurs this pin is driven low for 1 watchdog timer cycle. During Debug Mode if this pin is pulled low in while the DBRQN line is pulled low then the DSP pointed to by the DBSEL pin will be reset.

GPIO. This pin can also act as GPIO using the P3 and P3DIR registers.

Or GPIO. This pin can also act as GPIO using the P3 and P3DIR registers.

microcontroller external interrupt. In addition,if this pin is pulled low during powerdown this allowsthe M8051 to resume executing intructions where it left off. This pin can also act as GPIO using the P3 and P3DIR registers.

GPIO. This pin can also act as GPIO using the P3 and P3DIR registers.

digital input or output bywriting to the P1 and P1DIR registers.This pin is tri-stated while the RESET pin is held low and is pulled low when RESET is released. This pin will be pulled high when in IDLE or PWRDN modes.

digital input or output bywriting to the P1 and P1DIR registers. At reset it is configured as an input with the output tri-stated.

individually configured to be digitalinput oroutput by writing to the P1 and P1DIR registers. All GPIOs are configured to be inputs with the outputs tri-stated except for P1.0. This pin is tri-stated during while the RESET pin is held low and is pulled low when RESET is released. This pin will be pulled high whenin IDLE or PWRDN modes.

Output for SPI type serial port when in SPI Master Mode andSerial Data Input when in SPI Slave Mode.

6/26

TDA7503

PIN DESCRIPTION

N. Name Type

5 MISO I/O I Microcontroller SPI Master Input Slave Output Serial Data . Serial Data

8 SS/GPIOS I/O I Microcontroller SPI Slave Select . Slave Select Input for SPI type serial

32 PVCC I – PLL Clock Power Supply . Vdd Pin for PLL Clock Oscillator. 28 XTO O High Crystal Oscillator Output. Crystal Oscillator output drive. 29 XTI I – Crystal Oscillator Input. External Clock Input or crystal connection. 30 FILT O High PLL Loop Filter Capacitor Output. Capacitor connected between FILT

31 PGND I – PLL Clock GroundInput. Ground connection for oscillator circuit. 53 VDDI3_CORE1 PWR – 3.3V core supply. 23 VDDI3_CORE2 PWR – 3.3V core supply.

2 VDDI3_CORE3 PWR – 3.3V core supply. 73 VDDI3_CORE4 PWR – 3.3V core supply. 54 VSSI3_CORE1 GND – Core ground. 22 VSSI3_CORE2 GND – Core ground.

3 VSSI3_CORE3 GND – Core ground. 74 VSSI3_CORE4 GND – Core ground. 27 VDDE5_SA1 PWR – 5V supply for SAI pads. 26 VSSE5_SA1 GND – Ground for SAI pads. 10 VDDE5_CI1 PWR – 5V supply for Control Interface Pads.

9 VSSE5_CI1 GND – Ground forControl Interface Pads. 71 VDDE5_MI1 PWR – 5V supply for Micro Memory Interface Pads. 91 VDDE5_MI2 PWR – 5V supply for Micro Memory Interface Pads. 72 VSSE5_MI1 GND – Ground forMicro Memory Interface Pads. 90 VSSE5_MI2 GND – Ground forMicro Memory Interface Pads. 44 VDDE5_DR1 PWR – 5V supply for DSP EMI Interface Pads. 58 VDDE5_DR2 PWR – 5V supply for DSP EMI Interface Pads. 45 VSSE5_DR1 GND – Ground for DSP EMI Interface Pads. 57 VSSE5_DR2 GND – Ground for DSP EMI Interface Pads.

(continued)

Status (1)

Reset

Function

Input for SPI style serial port when in SPI Master Mode and Serial Data Output when in SPI Slave Mode.

port. This pin can be used as a GPIO when the SPI is disabled or in master mode.

and XGND establishes primary PLL.

7/26

TDA7503

RECOMMENDED DC OPERATING CONDITIONS

Symbol Parameter Test Condition Min. Typ. Max. Unit

V

DDC

DDP 5V Power Supply Voltage 4.5 5 5.5 V

V

Tj Operating Junction

GENERAL INTERFACE ELECTRICALCHARACTERISTICS

Symbol Parameter Test Condition Min. Typ. Max. Unit Note

I

il

I

ih

I

oz

C

in

I

latchup

V

esd

Note 1: Theleakage currents are generally very small, < 1nA. The value given here, 1mA, is a maximum that can occur after an Electrostatic Stress on the pin.

Note 2: Guaranteedby design. Note 3: Human Body Model.

3.3V Power Supply Voltage 3 3.3 3.6 V

-40 125 °C

Temperature

Low Level Input Current

Vi=0V 1 µA1

Without pull-up device High Level Input Current

Vi = V

DDP

1 µA1

Without pull-down device Tri-state Output leakage

Vo = 0V or V

DDP

1 µA1

Without pullup/down device Input capacitance 10 pF 2 I/O Latch-up Current V < 0V, V > V

DDP

200 mA

Electrostatic Protection Leakage < 1µA 2000 V 3

DC ELECTRICAL CHARACTERISTICS

Symbol Parameter Test Condition Min. Typ. Max. Unit Note

V

il

V

ih

V

ol

V

oh

Note 1: Takes intoaccount 200mV voltage drop in both supply lines.

Low Level Input Voltage 0.25⋅V High Level Input Voltage 0.7⋅V Low Level Output Voltage Iol= 2mA 0.4 V 1 High Level Output Voltage Iol= -2mA V

8/26

DDP

-0.4 V 1

DDP

V V