The TDA7464 is a volumetone (bass middle and
treble) balance (Left/Right) processorswith stereo
SRS and voicecanceller for quality audio applications in car radio, Hi-Fi, TV systems.
It reproduces SRS (Sound Retrieval System)
sound by external components and surround
sound by using phase shifters and a signal matrix. The AC signal setting is obtained by resistor
networks and switches combined with operational
amplifiers according to the SRS laboratories
TDA7464
TQFP44
ORDERING NUMBER: TDA7464
PIN CONNECTION
LP
PS1
PS2
PS3
VSPS4
CREF
R_IN4
R_IN3
R_IN2
LPVC
44 43 42 41394038 37 36 35 34
1
LP1
2
HP1
3
HP2
4
NETW1
5
NETW2
6
VAR_L
VAR_R
7
8
9
10
12 13 14 15 16
BASS_RI
BASS_RO
MIDDLE_LI
MIDDLE_LO
MIDDLE_RO
171118 19 20 21 22
SDA
AGND
TREBLE_L
TREBLE_R
MIDDLE_RI
BASSO_L
BASSO_R
BASS_LO
BASS_LI
specification. Control of all the functions is accomplishedby serial bus.
Thanks to the used BIPOLAR/CMOSTechnology,
Low Distortion, Low Noise and DC stepping are
obtained.
THDTotal Harmonic DistortionV = 1Vrms f = 1KHz0.010.1%
S/NSignal to Noise Ratio V
S
Thermal Resistance Junction-pinsMax.85°C/W
Operating Supply Voltage11V
S
Operating Ambient Temperature-10 to 85
Storage Temperature Range-55 to +150°C
stg
Supply Voltage7910.2V
S
CL
Max. input signal handling2Vrms
out = 1Vrms (mode = OFF)106dB
Channel Separation f = 1KHz90dB
C
Input Attenuation Control (0.5dB)-31.50dB
Treble Control (2db step)-14+14dB
Middle Control (2db step)-14+14dB
Bass Control (2dB step)-14+14dB
Balance Control 1dB step (L
CH, RCH)-790dB
Mute Attenuation100dB
C
°
ELECTRICALCHARACTERISTICS (refer to the test circuit T
Control Range79dB
Step Resolution0.511.5dB
Attenuation set errorAv = 0 to -20dB-1.501.5dB
Av = -20 to -79dB-302dB
DC StepsAdjacent att. steps-303mV
Output Mute Condition70100dB
Input Impedance22.53037.5KΩ
Zero CrossingThresholdD7 = 0
Output Noise (OFF)Output Mute, Flat
B
= 20Hz to 20KHz
W
Output Noise (Movie) Standard
Surround Sound
Output Noise (Music) Standard
Surround Sound
Output Noise (Simulated)
Standard Surround Sound
Output Noise (SRS)
Mode = Movie ,
B
= 20Hz to 20KHz
W
Mode = Music ,
B
= 20Hz to 20KHz,
W
Mode = Simulated,
B
= 20Hz to 20KHz
W
BW= 20Hz to 20KHz50µVrms
V
S
+ 20
2
4
5
30µVrms
30
30µVrms
Surround Sound
= 1Vrms0.010.1%
in
Channel Separation7090dB
Clipping Leveld = 0.3%22.5Vrms
Output Resistance103050Ω
DC Voltage Level3.8V
Input Low Voltage1V
Input High Voltage3V
Input Current-5+5µA
Output Voltage SDA
IO= 1.6mA0.4V
Acknowledge
mV
Vrms
µ
Vrms
µ
µVrms
6/21
TDA7464
I2C BUSINTERFACE
Data transmission from microprocessor to the
TDA7464 and viceversa takes place through the
2 wires I
2
C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage mustbe connected).
Data Validity
As shown in fig. 3, the data on theSDA line must
be stable during the high period of theclock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start andStop Conditions
As shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOWto HIGH transition of the SDA linewhile SCL is HIGH.
Byte Format
Every byte transferredon the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
2
Figure 3: Data Validity on theI
CBUS
knowledgebit. The MSB is transferredfirst.
Acknowledge
The master (µP) puts a resistiveHIGHlevel on the
SDA line during the acknowledge clock pulse(see
fig. 5). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line
duringthisclock pulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the mastertransmitter can generate the STOP information in order to abort the
transfer.
Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio-
processor,the µP canuse a simplertransmission:
simply it waits one clock without checking the
slaveacknowledging,and sendsthe new data.
This approach of course is less protected from
misworking.
Figure 4: TimingDiagram of I
2
Figure 5: Acknowledgeon the I
CBUS
2
CBUS
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