SGS Thomson Microelectronics TDA7448 Datasheet

6 CHANNEL VOLUME CONTROLLER

■ 6 CHANNEL INPUTS

■ 6 CHANNEL OUTPUTS

■ VOLUME ATTENUATION RANGE OF

0 TO -79dB

■ VOLUME CONTROL IN 1.0dB STEPS

■ 6 CHANNEL INDEPENDENT CONTROL

■ ALL FUNCTION ARE PROGRAMMABLE VIA

SERIAL BUS

DESCRIPTIO

The TDA7448 is a 6 channel volume controller for
quality audio applications in Multi-Channels Audio
Systems

Thanks to the used BIPOLAR/CMOS Technology,

TDA7448

PRODUCT PREVIEW

SO20

ORDERING NUMBER: TDA7448

Low Distortion, Low Noise and DC stepping are ob­tained.

BLOCK DIAGRAM

2

IN1 OUT1

50K

19

IN2

50K

3

IN3

50K

18

IN4

50K

4

IN5

50K

17

IN6

50K

11

GND

CREF

20

VOLUME

VOLUME

VOLUME

VOLUME

VOLUME

VOLUME

SUPPLY

2

I

C BUS

DECODER

1

V

S

7

14

6

15

5

16

10

9

12

D02AU1396

OUT2

OUT3

OUT4

OUT5

OUT6

SCL
SDA
ADDR

December 2002

This is preliminary information on a new product now in development. Details are subject to change without notice.

1/13

TDA7448

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

Operating Supply Voltage 10.5 V

S

Operating Ambient Temperature -10 to 85 °C
Storage Temperature Range -55 to 150 °C

T

T

V

amb

stg

PIN CONNECTION

V
IN1
IN3
IN5

OUT5
OUT3
OUT1

N.C.
SDA

S

1
2
3
4
5
6
7
8
9 ADDR

SCL 10 GND

D02AU1397

20
19
18
17
16
15
14
13
12
11

CREF
IN2
IN4
IN6
OUT6
OUT4
OUT2
N.C.

THERMAL DATA

Symbol Parameter Value Unit

R

th j-pin

thermal Resistance junction-pins 150 °C/W

QUICK REFERENCE DATA

Symbol Parameter Min. Typ. Max. Unit

V

S

V

CL

THD Total Harmonic Distortion V = 1Vrms f =1KHz 0.01 0.1 %

S/N Signal to Noise Ratio Vout = 1Vrms 100 dB

S

C

Supply Voltage 4.75 9 10 V
Max Input Signal Handling 2 Vrms

Channel Separation f = 1KHz 90 dB
Volume Control (1dB step) -79 0 dB
Mute Attenuation 90 dB

2/13

TDA7448

ELECTRICAL CHARACTERISTCS

(refer to the test circuit T

Symbol Parameter Test Condition Min. Typ. Max. Unit

SUPPLY

V

SVR Ripple Rejection 80 dB

Supply Voltage 4.75 9 10 V

S

I

Supply Current 7 mA

S

INPUT STAGE

R

V

S

Input Resistance 35 50 6 5 KΩ

IN

Clipping Level THD = 0.3% 2 2.5 Vrms

CL

Input Separation The selected input is grounded

IN

VOLUME CONTROL

C

RANGE

A

VMAX

A

STEP

E

E

V

A

mute

Control Range 79 dB
Max. Attenuation 79 dB
Step Resolution 0.5 1 1.5 dB
Attenuation Set Error AV = 0 to -24dB -1 0 1 dB

A

Tracking Error AV = 0 to -24dB -1 0 1 dB

T

DC Step adyacent attenuation steps -3 0 3 mV

DC

Mute Attenuation 90 db

AUDIO OUTPUTS

V

CLIP

R

V

Clipping Level THD = 0.3% 2 2.5 Vrms
Output Load Resistance 2 KΩ

L

DC Voltage Level 4.5 V

DC

GENERAL

E

S/N Signal to Noise Ratio All gains = 0dB; V

S

THD Distortion A

Output Noise BW = 20Hz to 20KHz

NO

Channel Separation left/Right 80 90 dB

C

BUS INPUT

V

V

I
V

Input Low Voltage 1V

Il

Input High Voltage 2.5 V

IH

Input Current VIN = 0.4V -5 5 µA

IN

Output Voltage SDA

O

Achnowledge

= 25°C, VS = 9V, RL = 10KΩ, RG = 600Ω, unless otherwise specified)

amb

90 dB

through a 2.2µ capacitor

A

= -24 to -79dB -2.0 0 2.0 dB

V

A

= -24 to -79dB -2 0 2 dB

V

10 15 µV

All gains = 0dB, Flat

= 1Vrms 100 dB

O

= 0; VI = 1Vrms 0.01 0.1 %

V

IO = 1.6mA 0.4 0.8 V

3/13

TDA7448

Figure 1. Tes t circuit

0.47µF
IN1

GND

CREF

2

IN2

19

IN3

3

IN4

18

IN5

4

IN6

17

11

20

IN1

0.47µF

IN2

0.47µF

IN3

0.47µF

IN4

0.47µF

IN5

0.47µF

IN6

10µF

50K

50K

50K

50K

50K

50K

VOLUME

VOLUME

VOLUME

VOLUME

VOLUME

VOLUME

SUPPLY

2

I

C BUS

DECODER

1

V

S

7

14

6

15

5

16

10

9

11

D02AU1406

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

SCL
SDA
ADDR

APPLICATION SUGGESTIONS

The volume control range is 0 to -79dB, by 1dB step
resolution.

The very high resolution allows the i mplementation of
systems free from any noise acoustical effect.

CREF

The suggested 10µF reference capacitor (CREF)
value can be reduced to 4.7

µ

F if the application re-

quires faster power ON.

Figure 2. THD vs. frequency

Figure 3. THD vs. R

LOAD

Figure 4. Channel separation vs. frequency

4/13

TDA7448

I2C BUS INTERFACE

Data transmission from microprocessor to the TDA7448 and vice versa takes place through the 2 wires I2C BUS in­terface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected).

Data Validity

As shown in fig. 1, the data on the SDA line must be stable during the high period of the clock. The HIGH and
LOW state of the data line can only change when the clock signal on the SCL line is LOW.

Start and Stop Conditions

As shown in fig. 2 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop
condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.

Byte Format

Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit.
The MSB is transferred first.

Acknowledge

The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 5). The
peripheral (aud io pr ocessor) that acknowl edges has to pull-down (LOW) th e SDA line duri ng this clock pulse.

The audio processor which has been addressed has to generate an acknowledge after the reception of each
byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master
transmitter can generate the STOP information in order to abort the transfer.

Transmission without Acknowledge

Avoiding to detect the acknowledge of the audio processor, the µP can use a simpler transmission: simply it
waits one clock without checking the slave acknowledging, and sends the new data.

This approach of course is less protected from misworking.

Figure 5. Dat a Va li di t y on t he I2CBUS

SDA

SCL

Figure 6. Timin g D i agram of I

2

SCL

SDA

START

Figure 7. Ackn owl e d ge on the I

SCL

STABLE, DATA

CBUS

2

CBUS

1

DATA LINE

VALID

CHANGE

DATA

ALLOWED

D99AU1032

23789

D99AU1031

STOP

2

I

CBUS

SDA

START

MSB

D99AU1033

ACKNOWLEDGMENT

FROM RECEIVER

5/13

TDA7448

SOFTWARE SPECIFICATION

Interface Protocol
The interface protocol comprises:

■ A start condition (S)

■ A chip address byte, containing the TDA7448 address

■ A subaddress bytes

■ A sequence of data (N byte + acknowledge)

■ A stop condition (P))

CHIP ADDRESS

SUBADDRESS DATA 1 to DATA n

MSB

S 1 0 0 0 1 0 0 0 ACK ACK DATA ACK P

D96AU420

LSB MSB LSB MSB LSB

XXB

X DATA

ACK = Acknowledge; S = Start; P = Stop; A = Address; B = Auto Increment

EXAMPLES
No Incremental Bus

The TDA7448 receives a start condition, the correct chip address, a subaddress with the B = 0 (no incremental
bus), N-data (all these data concern the subaddress selected), a stop condition.

CHIP ADDRESS

MSB

S10001000 ACK ACK DATA ACK P

D96AU421

LSB MSB LSB MSB LSB

SUBADDRESS DATA

XD3

XX0

D2 D1 D0

Incremental Bus

The TDA7448 receivea start conditions, the correct chip address, a subaddress with the B = 1 (incremental bus):
now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS from "XXX1000"
to "XXX1111" of DATA are ignored.The DATA 1 concern the subaddress sent, and the DATA 2 concern the
subaddress sent plus one in the loop etc, and at the end it receivers the stop condition.

CHIP ADDRESS

MSB

S 1 0 0 0 1 0 0 0 ACK ACK DATA ACK P

D96AU422

LSB MSB LSB MSB LSB

SUBADDRESS DATA 1 to DATA n

XX1

XD3

D2 D1 D0

DATA BYTES

Address= 88 (HEX) (10001000): ADDR open; 8A (HEX) (10001010): connect to supply
FUNCTION SELECTION: subaddress

MSB LSB

D7 D6 D5 D4 D3 D2 D1 D0

X X X B 0 0 0 0 SPEAKER ATTENUATION OUT 1
X X X B 0 0 0 1 SPEAKER ATTENUATION OUT 2
X X X B 0 0 1 0 SPEAKER ATTENUATION OUT 3
X X X B 0 0 1 1 SPEAKER ATTENUATION OUT 4
X X X B 0 1 0 0 SPEAKER ATTENUATION OUT 5
X X X B 0 1 0 1 SPEAKER ATTENUATION OUT 6
X X X B 0 1 1 0 NOT USED”
X X X B 0 1 1 1 NOT USED

B=1: INCREMENTAL BUS; ACTIVE
B=0: NO INCREMENTAL BUS
X= DON’T CARE

6/13

SUBADDRESS

TDA7448

In Incremental Bus Mode, the three “not used” functions must be addressed in any case. For example to refresh
“ Speaker Attenuation 3 = 0dB and Speaker Attenuation 6 = -40 dB”; the following bytes must be sent:

SUBADDRESS XXX10010
SPEAKER ATTENUATION OUT 1 XXXXXXXX
SPEAKER ATTENUATION OUT 2 XXXXXXXX
SPEAKER ATTENUATION OUT 3 00000000
SPEAKER ATTENUATION OUT 4 XXXXXXXX
SPEAKER ATTENUATION OUT 5 XXXXXXXX
SPEAKER ATTENUATION OUT 6 00101111

SPEAKER ATTENUATION SELECTION

MSB LSB

D7 D6 D5 D4 D3 D2 D1 D0

000 0dB
0 0 1 -1dB

SPEAKER ATTENUATION

0 1 0 -2dB
0 1 1 -3dB
1 0 0 -4dB
1 0 1 -5dB
1 1 0 -6dB
1 1 1 -7dB

0 0 0 0 0 -0dB
0 0 0 0 1 -8dB
0 0 0 1 0 -16dB
0 0 0 1 1 -24dB
0 0 1 0 0 -32dB
0 0 1 0 1 -40dB
0 0 1 1 0 -48dB
0 0 1 1 1 -56dB
01 -64dB
10 -72dB
11 MUTE

value = 0 to -79dB and MUTE

7/13

TDA7448

0

3

Figure 8. PIN:20

V

V

S

S

20K

CREF

20K

Figure 9. PINS: 5, 6, 7, 14, 15, 16

V

S

OUT1 to

OUT6

24

D96AU43

Figure 11. PINS: 10

20µA

SCL

D96AU424

Figure 12. PINS: 9

20µA

SDA

20µA

D02AU1398

Figure 10. PINS: 2, 3, 4, 17, 18, 19

V

S

IN

100K

V

REF

D96AU42

20µA

D96AU425

8/13

Figure 13. Test and Application Circuit

J1

IN1

TDA7448

J2

OUT1

IN1

IN2

IN3

IN4

IN5

IN6

GND

J3

1

2

3

4

5

6

7

C1 0.47µF

C3 0.47µF

C5 0.47µF

C7 0.47µF

C9 0.47µF

C11 0.47µF

C13 10µF 16V

+

C14

+

100µF 16V

IC1 TDA7448

2

IN1

19

IN2

3

IN3

18

IN4

4 5

IN5 OUT5

20

CREF

8

N.C.

13

N.C.

VS

1

C15

0.1µF

2

OUT1

OUT2

OUT3

OUT4

OUT6IN6

SCL

SDA

ADDR

GND

11

1

J6

GNDVS

7

14

6

15

1617

10

9

12

C2 22µF 16V

C4 22µF 16V

C6 22µF 16V

C8 22µF 16V

C10 22µF 16V

C12 22µF 16V

JP1

+

+

+

+

+

+

R1 10

R2
1K

R3
1K

J4

J5

I2C

OUT1

1

OUT2

2

OUT3

3

OUT4

4

OUT5

5

OUT6

6

GND

7

VS

1

DGND

2

SCL

3

4

SDA

9/13

TDA7448

Figure 14. Com p onent Lay ou t (65 x 72 m m )

Figure 15. PC Board (Component side)

10/13

Figure 16. PC Board (Solder side)

TDA7448

11/13

TDA7448

DIM.

MIN. TYP. MAX. MIN. TYP. MAX.

A 2.35 2 .65 0.093 0.104

A1 0.1 0.3 0.004 0.012

B 0.33 0 .51 0.013 0.020

C 0.23 0.32 0.009 0.013

D 12.6 13 0.496 0.512

E 7.4 7.6 0.291 0.299

e 1.27 0.050

H 10 10.65 0.394 0.419

h 0.25 0.75 0.010 0.030

L 0.4 1.27 0.016 0.050

K 0˚ (m in.)8˚ (max.)

mm inch

OUTLINE AND

MECHANICAL DATA

SO20

B

e

D

1120

110

L

h x 45˚

A

K

A1

C

H

E

SO20MEC

12/13

TDA7448

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or otherwise under any patent or patent r i ght s of STMi croelectr oni cs. Spec i fications mentioned i n this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics product s are not
authorized for use as cri tical comp onents in lif e support devi ces or systems without express written approva l of STMicroel ectronics.

The ST logo is a registered trademark of STMicroelectronics

© 2002 STMic roelectroni cs - All Rig hts Reserved

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13/13