SGS Thomson Microelectronics TDA7437 Datasheet
DIGITALLY CONTROLLED AUDIO PROCESSOR
INPUTMULTIPLEXER
- FOURSTEREO,ONEMONOINPUT,AND
ONEDIFFERENTIAL INPUT
- SELECTABLEINPUT GAIN FOR OPTIMAL
ADAPTATIONTO DIFFERENT SOURCES
FULLY PROGRAMMABLE LOUDNESS
FUNCTION
VOLUME CONTROL IN 1dB STEPS INCLUDING GAIN UP TO 16dB
ZERO CROSSINGMUTE, SOFT MUTE AND
DIRECT MUTE
BASS AND TREBLE CONTROL
FOURSPEAKERATTENUATORS
- FOURINDEPENDENT SPEAKERS
CONTROLIN 1dB STEPSFOR
BALANCEAND FADER FACILITIES
PAUSE DETECTOR PROGRAMMABLE
THRESHOLD
ALL FUNCTIONS PROGRAMMABLE VIA SE-
2
RIAL I
DESCRIPTION
The audioprocessor TDA7437 is an upgrade of
the TDA731X audioprocessorfamily.
CBUS
TDA7437
PQFP44 and TQFP44
ORDERING NUMBERS: TDA7437 (PQFP44)
TDA7437T (TQFP44)
Due to a highly linear signal processing, using
CMOS-switching techniques instead of standard
bipolar multipliers, very low distortion and very
low noise are obtained.Several new features like
softmute, and zero-crossing mute are implemented.
The soft Mute function can be activated in two
ways:
1 Via serial bus(Mute byte, bit D0)
2 Directly on pin 28 through an I/O line of the
microcontroller
Very low DC stepping is obtained by use of a
BICMOStechnology.
PIN CONNECTION
December 1999
TREB_R
IN_R
MUXOUT_R
LOUD_R
DIFFGND_R
DIFF_R
STEREO4_R
STEREO1_R
STEREO2_R
STEREO3_R
MONO
TREB-L
AGND
AVDD
DVDD
CREF
ADDR
SCL
SDA
44 43 42 41 3940 38 37 36 35 34
1
2
3
4
5
6
7
8
9
10
DIFF_L
STEREO4_L
STEREO1_L
171118 19 20 21 22
CSM
STEREO2_L
STEREO3_L
12 13 14 15 16
LOUD_L
DIFFGND_L
DGND
PAUSE
IN_L
MUXOUT_L
OUT_LF
33
32
31
30
29
28
27
26
25
24
23
D96AU435A
MID_LI
OUT_RF
OUT_LR
MID_RI
MID_RO
OUT_RR
SMEXT
BASS_RO
BASS_RI
BASS_LO
BASS_LI
MID_LO
1/23
TDA7437
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
,DV
AV
DD
T
amb
T
stg
THERMAL DATA
Symbol Parameter Value Unit
R
th j-amb
QUICK REFERENCE DATA
Symbol Parameter Min. Typ. Max. Unit
,DVDDSupply Voltage (AVDDand DVDDmust be at the same potential) 6 9 10.2 V
AV
DD
V
CL
THD Total Harmonic Distortion V = 1Vrms f= 1KHz 0.01 0.8 %
S/N Signal to Noise Ratio 111 dB
S
C
Operating Supply Voltage 10.5 V
DD
Operating Ambient Temperature -40 to 85 °C
Storage Temperature Range -55 to 150 °C
Thermal ResistanceJunction-pins Max. 150 °C/W
Max. input signal handling 2.1 2.6 Vrms
Channel Separation f = 1KHz 95 dB
Input Gain 1dB step 0 15 dB
Volume Control 1dB step -63 16 dB
Treble Control 2dB step -14 +14 dB
Bass Control 2dB step -14 +14 dB
Middle Control 2dB step -14 +14 dB
Fader and BalanceControl 1dB step -79 0 dB
Loudness Control 1dB step 0 20 dB
Mute Attenuation 100 dB
2/23
BLOCK DIAGRAM
TDA7437
5.6K
2.7K
100nF
18nF 100nF
5.6nF 22nF
BIN(L)BOUT(L)MIN(L)MOUT(L)
FLout
ATT
SPKR
RLout
ATT
SPKR
S-MUTE
ADDR
SDA
SCL
C BUS DECODER + LATCHES
2
I
DIGGND
RRout
ATT
SPKR
S-MUTE
FRout
ATT
SPKR
CONTROL
SOFT, ZERO
MUTE
D95AU249B
CSM
PAUSE
SMEXT
BIN(R)
100nF
BOUT(R)MIN(R)
18nF 100nF
22nF
(R)
MOUT
47nF47nF
5.6K
2.7K
TREBLE(R)
2.2µF 47nF
TREBLE(L)
LOUD(L)
IN_L
MUXOUT_L
STEREOIN1L
4 x 470nF
STEREOIN3L
STEREOIN2L
TREBLE BASSMIDDLE
VOLUME
+ LOUDN
INGAIN
DIFFINL
STEREOIN4L
2 x 4.7µF
MULTIPLEXER
MONO
DIFFINLGND
5 x 470nF
STEREOIN1R
STEREOIN2R
TREBLE BASSMIDDLE
VOLUME
+ LOUDN
INGAIN
STEREOIN3R
STEREOIN4R
DIFFINR
DIFFINRGND
2 x 4.7µF
SUPPLY
AVDD
DVDD
47nF 5.6nF
IN_R
CREF LOUD(R)
22µF
ANGND
2.2µF
MUXOUT_R
3/23
TDA7437
ELECTRICALCHARACTERISTICS (AVDD,DVDD= 9V; RL= 10KΩ;Rg=50Ω;T
amb
=25°C;
all gains= 0dB;f = 1KHz. Refer to the test circuit, unless otherwise specified.)
Symbol Parameter Test Condition Min. Typ. Max. Unit
INPUT SELECTOR (MONO AND STEREO INPUTS)
R
V
CL
S
I
R
L
G
I MIN
G
I MAX
G
step
E
a
V
DC
DIFFERENTIAL INPUT (Pin 5, 6, 13, 14)
R
CMRR Common Mode Rejection Ratio V
d Distortion V
IN
e
DIFF
G
VOLUME CONTROL
R
G
MAX
A
MAX
A
STEPC
E
A
E
t
V
DC
LOUDNESS CONTROL (Pin 4, 12)
R
A
MAX
A
step
ZERO CROSSING MUTE
V
TH
A
MUTE
V
DC
Input Resistance pin 7 to 11and 15 to 18 70 100 130 KΩ
I
Clipping Level d ≤ 0.3% 2.1 2.6 V
Input Separation 80 95 dB
Output Load Resistance 2 KΩ
Minimum Input Gain -0.75 0 +0.75 dB
Maximum Input Gain 14 15 16 dB
Step Resolution 0.5 1.0 1.5 dB
Set Error -1.0 0 1.0 dB
DC Steps Adiacent GainSteps 0.5 10 mV
to G
G
IMIN
I
Input Resistance Input selector BIT D4 = 0 (0dB) 10 15 20 KΩ
IMAX
3mV
Input selector BIT D4 = 1(-6dB) 14 20 26 KΩ
CM
RMS
I
=1V
=1V
; f =1KHz 45 70 dB
RMS
0.01 0.08 %
Input Noise 20Hz to 20KHz; Flat; D6 = 0 5 µV
Differential Gain D4 = 0 -1 0 1 dB
D4 = 1 -7 -6 -5 dB
Input Resistance Pin 2 and 20 31 44 57 KΩ
I
Maximum Gain 15 16 17 dB
Maximum Attenuation 61 63.75 66.5 dB
Step Resolution Coarse Atten. 0.5 1.0 1.5 dB
Attenuation Set Error G = 16 to -20dB -1.0 0 1.0 dB
G = -20 to -63dB -2.75 2.75 dB
Tracking Error 2dB
DC Steps Adjacent GainSteps -5 +5 mV
Adjacent Attenuation Steps -3 +3 mV
From 0dB to A
Internal Resistor Loud = On 35 50 65 KΩ
I
MAX
0.5 5 mV
Maximum Attenuation 19 20 21 dB
Step Resolution 0.5 1 1.5 dB
Zero Crossing Threshold
WIN = 11 30 mV
(note 1)
WIN = 10 60 mV
WIN = 01 110 mV
WIN = 00 220 mV
Mute Attenuation 80 100 dB
DC Step 0dB to Mute 0.1 3 mV
RMS
4/23
TDA7437
ELECTRICALCHARACTERISTICS (continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit
SOFT MUTE
A
MUTE
T
DON
T
DOFF
R
INT
V
SMH
V
SML
BASS CONTROL
C
range
A
step
R
g
MIDDLE CONTROL
C
range
A
step
R
g
TREBLE CONTROL
C
RANGE
A
step
SPEAKER ATTENUATORS
C
RANGE
A
step
A
MUTE
E
A
V
DC
AUDIO OUTPUT
V
clip
R
L
R
O
V
DC
Mute Attenuation 50 65 dB
ON Delay Time C
OFF Current V
CSM
=22nF;0 to-20dB; I =I
CSM
=22nF;0 to-20dB; I =I
C
V
CSM
CSM
=0V;I= I
=0V;I = I
MAX
MIN
MAX
0.8 1.5 2.0 ms
MIN
25 45 60 ms
20 40 60 µA
2 µA
Pullup Resistor (pin 28) (note 2) 100 KΩ
(pin 28) Level High 3.5 V
(pin 28) Level Low Soft Mute Active 1 V
Control Range ±11.5 ±14 ±16 dB
Step Resolution 1 2 3 dB
Internal Feedback Resistance 31 44 57 KΩ
Control Range ±11.5 ±14 ±16 dB
Step Resolution 1 2 3 dB
Internal Feedback Resistance 17.5 25 32.5 KΩ
Control Range ±13 ±14 ±15 dB
Step Resolution 1 2 3 dB
Control Range 79 dB
Step Resolution AV= 0to -40dB 0.5 1 1.5 dB
Output Mute Attenuation Data Word = 1111XXXX 80 100 dB
Attenuation Set Error AV= 0to -40dB 1.5 dB
DC Steps Adjacent Attenuation Steps 0.1 3 mV
Clipping Level d = 0.3% 2.1 2.6 Vrms
Output Load Resistance 2 KΩ
Output Impedance 50 90 140 Ω
DC Voltage Level 3.5 3.8 4.1 V
5/23
TDA7437
ELECTRICALCHARACTERISTICS (continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit
PAUSE DETECTOR
V
TH
I
DELAY
V
THP
GENERAL
V
CC
I
CC
PSRR Power SupplyRejection Ratio f = 1KHz 70 90 dB
e
NO
E
t
S/N Signal to Noise Ratio All Gains = 0dB; V
S
C
d Distortion V
Pause Threshold WIN = 11 30 mV
WIN = 10 60 mV
WIN = 01 110 mV
WIN = 00 220 mV
Pull-Up Current 15 25 35 µA
Pause Threshold 3.0 V
Supply Voltage 6 9 10.2 V
Supply Current 7 10 13 mA
Output Noise OutputMuted(B= 20to20kHzflat) 4 µV
All Gains0dB
615µV
(B=200to20kHzflat)
Total Tracking Error AV= 0to -20dB 0 1 dB
= -20to -60dB 0 2 dB
A
V
= 2.1V
O
rms
111 dB
Channel Separation L- R 80 95 dB
=1V all gain = 0dB 0.01 0.08 %
IN
BUS INPUTS
V
IL
V
lN
I
lN
V
O
Note 1: WIN represents the MUTE programming bit pair D6,D5for the zero crossing window threshold
Note 2: Internallpullup resistor toVs/2; ”LOW” = softmuteactive
Note: The ANGND and DIGGNDlayout wires must be kept separated. A 50Ω resistor is recommended to be put as far as possible
from the device.
Input Low Voltage 1V
Input High Voltage 3 V
Input Current VIN = 0.4V -5 5 µA
Output Voltage SDA
IO= 1.6mA 0.1 0.4 V
Acknowledge
The CLD - andCDR- can be shortcircuitedin applicationsproviding3 wiresCD signal
L+
L-∼R-
CD TDA7437
=
R+
L+
L-
R-
R+
D00AU1125
CLD - = DIFFINLGND
CDR - = DIFFINRGND
6/23
TDA7437
2
C BUS INTERFACE
I
Data transmission from microprocessor to the
TDA7437 and viceversa takes place thru the 2
wires I
2
C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be externallyconnected).
Data Validity
As shown in fig. 3, thedata on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop Conditions
As shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
A STOP conditions must be sent before each
START condition.
Byte Format
Every byte transferred to the SDA line must conFigure 3: Data Validity on the I
2
CBUS
tain 8 bits. Each byte must be followed by an acknowledgebit. The MSB is transferredfirst.
Acknowledge
The master(µP)putsa resistiveHIGHlevelon the
SDA line during the acknowledgeclock pulse (see
fig. 5). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line
during the acknowledge clock pulse, so that the
SDAlineisstableLOWduringthis clockpulse.
The audioprocessor which has been addressed
hasto generateanacknowledgeafterthereception
ofeachbyte, otherwisethe SDAlineremainsatthe
HIGHlevelduringthe ninthclock pulsetime.In this
case the master transmitter can generate the
STOPinformation in orderto abortthetransfer.
Transmissionwithout Acknowledge
Avoiding to detect the acknowledge of the audioprocessor, the µP can use a simplier transmission: simply it waits one clock without checking
the slave acknowledging, and sends the new
data.
This approach of course is less protected from
misworkingand decreasesthe noise immunity.
Figure 4: Timing Diagram of I2CBUS
2
Figure 5: Acknowledge on the I
CBUS
7/23
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