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TDA 3602

SGS-THOMSON Microelectronics TDA 3602 Service Manual

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INTEGRATED CIRCUITS
DATA SH EET
TDA3602
Multiple output voltage regulator
Product specification File under Integrated Circuits, IC01
July 1994
Multiple output voltage regulator TDA3602
FEATURES
• Two VP state controlled regulators (REG1 and REG2)
• Regulator 3 operates during load dump or thermal
shutdown
• Multi-function control pin
• A back-up circuit for Regulator 3 via a single capacitor
• Supply voltage of −6 V to 50 V (a voltage of −3 V on V
does not discharge capacitor Cbu)
• Low reverse current Regulator 3
• Low quiescent current in coma mode
• HOLD output
• RESET output (LOW at load dump)
• High ripple rejection.
PROTECTIONS
• Foldback current limit protection (Regulators 1 and 2)
• Load dump protection
• Thermal protection
• DC short-circuit safe to ground and V
of all regulator
P
outputs
• Reverse polarity safe of pin 1 (VP). No high currents are flowing which can damage the IC
• Capable of handling high energy on the regulator outputs.
GENERAL DESCRIPTION
The TDA3602 is a multiple output voltage regulator, intended for use in car radios with or without a microprocessor. It contains two fixed voltage regulators with foldback current protection (Regulators 1 and 2), and one fixed voltage regulator that also operates during load dump and thermal shutdown. This regulator can be used to supply a microprocessor.
P
A back-up circuit supplies Regulator 3 during a short period after the power is cut off (negative field decay or engine start procedure). A state control pin (pin 4) controls the device, which can be switched through four stages using the information at this pin. The switching levels at this pin contain hysteresis.
RESET and HOLD outputs can be used to interface with a microprocessor. The RESET signal can be used to call up or initialize a microprocessor (power-on reset). The HOLD signal can be used to control the power stages (mute signal in a low end application), or to generate a HOLD interrupt (microprocessor application).
An internal Zener diode on the back-up pin allows this pin to withstand a load dump when supplied by the pin using a 100 Ω series resistor.
The supply pin can withstand load dump pulses and negative supply voltages.
July 1994 2
Multiple output voltage regulator TDA3602
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supply
V
P
I
P
T
vj
Voltage regulators
V
R1
V
R2
V
R3
positive supply voltage
operating 9.2 14.4 18 V Regulator 3 on 6.0 14.4 18 V jump start −−30 V load dump; Regulator 3 on −−50 V operating note 1 6.5 − 30 V
load dump; Regulator 3 on note 1 −−50 V total quiescent current coma mode − 290 −µA virtual junction temperature −−150 °C
output voltage Regulator 1 0.5 mA ≤ IR1≤ 250 mA 8.2 8.5 8.8 V output voltage Regulator 2 0.5 mA ≤ IR2≤ 140 mA 4.8 5.0 5.2 V output voltage Regulator 3 0.5 mA ≤ IR3≤ 50 mA 4.8 5 5.2 V
Note
1. Vbu (pin 8) supplied by VP2 with a 100 Ω series resistor and I
ORDERING INFORMATION
EXTENDED TYPE
NUMBER
TDA3602
(1)
PINS PIN POSITION MATERIAL CODE
9 SIL plastic SOT110
Note
1. SOT110-1; 1996 August 21.
REG3
PACKAGE
< 10 mA.
July 1994 3
Multiple output voltage regulator TDA3602
handbook, full pagewidth
2
TDA3602
REG1
V 8.5 V
REGULATOR 1
&
REG2
V 5 V
9
REGULATOR 2
Q
REG3
V 5 V
7
REGULATOR 3
RS
hold
5
&
CONTROL
HOLD CIRCUIT
reset
3
MCD346 - 1
6
ground
Fig.1 Block diagram.
P
V
1
P
V
SCHMITT 
TRIGGER
POLARITY
bu
LOADDUMP /
PROTECTION
V REVERSE
July 1994 4
bu
V
SCHMITT 
TRIGGER
8
bu
V
(back up)
5 V switched
bu
V
Zener
(21 V)
> 2 V
sc
V
R1,R2 on
STATE
4
V
L / H current
reset
CIRCUIT
CONTROL
sc
(state control)
Multiple output voltage regulator TDA3602
PINNING
SYMBOL PIN DESCRIPTION
V
P
1 positive supply voltage
REG1 2 Regulator 1 output RESET 3 reset output V
sc
4 state control input
HOLD 5 hold output GND 6 ground REG3 7 Regulator 3 output V
bu
8 back-up
REG2 9 Regulator 2 output
handbook, halfpage
V
1
P
2
REG1
RESET
V
HOLD
GND
REG3
V
bu
REG2
3 4
sc
TDA3602
5 6 7 8 9
MCD345
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
This multiple output voltage regulator contains three fixed voltage regulators, numbered 1, 2 and 3. Two of these can be switched between the on and off states using the state control pin (pin 4). The third (Regulator 3), which is continuously in, can be switched by the state control pin between a low and a high current mode.
In addition to Regulators 1 and 2, the device is supplied by an internal switch that is open when the supply voltage falls below the back-up voltage (negative field decay or engine start procedure), or during a load dump. (During this load dump, Regulators 1 and 2 are switched off and RESET is switched LOW). This switched supply voltage (the so-called back-up voltage (Vbu), is available at pin 8. An electrolytic capacitor can be connected to this pin, and the charge on this capacitor can be used to supply the device for a short period after the supply voltage is removed.
Three pins are provided for interfacing with a microprocessor:
• state control pin
• hold output pin
• reset output pin.
When the supply voltage (VP) is connected to the device, Vbu will rise. When Vbu reaches 7.9 V, the device is in the power-on mode. The RESET output goes HIGH and Regulator 3 is switched on. In a microprocessor application, the RESET output can be used to call up the CPU and to initialize the program.
What follows depends on the voltage at the state control pin (V
). In most applications, when the supply voltage is
sc
connected, Vsc will rise slowly (e.g. by charging a capacitor).The device will leave the power-on mode and enter the reset mode when Vsc rises above 2.2 V. In both the power-on and reset modes, Regulator 3 will be in the high current mode, Regulators 1 and 2 will be switched off and the RESET output will be HIGH.
The device will enter the wake mode when Vsc reaches 2.8 V. The RESET pin will go LOW and the CPU must be switched to the sleep mode. Regulator 3 is still in the high current mode.
As Vsc continues rising and the voltage reaches 3.6 V, the stabilizer will be switched into the sleep mode. It will be in a coma mode when Vsc is greater than 3.8 V. In this mode, only the relevant circuits remain operating; this is to keep the power consumption as low as possible i.e. typically 290 µA.
If the device is switched on with Vsc already higher than 3.8 V, the device will be switched directly from the power-on mode into the coma mode.
When Vsc is lowered gradually from 3.6 V (or higher) to 2 V, the device will go from sleep to reset again.
Vsc must be lower than 1.1 V to bring the device into the on mode; note that this is not the same as the power-on mode. In this condition, Regulator 3 is in the high current mode, both Regulators 1 and 2 are switched on and the HOLD output will be HIGH (depending on the state of V and the in-regulation condition of Regulators 1 and 2).
P
July 1994 5
Multiple output voltage regulator TDA3602
When the device is in the on mode, it will switch back to the reset mode when Vsc rises to 2 V, or when the supply voltage drops below 7.3 V.
When V
drops below 3 V, the device will return to the power off mode, regardless of the condition the device was in.
REG3
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
P
supply voltage
operating − 18 V jump start t ≤ 10 min − 30 V load dump t ≤ 50 ms; t Regulator 3 on V
> −3 V; note 1 − 30 V
P
load dump t ≤50 ms; t
≥ 2.5 ms − 50 V
r
≥ 2.5 ms; note 1 − 50 V
r
reverse battery voltage −6 − V
T
stg
T
vj
V
pr
P
tot
storage temperature non-operating −55 +150 °C virtual junction temperature operating −40 +150 °C reverse polarity non-operating − 6V total power dissipation − 15 W
Note
1. V
(pin 8) supplied by VP2 with a 100 Ω series resistor and I
bu
REG3
< 10 mA.
THERMAL RESISTANCE
SYMBOL PARAMETER THERMAL RESISTANCE
R R
th j-a th j-c
from junction to ambient in free air 50 K/W from junction to case (see Fig.6) 12 K/W
CHARACTERISTICS
= 14.4 V; T
V
P
= 25 °C; measured in Fig.6; unless otherwise specified.
amb
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply
V
P
supply voltage
operating 9.2 14.4 18 V Regulator 3 on note 1 6.0 14.4 18 V jump start t ≤ 10 min −− 30 V load dump t ≤ 50 ms; t
I
P
quiescent current Vsc > 4V; note 2
= 12.4 V − 280 360 µA
V
P
= 14.4 V − 290 −µA
V
P
≥ 2.5 ms −− 50 V
r
July 1994 6
Multiple output voltage regulator TDA3602
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Schmitt triggers
VP2SCHMITT TRIGGER (FOR HOLD AND REGULATORS 1 AND 2) V
thr
V
thf
V
hy
REGULATOR 1SCHMITT TRIGGER (FOR HOLD) V
thr
V
thf
V
hy
REGULATOR 2SCHMITT TRIGGER (FOR HOLD) V
thr
V
thf
V
hy
VBU SCHMITT TRIGGER (REGULATOR 3) V
thr
V
thf
V
hy
State control pin
V
th
V
thr1
V
thf1
V
hy1
V
thr2
V
thf2
V
hy2
V
thr3
V
thf3
V
hy3
I
scl
rising voltage threshold 7.3 7.6 8.0 V falling voltage threshold 6.8 7.1 7.5 V hysteresis − 0.5 − V
rising voltage threshold − VR1 − 0.2 − V falling voltage threshold − VR1 − 0.3 − V hysteresis − 0.1 − V
rising voltage threshold − VR2 − 0.2 − V falling voltage threshold − VR2 − 0.3 − V hysteresis − 0.1 − V
rising voltage threshold V falling voltage threshold V
bu
REG3
7.3 7.9 8.4 V
2.5 3 3.5 V
hysteresis − 4.9 − V
voltage threshold between note 2 − V
+ 0.2 − V
thr1
sleep and coma voltage threshold wake to 3.35 3.6 3.85 V sleep voltage threshold sleep to 2.5 2.7 2.9 V wake hysteresis wake/sleep 0.85 0.92 1.0 V voltage threshold reset to 2.6 2.8 3.0 V wake
] voltage threshold wake to 1.75 1.9 2.05 V
reset hysteresis reset/wake 0.85 0.92 1.0 V voltage threshold on to reset 1.85 2.0 2.15 V voltage threshold reset to on 1.0 1.1 1.2 V hysteresis on/reset 0.85 0.92 1.0 V input current
≤ 0.8 V −− −1µA
V
sc
≥ 4 V −− 1µA
V
sc
July 1994 7
Multiple output voltage regulator TDA3602
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Reset output
V
OL
V
OH
I
OL
I
OH
Hold output
V
OL
V
OH
I
OL
I
OH
Regulator 1 (I
V
REG1
V
REG1
∆V
REG1
∆V
REGL1
SVRR1 supply voltage ripple rejection f = 200 Hz;2 V (p-p) 60 −−dB V
REGd1
I
REGm1
I
REGsc1
Regulator 2 (I
V
REG2
V
REG2
∆V
REG2
∆V
REGL2
SVRR2 supply voltage ripple rejection f = 200 Hz; 2 V (p-p) 60 −−dB V
REGd2
I
REGm2
I
REGsc2
LOW level output voltage IOL = 0 0 0.2 0.8 V HIGH level output voltage 2.0 5.0 5.25 V LOW level output current VOL ≤ 0.8 V 0.3 0.8 − mA HIGH level output current VOH > 3 V −0.3 −2.0 − mA
LOW level output voltage IOL = 0 0 0.2 0.8 V HIGH level output voltage 2.0 5.0 5.25 V LOW level output current VOL ≤ 0.8 V; note 3 0.3 1.0 − mA HIGH level output current VOH > 3 V −1.5 −9.0 − mA
= 5 mA unless otherwise specified)
REG1
output voltage off Vsc > 2.1 V − 1 400 mV output voltage
0.5 V ≤ I 10 V ≤ V
≤ 250 mA 8.2 8.5 8.8 V
REG1
≤ 18 V 8.2 8.5 8.8 V
P
line regulation 10 V ≤ VP ≤ 18 V −− 50 mV load regulation 0.5 mA ≤ I
drop-out voltage I current limit V
= 250 mA −− 0.4 V
REG1
> 7 V; note 4 0.4 − 1.2 A
REG1
≤ 250 mA −− 50 mV
REG1
short-circuit current RL ≤ 0.5 Ω; note 4 − 250 − mA
= 10 mA unless otherwise specified)
REG2
output voltage off Vsc >2.1 V − 1 400 mV output voltage
0.5 V ≤ I 8 V ≤ V
≤ 140 mA 4.8 5.0 5.2 V
REG2
≤ 18 V 4.8 5.0 5.2 V
P
line regulation 8 V ≤ VP ≤ 18 V −− 50 mV load regulation 0.5 mA ≤ I
drop-out voltage I current limit V
= 140 mA − 1.2 − V
REG2
> 4.5 V; note 4 200 − 600 mA
REG2
≤ 140 mA −− 50 mV
REG2
short-circuit current RL ≤ 0.5 Ω; note 4 − 130 − mA
July 1994 8
Multiple output voltage regulator TDA3602
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Regulator 3 (I
V
∆V
REG3
REGL3
output voltage
output voltage sleep mode; I
= 5 mA unless otherwise specified)
REG3
0.5 mA ≤ I 7 V ≤ V 18 ≤ V
≤ 50 mA 4.8 5.0 5.2 V
REG3
≤ 18 V 4.8 5.0 5.2 V
P
≤ 50 V 4.8 5.0 5.2 V
P
≤ 10 mA; 4.5 5.0 5.5 V
REG3
note 2
I
LO1
∆V
REG3
∆V
REGL3
leakage output current VP = 0; Vbu = 6 V; V line regulation 7 V ≤ VP ≤ 18 V −− 50 mV load regulation 0.5 mA ≤ I
≤ 50 mA −− 50 mV
REG3
= 6 V −− −1µA
REG3
SVRR3 supply voltage ripple rejection f = 200 Hz; 2 V (p-p) 60 −−dB V
REGd3
I
REGm3
drop-out voltage I current limit V
= 50 mA; note 5 −− 0.4 V
REG3
> 4.5 V; note 6 140 − 500 mA
REG3
Switch
V I
swm
swd
drop-out voltage Isw = 50 mA −− 0.45 V maximum current 140 −−mA
Notes
1. Minimum operating voltage only if VP has exceeded 8 V.
2. In the sleep mode, Regulators 1 and 2 are off. In the coma mode, the state control circuit is also switched off, to make the quiescent current as low as possible.
3. Hold circuit can sink this current in the RESET state and the ON state.
4. The foldback current protection limits the dissipated power at short-circuit (see Fig.5).
5. The drop-out voltage of Regulator 3 is measured between Vbu and V
6. At current limit, I
is held constant (behaviour in accordance with the broken line in Fig.5).
REGm
(pins 8 and 7).
REG3
July 1994 9
Multiple output voltage regulator TDA3602
Table 1 State control pin.
VP1 SCHMITT TRIGGER IS TRUE
STATE REG3 (5 V) REG1 + REG2 RESET REMARKS
Coma LOW current off 0 stabilizer consumes low quiescent current;
state control circuit is switched off to lower the
quiescent current Sleep LOW current off 0 state control circuit on Wake HIGH current off 0 CPU in sleep mode Reset HIGH current off 1 CPU called up On HIGH current on 1 normal operation Power on HIGH current off 1 V
Power off off off 0 V
rises from 0 to 8.5 V or higher
P1
(first start-up)
falls from VP to less than 3 V
P2
(V
= 2.5 V)
REG3
handbook, full pagewidth
REG3
REG3
bu
> 7.9 VV
bu
REG3
< 3 VV
< 3 VV
< 3 VV
REG3
COMA
> 3.8 VV
sc
SLEEP
> 3.6 VV
> 3.8 VV
sc
POWER ONPOWER OFF
< 3 VV
< 3 VV
sc
WAKE
> 2.8 VV
sc
> 2.2 VV
sc
RESET
> 2.0 VV
sc
or
< 7.1 VV
P
ON
< 3.8 VV
sc
< 2.7 VV
sc
< 1.9 VV
sc
< 1.1 VV
sc
and
> 7.6 VV
P
MCD347 - 1
Vbu = back-up voltage. Vsc = state control voltage. V
= Regulator 3 output voltage.
REG3
Fig.3 State diagram.
July 1994 10
Multiple output voltage regulator TDA3602
handbook, full pagewidth
REGULATOR 3
state control
REGULATORS
1 and 2
V
V
reset
hold
P
bu
MCD348
Fig.4 Timing diagram.
Table 2 Logic table HOLD function.
INPUTS FOR HOLD (note 1) OUTPUT
V
BU
VP SCHMITT
TRIGGER
ON STATE REG1 REG2 HOLD
10 X000 01 X000 1 1 0000 11 10X0 11 1X00 1 1 1111
Note
1. 0 = off; 1 = on; X = don't care.
July 1994 11
Multiple output voltage regulator TDA3602
QUALITY SPECIFICATION
Quality in accordance with UZW-BO/FQ-0601.
TEST INFORMATION
The outputs of the regulators are measured by means of a
handbook, halfpage
V
Rx
V
0
(Regulators
1 and 2)
selector switch (one by one). In addition, switch SW2 is only closed when V
is greater than VP; then the internal
bu
switch of the TDA3602 is opened. Vbu (pin 8) can only withstand a 50 V load dump pulse when switch SW2 is kept open or when switch SW2 is replaced by a 100 Ω resistor.
Fig.5 Foldback current protection.
handbook, full pagewidth
V
P
V
bu
V
on / off
sc
SW1
SW2
I
sc
C1 220 nF
C2  220 nF
state control
V
I
REGm
V
P
bu
1
8
4
MCD354 - 1
TDA3602
6
ground
Regulator 1
2
Regulator 2
9
Regulator 3
7
hold
5
reset
3
8.5 V
C3 10 µF
5 V
C4 10 µF
5 V continuous
C5 10µF
MCD351 - 1
R
V
L
2 W
Fig.6 Test circuit.
July 1994 12
Multiple output voltage regulator TDA3602
APPLICATION INFORMATION Noise Table 3 Noise at regulator outputs dependent on
capacitive load (C
REGULA TOR
(NOTE 1)
REG I
L
).
L
C
L
10 µF47µF 220 µF
1 150 mA 800 µV 220 µV 160 µV 2 100 mA 500 µV115 µV 3 50 mA 350 µV 190 µV
Note
1. Regulators loaded with 100mA; noise in µV RMS (B = 10 Hz to 1 MHz).
The available noise at the output of the regulators depends on the bandwidth of the regulators, which can be adjusted by means of the load capacitors. The noise figures are given in Table 3.
Although stability is guarenteed when C
is higher than
L
10 µF (over temperature range) with tan (φ) = 1 in the frequency range 1 kHz to 20 kHz, it is recommended to use a 47 µF load capacitor for Regulators 1 and 2. When a microprocessor is supplied by Regulator 3 much noise can be produced by this microprocessor. This noise is not influenced by increasing the load capacitor of Regulator 3.
The noise on the supply line depends on the supply capacitor. When a high frequency capacitor of 220 nF with an electrolytic capacitor of 100 µF in parallel is placed directly over pin 1 (VP) and pin 6 (ground) the noise is minimized.
The stabilizer is in 'power on' after the supply is reconnected (Vbu> 7.9 V) and 0.1 < Vsc < 2.2 V.
STABILIZER WITHOUT MICROPROCESSOR 2 Fig.8 illustrates the application circuit for a low end radio
set with push switches when no microprocessor is used. The stabilizer can be switched to the on mode by pressing switch SW1. In this mode, Regulators 1 and 2 are switched on, so transistor T1 takes over from switch SW1. The stabilizer can only be switched off by connecting the base of T1 to ground (SW1 not pressed). This can be achieved by pressing switch SW2.
The hold signal is only HIGH when the device is in the on mode and both VP and the regulators are available, so that this signal can be used to control the power stages (mute). During a fault condition, this signal turns LOW immediately.
When the stabilizer is connected to the supply for the first time, the initial state will be the power-on stage, so Regulators 1 and 2 are not switched on.
TABILIZER USED WITH MICROPROCESSOR
S For a good understanding of the high end application,
shown in Fig.10, consult the flow chart of Fig.9. When the set is off, a reset can be generated by
connecting the set to the supply for the first time (stabilizer in power-on), or by pressing any key on the key matrix (stabilizer in reset mode). When the reset is generated, the stabilizer is held in the reset mode for a short period by T1. The microprocessor has to take over control by making reset mode equal to 0. The microprocessor can then proceed with the initializing process. After this action, the microprocessor has to check if the correct key has been pressed. If so, the radio can be switched on by making on equal to 0; if not, the microprocessor must switch the device to the coma mode again, by making reset mode and on both equal to 1; (wake mode is entered after a short time constant, determined by R1 × C7 × constant), and switch itself to sleep mode.
Application circuits
STABILIZER WITHOUT MICROPROCESSOR 1 The low end application is illustrated in Fig.7. When switch
SW1 is closed, a pulse is generated at the state control input by C5 and R1, and the regulator is switched from power off to the on mode (all three regulators are on). The HOLD signal can be used to control the mute signal for the power amplifiers. This signal is HIGH when all the regulators are in regulation and VP1 Schmitt trigger is true.
July 1994 13
When the reset is generated for the first time (power-on mode), the mode of the device can be detected by the hold signal. If on = 0 and hold remains LOW, then the microprocessor is in the power-on mode. In this event, the microprocessor must go to the switch-off routine (making on and reset mode both equal to 1).
Multiple output voltage regulator TDA3602
retro - rack
andbook, full pagewidth
retro - rack
andbook, full pagewidth
on / off
SW1
battery
> 220 µF
> 220 µF
C1
C1
R1
100 kΩ
R2
2.2 kΩ
V
P
V
bu
reset
1
8
3
4
C5
68 nF
47 kΩ
R1
C8 220 nF
C8 220 nF
state control
Fig.7 Low end application circuit.
V
P
V
C5
3.3 µF
C6 100 nF
1
bu
8
TDA3602
4
6
C8 220 nF
state control
TDA3602
6
ground
Regulator 1
Regulator 2
9
Regulator 3
7
hold
5
reset
3
Regulator 1
Regulator 2
Regulator 3
7
hold
C2 10 µF
C3 10 µF
C4 10 µF
C2 10 µF
C3 10 µF
C4 10 µF
MCD349 - 1
8.5 V2
5 V9
5 V continuous
mute5
8.5 V2
5 V
5 V continuous
mute
on
SW1
off
SW2
T1
R3
47 kΩ
Fig.8 Application circuit 2.
July 1994 14
ground
MCD350 - 1
Multiple output voltage regulator TDA3602
handbook, full pagewidth
SET OFF
RESET- MODE = 0
READ KEY
KEY = SET ON
Reset - pulse by pressing any key
yesno
ON = 0
RESET- MODE = 1
SET ON
READ KEY
yes no
KEY = SET OFF
RESET
ON = 1
RESET- MODE = 1
SET OFF
Fig.9 Flow chart for high end application.
July 1994 15
MCD353 - 1
Multiple output voltage regulator TDA3602
handbook, full pagewidth
8.5 V2
C2
Regulator 1
1
P
V
C8
0.68 µF
C1
220µ F
5 V
10 µF
Regulator 2
9
V
bu
C3
8
10 µF
Regulator 3
TDA3602
F
µ
C6
220
R1
5 V continuous
C4
10 µF
hold
5
7
4
C7
state control
39 Ωk
reset
3
6
100 nF
C5
1 µF
ground
R2
15 Ωk
R6
82 Ωk
R4
120 Ωk
MCD352 - 1
R3
120 Ωk
T1
stabilizer on
battery
retro - rack
infrared
ir in
V
P
rows
columns
July 1994 16
on
open
collector
hold
reset-mode
Fig.10 High end application circuit.
I / O ports
reset
security in
ground
80C51 CPU
security
Multiple output voltage regulator TDA3602
Example of a modern car radio design with the TDA3602
ESIGN CONSIDERATIONS
D A modern car radio set meets the following design
considerations:
1. Semi on/off logic. The radio set has to switch on/off by pressing the on/off key or by switching the ignition
2. Security code check
3. Low quiescent current in standby (this means that the microprocessor is off when the set is off)
4. The set must recover the state it had before an engine start or load dump
5. Apart from HOLD, RESET and VP only two more I/O lines are used for full on/off logic
6. Supply by 1 or 2 supply lines
7. Radio Data System (RDS) should be implemented in the set, but this is not a regulator problem
8. Lights must switch off during load dump
Although the TDA3602 is designed only to be supplied by a continuous supply (battery), it is also possible to use both a continuous and a switchable supply (ignition). The ignition can be used to supply also the TDA3602, although in this event additional circuitry is needed.
PPLICATION CIRCUIT WITH (SEMI-)FULL ON/OFF LOGIC
A The application circuit of Fig.11 will meet all the above
mentioned design considerations. Three circuit parts can be distinguished:
Reset circuitry
A reset is required to call-up the microprocessor when it is switched to the sleep mode or the power-on reset (first initialization of the microprocessor). To achieve this, three different types of resets should be generated:
1. When the set has been disconnected from the supply, the microprocessor must be initialized at connection to the supply for the first time. The output ports of the microprocessor are in a random state. To ensure correct initialization, a reset has to be generated. This is accomplished by the power-on state of the TDA3602. In this state the reset output is HIGH and Regulators 1 and 2 are disabled (despite the voltage on the state control pin V
being below 1.1 V). Only
sc
after the voltage on the state control pin has risen above 2.2 V can Regulators 1 and 2 be switched on again by pulling the state control pin below 1.1 V.
2. In the sleep mode the microprocessor should be called up by pressing the on/off key (normal off condition). Now the reset is also generated by the RESET output of the TDA3602. This reset output will go HIGH when Vsc decreases from the value V
to below 1.9 V.
REG3
3. At fault conditions (VP below 7.1 V, V
REG1
< V
nominal −0.3 V or
REG1
VP > 1 8 V), HOLD drops to logic 0 and the microprocessor switches off the set. In accordance with the design considerations is that the mode of operation must switch to the state it was in before an engine start or load dump occurred. To achieve this the HOLD output of the TDA3602 can be used to generate a reset pulse (only when Vsc remains below
1.1 V).
The RESET and HOLD outputs of the TDA3602 are combined to generate the reset pulses. The pulses are created by differentiating the outputs, using capacitors C8 and C9. The reset pulses are added by means of the diodes D2 and D3. The time constants are:
• tres
= 3 × R7 × C8 = 3 × 10 kΩ × 1uF = 30 ms
res(rise)
on/off button S1 should be pressed for at least 30ms, before the microprocessor will see this
• tres
• tres
• tres
hold(rise) (dis) hold(disl)
= 3 × R7 × C9 = 5.4 ms
= 3 × R8 × C8 = 140 ms
= 3 × R9 × C9 = 25 ms
the microprocessor has to wait and check if HOLD remains LOW for at least 25 ms before it switches off; now it is certain that a correct reset will occur to wake up the microprocessor again.
July 1994 17
Multiple output voltage regulator TDA3602
C11
C11
47 nF
47 nF
TR2
TR3
TR4
BULB UNIT
R10
47 Ωk
XTAL1
handbook, full pagewidth
C2
C1
220
220µF
nF
16 V
mute
power
S1
stage
Ωk
II
reset hold
Ωk
P
V
S2
S3
I/O I O O
P1.1 P1.2 P0.1 P0.2
P1.0P0.0
open-drain outputs
47 µF
C12
REG2
P
V
TDA3602SC
bu
V
µF
220
C3
R1
D4
Ω
ex1
R
100
C6
R4
1 Ωk
C11
REG1
47
nF
Ωk
100
TR1
47 µF
REG3
C7
R6
R5
GND HOLD
RESET
F
µ
10
Ωk
47
Ωk
100
C9
C8
47
C10
180 nF
1 µF
R7
nF
47
R9
D3
D2
47
R8
10 Ωk
D1
MSA723
mP 80C51
Fig.11 Application with all features of semi on/off logic.
R3
180 Ωk
Ωk
R2
390
L1
retrack
x1
xc1
A4
x2
xc2
ignition
A7
battery
14.4 V
x3xc3
July 1994 18
on/off security key matrix
x4
xc4
Multiple output voltage regulator TDA3602
A reset by the hold function can only be created when the state control pin remains LOW. This is accomplished by means of transistor T1 when Port P0,0 is high ohmic. Because of resistors R2, R3 and R5 the transistor will switch off when V an engine start, when V
falls below a level of 5.0 V. During
ignition
reaches voltages as low as
ignition
5 V, the transistor will switch off. Regulators 1 and 2 are already switched of by means of the VP Schmitt-trigger, causing the HOLD output to go LOW. When V
ignition
again increases the transistor will be switched on again (Port P0,0 has to be open = logic 1), thereby switching the state control pin to 0 V. As V
7.6 V (V
of the VP1 Schmitt-trigger) Regulators 1 and 2
rise
continues to increase above
ignition
will again switch on causing the HOLD output to go HIGH, creating a new reset pulse.
The set can also be switched off by opening the ignition key, causing transistor T1 to switch off. When the ignition key is closed again, the set will restart to the original situation that existed before the ignition key was opened.
The charge time of C6 equals 3× R4× C6 = 14ms. This is less than the reset time tres
. To avoid the TDA3602
res(rise)
switching to coma mode before the microprocessor is awakened, a double function has been given to T1. During a reset pulse T1 is on (because of resistor R7), thus Vsc will remain 0 V provided a reset occurs. After the reset pulse has disappeared, the microprocessor is able to fully control Vsc by mean of Port P0,0 or Port P1,1.
Security code circuitry
When the set is off and it is pulled out of RETRACK,×3 and ×4 are disconnected thereby switching the base of transistor T1 to the output voltage of Regulator 3 (using resistors R5 and R6). Transistor T1 is starting to conduct and a RESET pulse is generated. The microprocessor is activated and checks if Port P1,0 = logic 1. If this is so, the microprocessor knows that the set is pulled out of RETRACK and that time is limited to finish the program correctly (because the microprocessor is operating on the charge of capacitor C3). The security flag has to be set in an EEPROM and the microprocessor can switch to power-down before Regulator 3 switches to power-off.
Another possibility is that the set was running and pulled out of RETRACK. Now a hold is generated, and the hold interrupt routine has to check the security in Port P1,0.
R6 is an internal resistor in the microprocessor. An external resistor limits however the spread.
Bulb circuitry
The lights are switched on provided the RESET output of the TDA3602 is HIGH. This normally occurs when the set is switched on. Only at first connection (power-off) will the RESET output be HIGH when the set is off. In this event the lights are also switched on. This is not a problem because the required time for initializing the microprocessor will be very short.
When a load dump occurs, the RESET output will go LOW, disabling the lights. With the aid of this feature it is possible to prevent the light bulbs being damaged at load dump.
Noise.
Regulators 1 and 2 are loaded with a 47 µF/16 V load capacitor because of output noise. With this value the output noise will be lower than 220 µV for Regulator 1 and lower than 120 µV for Regulator 2 (see Table 3 and associated text).
To minimize the noise on the supply line, capacitors C1 and C2 should be placed as close as possible across the supply and ground pins of the TDA3602.
Timing diagram
In the timing diagram all of the situations which can occur are shown (see Fig.12). A HIGH of switch S1 indicates that S1 is pressed. A HIGH on Port P0,0 indicates that Port P0,0 is high ohmic (Port P0 is an open-collector output). If no open-collector output is available another port can be used, but an extra diode has to be added in series with this port to prevent T1 being switched on by this port. A HIGH for the microprocessor indicates that the microprocessor is operating, a LOW indicates that the microprocessor is in standby mode.
The following situations are covered in the timing diagram:
1. Initialization of the microprocessor (TDA3602 in power-off mode)
2. Switching the ignition with the set off (Port P0,0 = logic 0)
3. Switching the set on/off/on by pressing S1 sequentially (ignition available)
4. Switching behaviour at engine start and load dump (set on)
5. Switching the set off and on again by switching the ignition.
July 1994 19
Multiple output voltage regulator TDA3602
The timing diagram can only be understood after a thorough investigation of the flow charts (see section Flow chart semi on/off logic with security code). Furthermore short and long RESET pulses can be seen (see Fig.12).
handbook, full pagewidth
V
battery
ignition
V
REG3
A4
A7
Flowchart semi on/off logic with security code
This section describes the software for controlling the TDA3602 (semi on/off logic). A “o” in the flowchart flow diagram Fig.13, indicates that the port mentioned is switched as an output. A “1” indicates that the port mentioned is switched as an input (temporarily).
The flowchart of figure 13 can be used for semi on/off logic.
reset
microprocessor
reset
V
SC
S1
microprocessor
REGULATORS
1 and 2
hold
P0. 0
initialization on
off on engine start load dump off by ignition
switch 1
MSA724
Fig.12 Timing of the applications.
July 1994 20
Multiple output voltage regulator TDA3602
handbook, full pagewidth
WAIT 25 ms
HOLD ?
= 0
SET
FLAG ?
= 1
P0, 0 (in)
= 1
P0, 0 = 0 (o)
= 1
= 0
= 0
START
P1, 0 ?
= 0
P1, 0 ?
SET FLAG = 1
= 1 set disconnected
= 1 first connection
SET FLAG = 1
SET ON
S
PRESSED
?
Po, 2 = 0 SEC FLAG = 0 SET FLAG = 0 P0, 0 = 0 (o)
µP: POWER DOWN
noyes
= 1
STOP
INTERUPT
HOLD = 0
HOLD ?
WAIT 10 ms
P0, 0 = 1 (o) P0, 0 = 0 (o)
P0, 0 = 1 (o)
µ
P
POWER DOWN
STOP
hold LOW because of:
Fig.13 Interfacing flow chart TDA3602.
July 1994 21
RTI
set pulled out
(1)
of RETRACK
SEC FLAG = 1
regulator fault ignition = 0
= 1
= 0
P1, 0 ?
= 0
TIME OUT
= 25 ms ?
noyes
MSA728
Multiple output voltage regulator TDA3602
C11
C11
47 nF
47 nF
TR2
TR3
TR4
BULB UNIT
R10
47 Ωk
XTAL1
handbook, full pagewidth
C2
C1
220 nF
16 V
220µF
mute
power
S1
stage
Ωk
II
reset hold
Ωk
P
V
S2
S3
I/O I O O
P1.1 P1.2 P0.1 P0.2
P1.0P0.0
open-drain outputs
47 µF
C12
REG2
P
V
TDA3602SC
bu
V
220 µF
C3
R1
1 Ωk
C6
R4
C11
REG1
47 nF
Ωk
100
TR1
47 µF
REG3
C7
R6
R5
GND HOLD
RESET
F
µ
10
Ωk
47
Ωk
100
C9
C8
47
C10
180 nF
1 µF
R7
nF
47
R9
D3
D2
47
R8
10 Ωk
D1
MSA725
mP 80C51
Fig.14 Application with all features of full on/off logic.
R3
180 Ωk
Ωk
R2
x2
xc2
ignition
A7
390
battery
14.4 V
x3xc3
L1
retrack
x1
xc1
A4
July 1994 22
on/off security key matrix
C6
47 nF
x4
xc4
Multiple output voltage regulator TDA3602
FULL ON/OFF LOGIC Using application circuit Fig.14, full on/off logic can be
achieved. Also extra software loops are required to enable the set when ignition is off. The set can be controlled by
halfpage
START
P1, 1 = 1 (i)
X = Sx
X Sx + 4 ?
yes
P0, X = 0
Y = Sy
Y Sy + 4 ?
yes
input P1, Y
Y = Y + 1
P0, X = 1 X = X + 1
P1, 1 = 0 (o)
no
no
t R4 x C6 x in (5/3) t 2.4 ms
Port P1,1 if the ignition is off (thus no extra I/O ports of the microprocessor are required for full on/off logic).
Because Port P1,1 is a part of the key matrix the complete key-scan loop must be finished within less than 0.5 × R4 × C6 = 2.4 ms, otherwise the TDA3602 will enter the reset state and Regulators 1 and 2 are switched off during this key-scan loop. When the time of the complete loop is within 2.4 ms the Vsc will remain below 2 V (thus Regulators 1 and 2 remain on).
It is also possible to switch Port P1,1 during the key-scan loop sequentially from output (logic 0) to input. If this is achieved within a time period of 1 ms, Vsc cannot become HIGH long enough to switch Regulators 1 and 2 off.
When ignition is available, transistor T1 overrules Port P1,1. In this event no variation on Vsc is seen during the key-scan loop.
The flow chart presented in Fig.15 is only required for the full on/off logic application of Fig.14.
The complete key-scan routine must be finished within 2.4 ms (when ignition is off) and that the key-scan routine has to end with a statement P1,1 = logic 0. In the flow chart of the key-scan routine, Sx is the start value of the rows and Sy the start value of the columns. With Sx = 1 and Sy = 1, one '0' is shifted on the output ports P0,1 to P0,5 and the input ports P1,1 to P1,5 are being read sequentially per shift action.
Connections between microprocessor and Regulator 2 supplied
STOP
MSA727
Fig.15 Software key matrix with loops.
July 1994 23
When digital ICs, supplied by Regulator 2, are connected to I/O ports (especially Ports 1 and 2), special attention in the software has to be taken to avoid currents flowing from Regulator 3 to Regulator 2. Because of ESD diodes in digital ICs a current can flow from an output port (which is in a high state) through the ESD diode into Regulator 2. This will cause an increase in the quiescent current of the set. The recommended action to avoid this problem is to switch the specific I/O ports to logic 0.
Multiple output voltage regulator TDA3602
handbook, full pagewidth
REGULATORS
1 and 2
V
SC
S1
P1. 1
P0. 1
P0. 2
ignition switch = open (set was on with ignition off)
2 V
t 2.4 V
0
key scan cycle
S1 pushed to switch-off S1 pushed to switch-on
Fig.16 Timing key matrix.
open
MSA726
July 1994 24
Multiple output voltage regulator TDA3602
PACKAGE OUTLINE
SIL9MPF: plastic single in-line medium power package with fin; 9 leads
D
D
1
q
P
pin 1 index
P
1
q
2
q
1
SOT110-1
A
2
A
3
A
A
4
E
seating plane
19
Z
b
e
2
b
b
1
0 5 10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A
18.5
17.8
2
max.
3.7
A
8.7
8.0
b
0.67
0.50
b
1
2
1.40
1.14
bcD
A
3
4
15.8
1.40
15.4
1.14
0.48
0.38
21.8
21.4
(1)
D
1
21.4
20.7
A
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE VERSION
IEC JEDEC EIAJ
REFERENCES
SOT110-1
w M
(1)
E
eLPP
6.48
6.20
2.54
3.9
3.4
L
c
Q
(1)
w
0.25
Z
max.
1.0
2.75
2.50
1
3.4
3.2
q
Q
1.75
15.1
1.55
14.9
EUROPEAN
PROJECTION
q1q
2
5.9
4.4
5.7
4.2
ISSUE DATE
92-11-17 95-02-25
July 1994 25
Multiple output voltage regulator TDA3602
SOLDERING Introduction
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used.
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in
“IC Package Databook”
our
Soldering by dipping or by wave
The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds.
DEFINITIONS
(order code 9398 652 90011).
The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (T printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit.
Repairing soldered joints
Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds.
stg max
). If the
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
July 1994 26
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