Using the latesthigh voltage MESHOVERLAY
process, SGS-Thomson has designed an advanced family of power MOSFETs with outstanding performances. The new patent pending strip
layout coupled with the Company’s proprietary
edge termination structure, gives the lowest
RDS(on) per area, exceptional avalanche and
dv/dt capabilities and unrivalled gate charge and
switchingcharacteristics.
Ther mal Resistance J unctio n-c aseMax
Ther mal Resistance J unctio n-am bi entMax
Ther mal Resistance Cas e - si nkTy p
Maximum Lead Te mperature F or Soldering Pur pose
l
Avalanche Curre nt , Repet it i ve or Not-Repe t it ive
(pulse widt h limite d by T
Singl e Pul se Avalan che Energ y
AS
(starti ng T
=25oC, ID=IAR,VDD=50V)
j
max)
j
0.277
30
0.1
300
34A
1000mJ
o
C/W
o
C/W
o
C/W
o
C
ELECTRICAL CHARACTERISTICS (T
=25oC unless otherwisespecified)
case
OFF
SymbolParameterTest Cond itionsMin.Typ.Ma x.Unit
V
(BR)DSS
Drain-source
= 250 µAVGS=0
I
D
500V
Break dow n V oltage
I
I
DSS
GSS
Zero Gat e Voltage
Drain Curr ent (V
GS
Gat e- bod y Leaka ge
Current (V
DS
=0)
=0)
V
=MaxRating
DS
= Max RatingTc=125
V
DS
o
C
= ± 30 V
V
GS
10
100
± 100nA
ON (∗)
SymbolParameterTest Cond itionsMin.Typ.Ma x.Unit
V
GS(th )
R
DS(on)
Gat e Thre shold V oltage
St at i c D r ain -s ource On
V
DS=VGSID
=250µA
VGS=10VID= 17 A0.110.13Ω
345V
Resistance
I
D(on)
On St ate Drain Current VDS>I
D(on)xRDS(on)max
34A
VGS=10V
DYNAMIC
SymbolParameterTest Cond itionsMin.Typ.Ma x.Unit
g
(∗)Forward
fs
Tr ansc on ductance
C
C
C
Input Capacit an c e
iss
Out put Capacitanc e
oss
Reverse Transfer
rss
Capaci ta nc e
VDS>I
D(on)xRDS(on)maxID
=17A1820S
VDS=25V f=1MHz VGS= 07000
950
80
9100
1235
104
µA
µA
pF
pF
pF
2/8
STY34NB50
ELECTRICAL CHARACTERISTICS (continued)
SWITCHINGON
SymbolParameterTest Cond itionsMin.Typ.Ma x.Unit
t
d(on)
t
r
Turn-on T ime
Rise Tim e
VDD=250VID=17A
=4.7 ΩVGS=10V
R
G
46
32
(see test cir c ui t , figure 3)
Q
Q
Q
Tot al Gate Char g e
g
Gate-Source Charge
gs
Gat e- Drain Charge
gd
VDD=400V ID=34A VGS= 10 V159
35
67
SWITCHINGOFF
SymbolParameterTest Cond itionsMin.Typ.Ma x.Unit
t
r(Voff)
t
t
Off-voltage Rise Time
Fall Time
f
Cross-over T ime
c
VDD=400VID=34A
=4.7 ΩVGS=10V
R
G
(see test cir c ui t , figure 5)
56
53
120
SOURCE DRAIN DIODE
SymbolParameterTest Cond itionsMin.Typ.Ma x.Unit
I
V
I
SDM
SD
Q
I
RRM
SD
t
Source-drain Current
(•)
Source-drain Current
(pulsed)
(∗)For ward O n VoltageISD=34A VGS=01.6V
Reverse Recovery
rr
Time
Reverse Recovery
rr
= 34 Adi/dt = 100 A/µs
I
SD
=100VTj= 150oC
V
DD
(see test cir c ui t , figure 5)
950
12
Charge
Reverse Recovery
25
Current
64
45
223nC
78
74
168
34
136
ns
ns
nC
nC
ns
ns
ns
A
A
ns
µC
A
(∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
(•) Pulse widthlimited by safe operating area
Information furnished isbelieved to be accurate andreliable. However,STMicroelectronics assumes no responsibility for theconsequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject tochange without notice.This publication supersedes and replaces allinformation previously supplied. STMicroelectronics products
are not authorized for use as critical componentsin life support devices or systems withoutexpress written approval of STMicroelectronics.
Australia - Brazil - Canada- China - France- Germany- Italy - Japan- Korea- Malaysia - Malta- Mexico - Morocco- TheNetherlands -
Singapore- Spain - Sweden - Switzerland- Taiwan - Thailand - United Kingdom- U.S.A.
The ST logo isa trademarkof STMicroelectronics
1998STMicroelectronics – Printed in Italy – All Rights Reserved
STMicroelectronicsGROUP OF COMPANIES
.
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