SGS Thomson Microelectronics STA015T, STA015B, STA015 Datasheet



STA015 STA015B STA015T

MPEG 2.5 LAYER III AUDIO DECODER

SINGLE CHIP MPEG2 LAYER 3 DECODER
SUPPORTING:

- All features specifiedfor Layer III in ISO/IEC
11172-3(MPEG 1 Audio)

- All features specifiedfor Layer III in ISO/IEC
13818-3.2(MPEG2 Audio)

- Lowersamplingfrequenciessyntaxextension,
(not specifiedby ISO) called MPEG 2.5

DECODES LAYER III STEREO CHANNELS,
DUAL CHANNEL, SINGLE CHANNEL
(MONO)

SUPPORTING ALL THE MPEG 1 & 2 SAM­PLING FREQUENCIES AND THE EXTEN­SIONTO MPEG 2.5:
48, 44.1, 32, 24, 22.05, 16, 12, 11. 025, 8 KHz

ACCEPTS MPEG 2.5 LAYER III ELEMEN­TARY COMPRESSED BITSTREAM WITH
DATARATE FROM 8 Kbit/sUP TO 320 Kbit/s

ADPCMCODECCAPABILITIES:

- samplefrequencyfrom 8 kHzto 32 kHz

-samplesizefrom8bitsto32bits

- encodi ngalgor i thm:DVI,

ITU- G726pack(G723- 24,G721,G723-40)

-Tonecontrolandfast-forwardcapability

EASY PROGRAMMABLE GPSO INTERFACE
FOR ENCODED DATA UP TO 5Mbit/s
(TQFP44&LFBGA 64)

DIGITALVOLUME
BASS& TREBLE CONTROL
SERIALBITSTREAM INPUT INTERFACE
EASY PROGRAMMABLE ADC INPUT INTER-

FACE
ANCILLARY DATA EXTRACTION VIA I2C IN-

TERFACE.
SERIAL PCM OUTPUT INTERFACE (I

ANDOTHER FORMATS)
PLL FOR INTERNAL CLOCK AND FOR OUT-

PUTPCM CLOCK GENERATION
CRC CHECK AND SYNCHRONISATION ER-

ROR DETECTION WITH SOFTWARE INDI­CATORS

2

I

C CONTROL BUS
LOW POWER2.4VCMOS TECHNOLOGY
WIDE RANGE OF EXTERNAL CRYSTALS

FREQUENCIES SUPPORTED

2

WITH ADPCM CAPABILITY

PRODUCT PREVIEW

ORDERING NUMBERS: STA015 (SO28)

APPLICATIONS

PC SOUNDCARDS
MULTIMEDIA PLAYERS
VOICERECORDERED

DESCRIPTION

The STA015 is a fully integrated high flexibility
MPEG Layer III Audio Decoder, capable of de­coding Layer III compressedelementary streams,
as specified in MPEG 1 and MPEG 2 ISO stand­ards. The device decodesalsoelementarystreams

S

compressedby usinglow samplingrates,as speci­fiedby MPEG2.5.

STA015 receives the input data through a Serial
Input Interface. The decoded signal is a stereo,
mono, or dual channel digital output that can be
sent directly to a D/Aconverter, by the PCM Out­put Interface.This interface is software program­mable to adapt the STA015 digital output to the
most common DACs architectures used on the
market.

The functional STA015 chip partitioning is de­scribed in Fig.1 and Fig.2.

STA015T (TQFP44)

STA015B (LFBGA 64)

February 2000

This is preliminary informationon a new product now in development or undergoing evaluation. Details are subject to changewithout notice.

1/44

STA015-STA015B-STA015T

Figure1a. BLOCK DIAGRAM for TQFP44 and LFBGA64 package

SDA SCL

TQFP44

31 32

I2C CONTROL

34

SDI

SCKR

BIT_EN

DATA-REQ

SCK_ADC

CRCK_ADC

SDI_ADC

36

38

27

40

26

24

SERIAL

INPUT

INTERFACE

ADC

INPUT

INTERFACE

25

RESET

BUFFER

256 x 8

PARSER

SYSTEM & AUDIO CLOCKS

15 13 22 12

XTI XTO FILTTESTEN

MPEG L

ADPCM

CORE

Figure1b. BLOCK DIAGRAMfor SO28 package

SDA SCL

34

SO28

GPIO

INTERFACE

DSP BASED

42

III

VOLUME

& TONE

CONTROL

OUTPUT
BUFFER

PCM

OUTPUT

INTERFACE

GPSO

INTERFACE

D99AU1116

44

2

3

4

28

33

SDO

SCKT

LRCKT

OCLK

GPSO_REQ

GPSO_SCKL

GPSO_DATA

SDI

SCKR

BIT_EN

DATA-REQ

SCK_ADC

CRCK_ADC

SDI_ADC

2/44

5

6

7

28

8

27

25

SERIAL

INPUT

INTERFACE

ADC

INPUT

INTERFACE

BUFFER

256 x8

26

RESET

I2C CONTROL

MPEG L

PARSER

ADPCM

CORE

III

SYSTEM & AUDIO CLOCKS

21 20 24 19

XTI XTO FILTTESTEN

DSP BASED

VOLUME

&

TONE

CONTROL

OUTPUT
BUFFER

PCM

OUTPUT

INTERFACE

D99AU1117

9

SDO

10

SCKT

11

LRCKT

12

OCLK

Figure2. PINCONNECTIONS

STA015-STA015B-STA015T

VDD_1

VSS_1

SCKR

BIT_EN

SRC_INT/SCK_ADC

SCKT

LRCKT

OCLK

VSS_2

VDD_2

1

N.C.

2

LRCKT

3

OCLK

VSS_2

VDD_2

VSS_3

VDD_3

N.C.
PVDD
PVSS

4
5
6
7
8
9
10

GPSO_REQ

BIT_EN

IODATA[5]

28
27
26
25
24
23
22
21
20
19
18
17
16
1514

SCKR

IODATA[4]

1
2
3

SCL

SDI

SDO

44 43 42 41 3940 38 37 36 35 34

SCKT

SDO

IODATA[7]

4
5
6
7

SO28

8
9
10
11
12
13

D99AU1061

SRC_INT/SCK_ADC

IODATA[6]

TQFP44

XTI

IODATA[3]

IODATA[2]

171118 19 20 21 22

N.C.

VSS_4

IODATA[1]

IODATA[0]

12 13 14 15 16

FILT

XTO

OUT_CLK/DATA_REQ
LRCK_ADC
RESETSDA
SDI_ADC
TESTEN
VDD_4
VSS_4
XTI
XTO
FILT
PVSS
PVDD
VDD_3
VSS_3

SDI

GPIO/STROBE

33

GPSO_DATA

32

SCL

31

SDA

30

VSS_1

29

VDD_1

28

GPSO_SCKR

27

OUT_CLK/DATA_REC

26

LRCK_ADC

25

RESET

24

SDI_ADC

23

N.C.

D99AU1062

VDD_4

TESTEN

12345678

A1 =

SDI
A
B
C
D
E

F
G
H

B2 = SCKR
D4 = BIT_EN
D1 =

SRC_INT

E2 =

SDO
F2 = SCKT
H1 =

LRCKT
H3 =

OCLK
F3 =

VSS_2

E4 =

VDD_2
G4 =

VSS_3

G5 =

VDD_3
F5 = PVDD
G6 = PVSS

D00AU1149

G7 = FILT
G8 = XTO
F7 = XTI
E7 =

VSS_4

C8 =

VDD_4
D7 = TESTEN
A7 =

SDI_ADC
B6 = RESET
A5 =

LRCK_ADC
C5 =

OUT_CLK/DATA_REQ

B5 =

VDD_1
B4 =

VSS_1
A4 = SDA
B3 = SCL

C2 =

GPIO_STROBE
C3 = IODATA
E3 = IODATA
D2 = IODATA
F1 = IODATA
G3 =

GPSO_REQ
F8 = IODATA
F6 = IODATA
E6 = IODATA
C7 = IODATA
C6 =

GPSO_SCKR

[4]
[5]
[6]

[7]
[3]

[2]
[1]

[0]

A2 = GPSO_DATA

LFBGA64

3/44

STA015-STA015B-STA015T

1. OVERVIEW

1.1 - MP3 decoderengine

The MP3 decoder engine is able to decode any
Layer III compliant bitstream: MPEG1, MPEG2
and MPEG2.5 streams are supported. Besides
audio data decoding the MP3 engine also per­forms ANCILLARY data extraction: these data
can be retrieved via I2C bus by the application
microcontroller in order to implement specific
functions.

Decodedaudio data goesthrough a software vol­ume control and a two-band equalizer blocks be­fore feeding the output I2S interface. This results
in no need for an external audio processor.

MP3 bitstream is sent to the decoderusing a sim­ple serial input interface (see pins SDI, SCKR,
BIT_EN and DATA_REQ), supporting input rate
up to 20 Mbit/s. Received data are stored in a
256 bytes long input buffer which provides a

ABSOLUTE MAXIMUM RATINGS

feedback line (see DATA_REQ pin) to the bit­streamsource (tipicallyan MCU).

1.2 - ADPCMencoder/decoder engine

This device also embeds a multistandardADPCM
encoder/decoder supporting different sample
rates (from 8 KHz up to 32 KHz) and different
sample sizes (from 8 bit to 32 bits). During en­coding process two different interfaces can be
used to feeddata: theserial input interface (same
interface used also to feed MP3 bitstream) or the
ADC input interface, which provides a seamless
connection with an external A/D converter. The
currentlyused interface is selected via I2Cbus.

Also to retrieve encoded data two different inter­faces are available: the I2C bus or the faster
GPSOoutput interface. GPSO interface is able to
output data with a bitrate up to 5 Mbit/s and its
control pins (GPSO_SCKR, GPSO_DATA and
GPSO_REQ)can be configuredin order to easily
fit thetarget application.

Symbol Parameter Value Unit

V

DD

V

i

V

O

T

stg

T

oper

Power Supply -0.3 to 4 V
Voltageon Input pins -0.3 to VDD+0.3 V
Voltageon output pins -0.3 to VDD+0.3 V
Storage Temperature -40 to +150 °C
Operative ambient temp -20 to +85 °C

THERMALDATA

Symbol Parameter Value Unit

R

th j-amb

Thermal resistance Junction to Ambient 85 °C/W

4/44

STA015-STA015B-STA015T

PIN DESCRIPTION

SO28 TQFP44 LFBGA64 Pin Name Type Function PAD Description

1 29 B5 VDD_1 Supply Voltage
2 30 B4 VSS_1 Ground
3 31 A4 SDA I/O i

4 32 B3 SCL I I
5 34 A1 SDI I Receiver Serial Data CMOS Input Pad Buffer
6 36 B2 SCKR I ReceiverSerial Clock CMOS Input Pad Buffer
7 38 D4 BIT_EN I Bit Enable CMOSInput Pad Bufferwith

8 40 D1 SRC_INT/SCK_ADC I Interrupt Line/ADC Serial

9 42 E2 SDO O TransmitterSerialData(PCMData) CMOS 4mA Output Drive
10 44 F2 SCKT O Transmitter Serial Clock CMOS 4mA Output Drive
11 2 H1 LRCLKT O Transmitter Left/Right Clock CMOS 4mA Output Drive
12 3 H3 OCLK I/O Oversampling Clock for DAC CMOS Input Pad Buffer

13 5 F3 VSS_2 Ground
14 6 E4 VDD_2 Supply Voltage
15 7 G4 VSS_3 Ground
16 8 G5 VDD_3 Supply Voltage
17 10 F5 PVDD PLL Power
18 11 G6 PVSS PLL Ground
19 12 G7 FILT O PLL Filter Ext. Capacitor

20 13 G8 XTO O Crystal Output CMOS 4mA Output Drive
21 15 F7 XTI I Crystal Input (Clock Input) Specific Level InputPad

22 19 E7 VSS_4 Ground
23 21 C8 VDD_4 Supply Voltage
24 22 D7 TESTEN I Test Enable CMOSInputPad Bufferwith

25 24 A7 SDI_ADC I ADC Data Input CMOS Input Pad Buffer
26 25 B6 RESET I System Reset CMOSInputPad Bufferwith

27 26 A5 LRCK_ADC I ADC Left/Right Clock CMOS Output Pad Buffer
28 27 C5 OUT_CLK/

DATA_REQ
20 C7 IODATA[0] I/O GPIO Data Line CMOS 4mA Schmitt Trigger
18 E6 IODATA[1] I/O GPIO DataLine
16 F6 IODATA[2] I/O GPIO Data Line
14 F8 IODATA[3] I/O GPIO Data Line
37 C3 IODATA[4] I/O GPIO Data Line
39 E3 IODATA[5] I/O GPIO DataLine
41 D2 IODATA[6] I/O GPIO Data Line
43 F1 IODATA[7] I/O GPIO Data Line
35 C2 GPIO_STROBE I/O GPIO Strobe Signal

4 G3 GPSO_REQ O GPSO Request Signal CMOS Output Pad Buffer
28 C6 GPSO_SCKR I GPSO Serial Clock CMOS Input Pad Buffer
33 A2 GPSO_DATA O GPSO Serial Data CMOS Output Pad Buffer

Note: In functional mode TESTEN must be connectedto VDD.

2

C Serial Data +

Acknowledge

2

C Serial Clock CMOS Input Pad Buffer

CMOS Input Pad Buffer
CMOS 4mA Output Drive

pullup
CMOS Input Pad Buffer

Clock

CMOS 4mA Output Drive

Conn.

(see paragraph 2.1)

pull up

pull up

O Buffered Output Clock/

CMOS 4mA Output Drive

Data Request Signal

Bidir Pad Buffer

5/44

STA015-STA015B-STA015T

1. ELECTRICAL CHARACTERISTICS:VDD = 3.3V ±0.3V;Tamb = 0 to 70°C;Rg = 50Ω unless otherwise

specified

DC OPERATINGCONDITIONS

Symbol Parameter Value

V

T

GENERAL INTERFACE ELECTRICAL CHARACTERISTICS

Symbol Parameter Test Condition Min. Typ. Max. Unit Note

Note 1: Theleakage currentsare generally very small, < 1nA. The valuegiven here is a maximum that can occur after an electrostaticstress

on the pin.

Note 2: Human Body Model.

DC ELECTRICALCHARACTERISTICS

Symbol Parameter Test Condition Min. Typ. Max. Unit Note

Power Supply Voltage 2.4to 3.6V

DD

Operating Junction Temperature -20 to 125°C

j

I

IL

Low LevelInput Current

Vi= 0V -10 10 µA1

Without pull-up device

I

IH

High Level Input Current

Vi=V

DD

-10 10 µA1

Without pull-up device

V

esd

V

IL

V

IH

V

ol

V

oh

Electrostatic Protection Leakage < 1µA 2000 V 2

Low LevelInput Voltage 0.2*V
High Level Input Voltage 0.8*VDD V
Low LevelOutput Voltage Iol= Xma 0.4V V 1, 2
High Level Output Voltage 0.85*V

DD

V

DD

V1,2

Note 1:

Takes into account 200mV voltage drop in both supplylines.

Note 2: Xis the source/sink current under worst case conditions and is reflected in thename of the I/O cell according to the drive capability.

Symbol Parameter Test Condition Min. Typ. Max. Unit Note

I

pu

R

pu

Pull-up current Vi= 0V; pinnumbers 7, 24
Equivalent Pull-up

and 26

-25 -66 -125 µA1
50 kΩ

Resistance

Note 1:

Min.condition: V

Max. condition: V

DD

= 2.7V, 125°C Min process

DD = 3.6V, -20°C Max.

POWERDISSIPATION

Symbol Parameter Test Condition Min. Typ. Max. Unit Note

PD Power Dissipation

@V

=3V

DD

Sampling_freq ≤24 kHz 76 mW
Sampling_freq ≤32 kHz 79 mW
Sampling_freq ≤48 kHz 85 mW

6/44

STA015-STA015B-STA015T

Figure3.

Test Circuit (refer to SO28 package)

OUT_CLK/DATA_REQ

PV

V

DD

PV

V

SS

Figure4. Test Load Circuit

I

OL

V

V

V

V

DD

SS

DD

100nF

DD

100nF

DD

100nF

DD

100nF

SDA

3

SCL

24

TESTEN

D00AU1143

4

9
10
11
12

5

6

7
25

8
27
21
20
19

SDO
SCKT
LRCKT
OCLK
SDI
SCKR
BIT_EN
SDI_ADC

SCR_INT
LRCK_ADC

XTI
XTO

470pF

10K

1K

4.7nF

PV

SS

1

V

SS

V

SS

V

SS

V

SS

2

14

13

16

15

23

22

17 182826

100nF4.7µF 4.7µF

PV

PV

SS

DD

RESET

Test Load

V

Output I

DD

SDA 1mA 100pF 3.6V

OL

Other Outputs 100µA 100µA 100pF 1.5V

I

OH

C

V

L

REF

OUTPUT

C

I

L

OH

2. FUNCTIONAL DESCRIPTION

2.1 - Clock Signal

The STA015 input clock is derivated from an ex­ternal source or from a industry standard crystal
oscillator, generating input frequencies of 10,

V

REF

D98AU967

Other frequencies may be supported upon re­quest to STMicroelectronics. Each frequency is
supported by downloading a specific configura­tion file, provided by STM

XTI is an input Pad with specificlevels.

14.31818 or14.7456 MHz.

Symbol Parameter Test Condition Min. Typ. Max. Unit

V

IL

V

IH

Low LevelInput Voltage VDD-1.8 V
High Level Input Voltage VDD-0.8 V

CMOScompatibility
The XTI pad low and high levels are CMOS compatible; XTI pad noise margin is better than typical
CMOSpads.

TTL compatibility
The XTI pad low level is compatible with TTL while the high level is not compatible(for example if V

DD =

3V TTL min high level = 2.0V while XTI min high level = 2.2V)

7/44

STA015-STA015B-STA015T

Figure5. PLL and Clocks GenerationSystem

XTI

N

PFD CP

M

FRAC

Update FRAC

Switching
Circuit

2.4 - PCM Output Interface

The decodedaudio data are output in serial PCM
format.The interface consists of the followingsig­nals:

SDO PCM Serial Data Output
SCKT PCM SerialClock Output
LRCLK Left/RightChannel SelectionClock
The output samples precision is selectable from

Figure6. PCM OutputFormats

16 SCLK Cycles

LRCKT

16 SCLK Cycles

R
CC

VCO

Disable PLL

OCLK

X

XTI2OCLK

DCLK

S

XTI2DSPCLK

16 to 24 bits/word, by setting the outputprecision
with PCMCONF (16, 18, 20 and 24 bits mode)
register. Data can be output either with the most
significant bit first (MS) or least significant bit first
(LS), selected by writing into a flag of the
PCMCONFregister.
Figure 8 gives a description of the several
STA015PCM OutputFormats.

The sample rates set decoded by STA015 is de­scribed in Table 1.

16SCLK Cycles

16 SCLK Cycles

16 SCLK Cycles

Table 1:

SDO

SDO

LRCKT

SDO

SDO

SDO

SDO

M
S

L
S

32 SCLK Cycles

M

L

S

S

M

0

S

L

M

0

S

S

M
S

M

L

S

S

L

M

S

S

32 SCLK Cycles

M
S

L
S

M

00

00

S

L

MSBMSB

S

L

M

S

S

L

M

S

S

32SCLK Cycles

L
S

M
S

M
S

MSL

00

L
S

L
S

L
S

S

M

00

S

MSL

S

MSL

MSB MSB

M

L

S

S

M

L

S

S

32 SCLK Cycles

M

0

L
S

00

S

L

S

S

M

0

S

L

M

0

S

S

M
S

PCM_ORD = 0

L
S

PCM_PRECis 16 bit mode

PCM_ORD = 1

M
S

PCM_PRECis 16 bit mode

32 SCLK Cycles

PCM_FORMAT = 1

0

PCM_DIFF = 1

PCM_FORMAT = 0

L
S

PCM_DIFF = 0

PCM_FORMAT = 0
PCM_DIFF = 1

PCM_FORMAT = 1

L
S

PCM_DIFF = 1

MPEGSampling Rates (KHz)

MPEG 1 MPEG 2 MPEG 2.5

48 24 12

44.1 22.05 11.025
32 16 8

8/44

STA015-STA015B-STA015T

2.5 - STA015Operation Mode

The STA015 can work in two different modes,
calledMultimediaMode and BroadcastMode.

In

Multimedia Mode

(default mode) STA015 de­codes the incoming bitstream, acting as a master
of the data communication from the source to it­self.
This control is done by a specific buffer manage­ment,controlledbySTA015 embedded software.

The data source, by monitoring the DATA_REQ
line, send to STA015 the input data, when the
signalis high (defaultconfiguration).
The communication is stopped when the
DATA_REQline is low.
In this mode the fractional part of the PLL is dis­abled and the audio clocks are generated at
nominal rates. Fig. 7 describes the default
DATA_REQ signal behaviour. Programming
STA015 it is possible to invert the polarity of the
DATA_REQline (register REQ_POL).

Figure7.

SOURCE STOPS TRANSMITTING DATA SOURCE STOPS TRANSMITTING DATA

DATA_REQ

SOURCE SEND DATA TO STA015

D00AU1144

In Broadcast Mode, STA015 works receiving a
bitstream with the input speed regulated by the
source. In this configuration the source has to
guarantee that the bitrate is equivalent to the
nominalbitrateof the decodedstream.

To compensate the difference between the nomi­nal and the real sampling rates, the STA015 em­bedded software controls the fractional PLL op­eration. Portable or Mobile applications need

normally to operate in Broadcast Mode. In both
modes the MPEG Synchronisation is automatic
and transparentto the user.

2.6 - STA015Decoding States
There are three different decoder states: Idle,

Init, and Decode. Commands to change the de-

coding states are described in the STA015 I

2

C

registersdescription.
Idle Mode

In this mode the decoder is waiting for the RUN
command. This mode shouldbe used to initialise
the configuration registers of the device. The
DAC connected to STA015 can be initialised dur­ing this mode (set MUTE to 1).

PLAY MUTE Clock State PCM Output

X 0 Not Running 0
X 1 Running 0

Init Mode
”PLAY” and ”MUTE” changes are ignored in this

mode. The internal state of the decoder will be
updatedonly when the decoder changes from the
state ”init” to the state ”decode”.The ”init” phase
ends when the first decoded samples are at the
output stage of the device.

Decode Mode
This mode is completely described by the follow-

ing table:

PLAY MUTE Clock State

0 0 Not Running 0 No
0 1 Running 0 No
1 0 Running Decoded

1 1 Running 0 Yes

PCM

Output

Samples

Decoding

Yes

9/44

STA015-STA015B-STA015T

Figure8.

MPEGDecoder Interfaces.

DATA_REQ

SDI

DATA

SOURCE

D98AU912

SCKR

BIT_EN

Figure9. Serial Input Interface Clocks

SDI

XTO

XTI FILT

PLL

MPEG

DECODER

SERIAL AUDIO INTERFACE

RX TX

µP

IIC

SCL SDA

IIC

DATA IGNORED

SDO

SCKT

LRCKT

DAC

OCLK

SCKR

SCKR

BIT_EN

D98AU968A

2.2 - SerialInput Interface

STA015 receives the input data (MSB first)
thought the Serial Input Interface (Fig.5). It is a
serial communication interface connected to the
SDI (Serial Data Input) and SCKR (Receiver Se­rial Clock).
The interface can be configured to receive data
sampled on both rising and falling edge of the
SCKR clock. The BIT_EN pin, when set to low,
forces the bitstream input interface to ignore the
incoming data. For proper operation Bit_E

N line

should be toggled only when SCRK is stable low
(for both SCLK_POL configuration) The possible
configurationsare describedin Fig. 9.

2.3 - PLL & Clock Generator System

When STA015 receives the input clock, as de­scribed in Section 2.1, and a valid layer III input
bitstream, the internal PLL locks, providing to the
DSP Core the master clock (DCLK), and to the

SCLK_POL=0

SCLK_POL=4

DATA IGNOREDDATA VALID

Audio Output Interface the nominal frequenciesof
the incomingcompressedbit stream. The STA015
PLLblockdiagramisdescribedin Figure5.
The audio sample rates are obtained dividing the
oversampl i ng clock(OCLK)by softwareprogramm a­ble factors. The operation is done by STA015 em­beddedsoftwar eand it istrans parenttotheuser.
TheSTA015PLLcandrivedirectlymost of thecom­mercial DACs families, providing an over sampling
clock, OCLK, obtaineddividing the VCO frequency
witha softwareprogrammabledividers.

2.4 - GPSOOutput Interface

In order to retrieveADPCM encoded data a Gen­eral Purpose Serial Output interface is available
(in TQFP44 and LFBGA64 packages only). The
maximum frequency for clock is the
GPSO_SCKR DSP system clock frequency di­vided by 3 (i.e. 8.192 MHz @ 24.58MHz).The in­terface is based on a simple and configurable 3­lines protocol, as described by figure10.

10/44

Figure10.

GPSO_SCKR

GPSO_REQ

GPSO_SCKR

STA015 MCU

GPSO_DATA

GPSO_REQ

STA015-STA015B-STA015T

GPSO_DATA

To enable the GPSO interface bit GEN of
GPSO_ENABLE register must be set. Using the
GPSO_CONFregister the protocol can be config­ured in order to provide outcoming data on ris-

ADPCM to provide an interrupt; the use of the
other bits is still to be defined. The related con­figurationregisteris GPIO_CONF.Seethe follow­ing summary for related pin usage:

D00AU1145

ing/falling edge of GPSO_SCKR input clock; the
GPSO_REQ request signal polarity (usually con­nected to an MCU interrupt line) can be config­uredas well.

ADC Inteface

Name Description Dir

I/ODATA [0]

GPIO data line I/O

....................

I/ODATA [7]
GPIO_STROBE GPIO strobe line I/O

Beside the serial input interface based on SDI
and SCKR lines a 3 wire flexible and user config­urable input interface is also available, suitable to
interface with most A/D converters. To configure
this interface 4 specificI

2

C registersare available
(ADC_ENABLE, ADC_CONF, ADC_WLEN and
ADC_WPOS). Refer to registers description for
more details.

2.5 ADPCM Encoding: Overview

According to the previously described interfaces
there are 4 ways to manage ADPCM data stream
while encoding. Input interface can be either the
serial receiver block (SDI + SCKR + DATA_REQ
lines) or the ADC specific interface.

Output interfaces can be either the I

General PurposeI/O Interface

A new general purpose I/O interface has been
added to this device (TQFP44 and LFBGA64
only). Actually only the strobe line is used in

INPUT (data to encode) Output (encoded data)

ADC I/F (SDI_ADC + LRCK_ADC + SCK_ADC) GPSO I/F (GPSO_REQ + GPSO_DATA +

ADC I/F (SDI_ADC + LRCK_ADC + SCK_ADC) I

SERIAL I/F (SCKR+ SDI + DATA_REQ) GPSO I/F (GPSO_REQ + GPSO_DATA +
SERIAL I/F (SCKR+ SDI + DATA_REQ) (*) I

(*) STA013 Compatible mode

GPSO_SCKR)

2

C + Interrupt (SCL + SDA + DATA_REQ) SO28/TQFP44

GPSO_SCKR)

2

C (polling) (SCL + SDA) SO28/TQFP44

or without interrupt line) or the GPSO high-speed
serial interface (GPSO_REQ + GPSO_ DATA +
GPSO_SCKRlines). This result in the following 4
methodsto handle encoding flow:

Figure.11

....

I/O

2

C bus (with

Available on

package

TQFP44

LFBGA64

LFBGA64

TQFP44

LFBGA64

LFBGA64

LRCK_ADC

SDI_ADC

SCK_ADC

SDI

SCKR

DATA_REQ

ADC I/F

SERIAL

RECEIVER

ENCOD
ENGINE

GPSOMUX

I2C

D99AU1064

GPSO_REQ
GPSO_DATA
GPSO_SCKR

SDA
SCL

DATA_REQ

11/44

STA015-STA015B-STA015T

The following 4 figures (fig. 12, 13, 14, 15) show
the available connection diagrams as for as
ADPCM encoding function. As shown in the fig­ures some configuration is not available in SO28
package.

Figure13. Input fromADC, Output from I2C +

IRQ

2

I

C

DATA_REQ

MCU

SDI_ADC

ADC

SLAVE

LRCKT

SCKT

STA015

SO28

TQFP44

LFBGA64

SDO

DAC

OCLK

Figure 12. Input from BITSTREAM,Outputfrom

I2C

SDI

SCKR

DATA_REQ

MCU DAC

BIT_EN

2

C

I

Figure 14.

Input from BITSTREAM,Outputfrom

STA015

SO28

TQFP44

LFBGA64

LRCKT

SCKT

SDO

OCLK

D99AU1121A

GPSO

GPSO_DATA
GPSO_SCKR

GPSO_REQ

MCU DACSTA015

Figure 15.

SDI

SCKR

DATA_REQ

BIT_EN

I2C

TQFP44

LFBGA64

Input from ADC, Output from GPSO

LRCKT

SCKT

SDO

OCLK

D99AU1122A

2

I

MCU

ADC

MASTER

C

DATA_REQ

LRCK_ADC

SCK_ADC
SDI_ADC

STA015

SO28

TQFP44

LFBGA64

LRCKT

SCKT

SDO

OCLK

DAC

D99AU1123A

3-I2C BUS SPECIFICATION

2

The STA015 supports the I

C protocol. This pro­tocoldefines any device that sends data on to the
bus as a transmitter and any device that reads
the data as a receiver. The device that controls
the data transfer is known as the master and the
others as the slave. The master always starts the
transfer and provides the serial clock for synchro­nisation. The STA015 is always a slave device in
all its communications.

12/44

GPSO_DATA

MCU

ADC

MASTER

GPSO_SCKR

GPSO_REQ

LRCK_ADC

SCK_ADC

SDI_ADC

STA015

TQFP44

LFBGA64

LRCKT

SCKT

SDO

OCLK

DAC

D99AU1124A

3. 1 - COMMUNICATION PROTOCOL

3.1.0 - Datatransition or change

Data changes on the SDA line must only occur
when the SCL clock is low. SDA transition while
the clock is high are used to identify START or
STOP condition.

3.1.1 - Start condition

START is identified by a high to low transition of
the data bus SDA signal while the clock signal
SCL is stable in the high state.
A START condition must precede any command
fordata transfer.

STA015-STA015B-STA015T

3.1.2 - Stopcondition

STOP is identified by low to high transition of the
data bus SDA signal while the clocksignal SCL is
stable in the high state. A STOP condition termi­nates communications between STA015 and the
busmaster.

3.1.3 - Acknowledgebit

An acknowledgebit is used to indicate a success­ful data transfer. The bus transmitter, either mas­ter or slave, releases the SDA bus after sending
8 bit of data.

During the 9th clock pulse the receiver pulls the
SDA bus low to acknowledge the receipt of 8 bits
of data.

3.1.4 - Datainput

During the data input the STA015 samples the
SDA signalon the rising edgeof the clock SCL.

For correct device operation the SDA signal has
to be stable during the rising edge of the clock
and the data can changeonly when the SCL line
is low.

3.2 - DEVICEADDRESSING
To start communication between the master and

the STA015, the master must initiate with a start
condition. Following this, the master sends onto
the SDA line 8 bits (MSB first) corresponding to
the device select address and read or write
mode.

Figure16. Write Mode Sequence

The 7 most significant bits are the deviceaddress
identifier, corresponding to the I

2

C bus definition.

For the STA015 these are fixed as 1000011.
The 8th bit (LSB) is the read or write operation

RW, this bit is set to 1 in read mode and 0 for
write mode. After a START condition the STA015
identifies on the bus the device address and, if a
match is found, it acknowledges the identification
on SDA bus duringthe 9th bit time. The following
byte after the device identification byte is the in­ternalspace address.

3.3 - WRITE OPERATION(see fig. 16)
Following a START condition the master sends a

deviceselectcode with the RW bit set to 0.
The STA015 acknowledges this and waits for the

byte of internaladdress.
After receiving the internal bytes address the

STA015againrespondswith an acknowledge.

3.3.1 - Bytewrite

In thebyte write mode the master sends one data
byte, this is acknowledged by STA015. The mas­ter then terminates the transfer by generating a
STOP condition.

3.3.2 - Multibytewrite

The multibyte write mode can start from any inter­nal address. The transfer is terminated by the
mastergenerating a STOPcondition.

BYTE

WRITE

MULTIBYTE

WRITE

START

START RW

DEV-ADDR

DEV-ADDR

Figure17. Read Mode Sequence

ACK

CURRENT
ADDRESS

READ

RANDOM
ADDRESS

READ

SEQUENTIAL

CURRENT

READ

SEQUENTIAL

RANDOM

READ

DEV-ADDR

START

DEV-ADDR

START RW

START

START RW

DEV-ADDR

DEV-ADDR

RW=

HIGH

DATA

RW

ACK

SUB-ADDR

ACK

DATA

ACK

SUB-ADDR

ACK

RW

ACK

NO ACK

ACK

START RW

ACK

ACK

START RW

SUB-ADDR

SUB-ADDR

STOP

DATA

DEV-ADDR

DEV-ADDR

ACK

ACK

ACK

ACK

ACK

DATA IN

DATA IN

DATA

DATA

DATA

ACK

ACK

STOP

NO ACK

NO ACK

ACK

D98AU825B

STOP

STOP

DATA

DATA IN

ACK

ACK NO ACK

D98AU826A

STOP

DATA

STOP

13/44

STA015-STA015B-STA015T

3.4 - READOPERATION (see Fig. 17)

3.4.1 - Currentbyte address read

The STA015 has an internal byte address
counter. Each time a byte is written or read, this
counteris incremented.
For the current byte address read mode, follow­ing a START condition the master sends the de­viceaddresswith the RW bit set to 1.

The STA015 acknowledges this and outputs the
byte addressed by the internal byte address
counter. The master does not acknowledge the
received byte, but terminates the transfer with a
STOPcondition.

3.4.2 - Sequential address read

This mode can be initiated with either a current
address read or a random address read. How­ever in this case the master does acknowledge
the data byteoutputand the STA015 continues to
outputthe nextbyte in sequence.

To terminate the streams of bytes the master
does not acknowledge the last received byte, but

2

I

C REGISTERS

terminatesthe transfer with a STOP condition.
The output data stream is from consecutive byte

addresses,with the internal byte address counter
automaticallyincrementedafter one byte output.

2

C REGISTERS

4- I

The following table gives a description of the
MPEGSource Decoder (STA015)register list.

The first column (HEX_COD) is the hexadecimal
code for the sub-address.
The second column (DEC_COD) is the decimal
code.
The third column (DESCRIPTION) is the descrip­tion of theinformationcontainedin the register.

The fourth column (RESET) inidicate the reset
value if any. When no reset value is specifyed,
the defaultis ”undefined”.

The fifth column (R/W) is the flag to distinguish
register ”read only” and ”read and write”, and the
useful size of the register itself.

Each register is 8 bit wide. The master shall oper­ate reading or writing on 8 bits only.

HEX_COD DEC_COD DESCRIPTION RESET R/W

$00 0 VERSION R (8)
$01 1 IDENT 0xAC R (8)
$05 5 PLLCTL [7:0] 0xA1 R/W (8)
$06 6 PLLCTL [20:16] (MF[4:0]=M) 0x0C R/W (8)
$07 7 PLLCTL [15:12] (IDF[3:0]=N) 0x00 R/W (8)
$0C 12 REQ_POL 0x01 R/W (8)
$0D 13 SCLK_POL 0x04 R/W (8)
$0F 15 ERROR_CODE 0x00 R (8)
$10 16 SOFT_RESET 0x00 W (8)
$13 19 PLAY 0x01 R/W(8)
$14 20 MUTE 0x00 R/W(8)
$16 22 CMD_INTERRUPT 0x00 R/W(8)
$18 24 DATA_REQ_ENABLE 0x00 R/W(8)
$40 - $51 64 - 81 ADPCM_DATA_1 to ADPCM_DATA_18 0x00 R/W (8)
$40 64 SYNCSTATUS 0x00 R (8)
$41 65 ANCCOUNT_L 0x00 R (8)
$42 66 ANCCOUNT_H 0x00 R (8)
$43 67 HEAD_H[23:16] 0x00 R(8)
$44 68 HEAD_M[15:8] 0x00 R(8)
$45 69 HEAD_L[7:0] 0x00 R(8)
$46 70 DLA 0x00 R/W (8)
$47 71 DLB 0xFF R/W (8)
$48 72 DRA 0x00 R/W (8)

14/44