SGS Thomson Microelectronics ST95P08 Datasheet

8 Kbit Serial SPI EEPROM with Positive Clock Strobe

1 MILLION ERASE/WRITE CYCLES
40 YEARS DA TA RETE NT ION
SINGLE 3V to 5.5V SUPPLY VOLTAGE
SPI BUS COMPATIBLE SERIAL INTERFACE
2 MHz CLOCK RA TE MAX
BLOCK WRITE PROTECTION
STATUS REGISTER
16 BYTE PAGE MODE
WRITE PROTECT
SELF-TIMED PROGRAMMING CY CLE
E.S.D.PROTECTION GREATER than 4000V
SUPPO RTS POSITIVE CLOCK SPI MODES

8

1

PSDIP8 (B)

0.25mm Frame

ST95P08

8

1

SO8 (M)

150mil Width

DESCRIPTION

The ST95P08 is an 8 Kbit Electrically Erasable
Programmable Memory (EEPROM) fabricated with
STMicroelectronics’s High Endurance Single
Polysilicon CMOS technology. The 8 Kbit memory
is organised as 64 pages of 16 by tes. The memory
is accessed by a simple SPI bus c ompatible serial
interface. The bus signals are a serial clock input
(C), a serial data input (D) and a serial data output
(Q). The device connected to t he bus is selected
when the chip select input (

S) goes low. Commu­nications with the chip can be interrupted with a
hold input (
by a write protect input (

HOLD). The write operation is disabled

W).

T ab le 1. Signal Names

C Serial Clock
D Serial Data Input
Q Serial Data Output
S Chip Select
W Write Protect

Figure 1. Logic Diagram

V

CC

D
C
S

W

HOLD

ST95P08

V

SS

Q

AI01315

HOLD Hold
V

CC

V

SS

February 1999 1/16

Supply Voltage
Ground

ST95P08

Figure 2A. DIP Pin Connections

ST95P08

1

SV

2
3

W

4

SS

T ab le 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

T

T

T

A

STG

LEAD

Ambient Operating Temperature
Storage Temperature –65 to 150 °C
Lead Temperature, Soldering (SO8 package) 40 sec

8
7
6
5

AI01316

CC

HOLDQ
C
DV

(1)

(2)

(PSDIP8 package) 10 sec

Figure 2B. SO Pin Connections

ST95P08

1

SV

2
3

W

SS

4

8
7
6
5

AI01317B

–40 to 85 °C

215
260

CC

HOLDQ
C
DV

°C

V

O

V

V

CC

V

ESD

Notes:

1. Except for the rating "Operating T emperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"

2. Depends on range.

3. MIL-STD-883C, 3015.7 (100pF, 1500Ω)

4. EIAJ IC-121 (Condition C) (200pF , 0Ω)

SIGNALS DESCRIPTION
Serial Output (Q ).

fer data serially out of the ST95P08. Data is shifted
out on the falling edge of the serial clock.

Serial Input (D) .

data serially into the device. It receives instructions,
addresses, and data to be written. Input is latched
on the rising edge of the serial clock.

Serial Clock (C).

timing of the serial interface. Instructions, ad­dresses, or data present at the input pin are latched

Output Voltage –0.3 to VCC +0.6 V
Input Voltage –0.3 to 6.5 V

I

Supply Voltage –0.3 to 6.5 V
Electrostatic Discharge Voltage (Human Body model)
Electrostatic Discharge Voltage (Machine model)

may cause permanent damage to the device. These are stress rating s only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and
other relevant quality documents.

(3)

(4)

4000 V

500 V

the Q pin changes after the falling edge of the clock

The output pin is used to trans-

input.

Chip Select (

S).

This input is used to select the

ST95P08. The chip is selected by a high to low

The input pin is used to transfer

transition on the
time, the chip is deselected by a low t o high t ransi­tion on the

S pin when C is at ’0’ state. At any

S pin when C is at ’0’ state. As soon as
the chip is deselected, the Q pin is at high imped­ance state. This pin allows multiple ST95P08 to

The serial clock provides the

share the same SPI bus. After power up, the chip
is at the deselect state. T r ansition of
when C is at ’1’ state.

on the rising edge of the clock input, while data on

S are ignored

2/16

Figure 3. Block Diagram

ST95P08

HOLD

W

S

C

D

Q

Control Logic

I/O Shift Register

Address Register

and Counter

Y Decoder

High Voltage

Generator

Data

Register

Status

Block
Protect

16 Bytes

X Decoder

AI01272

3/16

ST95P08

T able 3. AC Measurement Conditions

Figure 4. AC Testing Input Output Waveforms

Input Rise and Fall Times ≤ 50ns

0.8V

0.2V

CC

CC

Input Pulse Voltages 0.2V
Input and Output Timing

Reference Voltages

Note that Output Hi-Z is defined as the point where data is no
longer driven.

T able 4. Input Parameters

(1)

(TA = 25 °C, f = 1 MHz )

0.3V

to 0.8V

CC

to 0.7V

CC

CC

CC

Symbol Parameter Min Max Unit

C

IN

C

IN

t

LPF

Note:

1. Sampled only, not 100% tested.

Input Capacitance (D) 8 pF
Input Capacitance (other pins) 6 pF
Input Signal Pulse Width 10 ns

Tabl e 5. DC Characteristics

(T

= 0 to 70°C or –40 to 85°C; VCC = 3V to 5.5V)

A

0.7V

0.3V

AI00825

CC

CC

Symbol Parameter Test Condition Min Max Unit

I

LI

I

LO

I

CC

I

CC1

V

IL

V

IH

V

OL

V

OH

Input Leakage Current 2 µA
Output Leakage Current ±2 µA

VCC Supply Current (Active)

C = 0.1 V

@ 2 MHz, Q = Open

S = VCC, VIN = VSS or VCC,

VCC Supply Current (Standby)

S = VCC, VIN = VSS or VCC,

Input Low Voltage – 0.3 0.3 V
Input High Voltage 0.7 V
Output Low Voltage IOL = 2mA 0.2 V
Output High Voltage IOH = –2mA 0.8 V

V

V

= 5.5V

CC

CC

/0.9 VCC ,

CC

= 3V

CC

CC

2mA

50 µA

10 µA

CC

V

VCC + 1 V

CC

V
V

4/16

ST95P08

Table 6. AC Characteristics

(T

= 0 to 70°C or –40 to 85°C; VCC = 3V to 5.5V)

A

Symbol Alt Parameter Test Condition Min Max Unit

f

C

t

SLCH

t

CLSH

t

CH

t

CL

t

CLCH

t

CHCL

t

DVCH

t

CHDX

t

DLDH

t

DHDL

t

HXCH

t

CLHX

t

SHSL

t

SHQZ

t

QVCL

t

CLQX

t

QLQH

t

QHQL

t

HHQX

t

HLQZ

(1)

t

W

Note:

1. Not enough characterisation data were availa ble on this parameter at the time of issue this Data Sheet. The typical value is well
below 5ms, the maximum value will be reviewed and lowered when sufficient data is available.

t

t
t
t

t

t

t

DSU

t

t

t

HSU

t

t

t

t
t

t

t

t

f

SU

SH

WH

WL

RC

FC

DH

t

HH

CS

DIS

t

HO

RO

FO

HZ

t

C

Clock Frequency D.C. 2 MHz
S Setup Time 50 ns
S Hold Time 50 ns
Clock High Time 200 ns
Clock Low Time 300 ns
Clock Rise Time 1 µs
Clock Fall Time 1 µs
Data In Setup Time 50 ns
Data In Hold Time 50 ns

RI

FI

Data In Rise Time 1 µs
Data In Fall Time 1 µs
HOLD Setup Time 50 ns
HOLD Hold Time 50 ns

S Deselect Time

4.5V < V
3V < V

< 5.5V 200 ns

CC

< 4.5V 250 ns

CC

Output Disable Time 150 ns

V

Clock Low to Output Valid 300 ns
Output Hold Time 0 ns
Output Rise Time 100 ns
Output Fall Time 100 ns

LZ

HOLD High to Output Low-Z 150 ns
HOLD Low to Output High-Z 150 ns

W

Write Cycle Time 10 ms

5/16