SGS Thomson Microelectronics ST52E420, ST52T420, ST52T410 Datasheet
®
E420
8-BIT INTELLIGENT CONTROLLER UNIT (ICU)
Memories
Upto4KbytesOTP
128 bytes of RAM
Readout Protection
Core
Register File Based Architecture
55 instructions
Hardware multiplication and division
Decision Processor for the implement ation of
Fuzzy Logic algorithms
Clock and Power Supply
Up to 20 M H z clock frequency.
Power Saving features
ST52T410/T420/
ST52T410/T420/E420
Three Timer/PWMs, ADC, WDG
PRELIMINARY DATASHEET
Interrupts
Up to 5 interrupt vec tors
Top Level External Interrupt (INT)
I/O Ports
19 I/O PINs configurable in Input and Output
mode
High current sink/source in all pins.
Peripherals
3Programmable 8-bit Tim er/PWM s withinternal
16-bit Prescaler featuring:
– PWM output
– Input capture
– Output compare
– Pulse generator mode
On-chip 8-bit Sam ple and Hold A/D C onv erter
with 8-channel analog multiplexer (ST52T420/
E420 only)
Watchdog timer
Development tools
High level Software tools
Emulator
Low cost Programmer
Gang Programme r
Rev. 1.6 - November 2002 1/84
ST52T410/T420/E420
ST52T410/ST52x420 Device Summ ary
Device NVM RAM
ST52T420G0py 1K OTP 128 3x8-bit 8-Ch - Yes 3.0-5.5 V 19 Dip/So 28
ST52T420G1py 2K OTP 128 3x8-bit 8-Ch - Y es 3.0-5.5 V 19 Dip/So 28
ST52T420G2py 4K OTP 128 3x8-bit 8-Ch - Y es 3.0-5.5 V 19 Dip/So 28
ST52E420G2D6 4K EPROM 128 3x8-bit 8-Ch - Yes 3.0-5.5 V 19 Cdip 28
ST52T410G0py 1K OTP 128 3x8-bit - Yes 2.7-5.5 V 19 Dip/So 28
ST52T410G1py 2K OTP 128 3x8-bit - Yes 2.7-5.5 V 19 Dip/So 28
ST52T410G2py 4K OTP 128 3x8-bit - Yes 2.7-5.5 V 19 Dip/So 28
Timers
PWM
ADC SCI Watchdog
Operating
Supply
I/O Package
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ST52T410/T420/E420
TABLE OF CONTENTS
TABLE OF CONTENTS
1GENERALDESCRIPTION......................................... 7
1.1Introduction...................................................................7
1.2 Functional Desc ript ion . .........................................................7
1.2.1MemoryProgrammingMode................................................ 7
1.2.2Workingmode............................................................ 8
1.3PinDescription...............................................................12
2INTERNALARCHITECTURE...................................... 15
2.1 ST52T410/ST5 2x420 Operating M odes . ...........................................15
2.2ControlUnitandDataProcessingUnit.............................................15
2.2.1ProgramCounter ........................................................ 15
2.2.2Flags.................................................................. 15
2.3AddressSpaces..............................................................17
2.3.1RAMandSTACK........................................................ 17
2.3.2 Input Registers Bench . . . ................................................. 18
2.3.3ConfigurationRegisters ................................................... 19
2.3.4OutputRegisters......................................................... 20
2.4 Arithmetic Logic Unit. . . ........................................................21
3EPROM....................................................... 24
3.1EPROMProgrammingPhaseProcedure...........................................25
3.1.1EPROMOperation....................................................... 26
3.1.2EPROMLocking......................................................... 26
3.1.3EPROMWriting ......................................................... 26
3.1.4EPROMRead/VerifyMarginMode........................................... 27
3.1.5StandbyMode.......................................................... 27
3.1.6IDcode................................................................ 27
3.2EpromErasure...............................................................27
4INTERRUPTS.................................................. 28
4.1InterruptOperation............................................................28
4.2 Global Interrupt Request Enabling ................................................28
4.3InterruptSources.............................................................29
4.4 Interrupt Maskability . . . ........................................................29
4.5InterruptPriority..............................................................31
4.6InterruptsandLowpowermode..................................................33
4.7InterruptRESET..............................................................33
5CLOCK,RESET&POWERSAVINGMODE.......................... 34
5.1SystemClock................................................................34
5.2 RESET .....................................................................34
5.3PowerSavingMode...........................................................34
5.3.1WaitMode.............................................................. 34
5.3.2HaltMode.............................................................. 35
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ST52T410/T420/E420
6FUZZYCOMPUTATION(DP)...................................... 37
6.1FuzzyInference ..............................................................37
6.2FuzzyficationPhase...........................................................37
6.3InferencePhase..............................................................37
6.4 Defuzzyfication . ..............................................................38
6.5 Input Members hip Function . . . ..................................................38
6.6OutputSingleton..............................................................39
6.7FuzzyRules .................................................................39
7I/OPORTS.................................................... 41
7.1Introduction..................................................................41
7.2 Input Mode ..................................................................41
7.3OutputMode.................................................................42
7.4AlternateFunctions............................................................42
7.5I/OPortConfigurationRegisters..................................................43
8A/DCONVERTER(ST52X420ONLY)............................... 47
8.1Introduction..................................................................47
8.2 Operational Description ........................................................47
8.2.1OperatingModes........................................................ 48
8.2.2PowerDownMode....................................................... 49
8.3A/DRegistersDescription.......................................................49
9WATCHDOGTIMER............................................. 50
9.1 Operational Description ........................................................50
9.2RegisterDescription...........................................................51
10PWM/TIMER.................................................. 52
10.1TimerMode.................................................................52
10.2PWMMode.................................................................54
10.3TimerInterrupt ..............................................................55
11ELECTRICALCHARACTERISTICS ............................... 66
11.1ParameterConditions.........................................................66
11.1.1MinimumandMaximumvalues............................................ 66
11.1.2Typicalvalues.......................................................... 66
11.1.3Typicalcurves.......................................................... 66
11.1.4 Loading c apac it or ....................................................... 66
11.1.5Pininputvoltage........................................................ 66
11.2AbsoluteMaximumRatings ....................................................66
11.3 Recommended Operating Condition. . . ...........................................68
11.4SupplyCurrentCharacteristics..................................................69
11.5ClockandTimingCharacteristics................................................71
11.6MemoryCharacteristics .......................................................72
11.7ESDPinProtectionStrategy....................................................73
11.7.1 Standard Pi n Protection . ................................................. 73
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ST52T410/T420/E420
11.7.2 Multi-supply C onfiguration ................................................ 74
11.8PortPinCharacteristics .......................................................75
11.8.1 General Charact eristics . ................................................. 75
11.9ControlPinCharacteristics.....................................................78
11.9.1 RESET pin ............................................................ 78
11.9.2VPPpin............................................................... 78
11.108-bitA/DCharacteristics......................................................79
ORDERINGINFORMATION........................................ 83
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ST52T410/T420/E420
6/84
ST52T410/T420/E420
1 GENERAL DESCRIPTION
1.1 Introduction
ST52T4 10/ST52x420 are 8- bit Intelligent Control
Units (ICU) of t he ST Five Family, which can
perform both boolean and fuzzy algorithms i n an
efficient manner, in order to reach the best
performances that the t wo methodologies allow.
ST52T410/ ST52x420 are produced b y
STMicroelectronics using the reliable high
performance CMOS process, including integratedon-chip peripherals that allow maximization of
system reliability , decreasin g system costs and
minimizing the nu mber of external components.
The fle xible I/O c onfigu ration of ST 52x4 00/440
allows for an interface with a wide range of external
devices, like D/A converters or power control
devices.
ST52T410/ST52x420 pins are configurable,
allowing the user to set the input or output signals
on each single pin.
A hardware multiplier (8 b it by 8 bit with 16 bi t
result) and a divide r (16 bit over 8 bit with 8 bit
result and 8 bit remainder) are available to
implement complex fu nctions by usi ng a single
instruction. The program memory utilization and
computational speed is optimized.
Fuzzy Logic dedicated structures in ST52T410/
ST52x420 ICU’s can be exploited to model
complex systems with high accuracy in a useful
and easy way.
Fuzzy Expert Systems for overall system
management and fuzzy Real time Controls can be
designed to increase performa nces at highly
competitive costs.
The linguistic approach characterizing Fuzzy Logic
is based on a set of IF-THEN rules, which describe
the control behavior, as well as on Membership
Functions, w hich are associated to input and
output variables.
Up to 334 Member ship Functions, with triangular
and trapezoidal shapes, or singleton values are
available to describe fuzzy variables.
The Timer/PW M peripheral allows the
management of power devices and timing signals,
implementing different operating modes and high
frequency PWM (Pulse With Modulation) controls.
Input Capture an d Output Compare f unc tions are
available on the TIMER.
The programmable Timer has a 16 bit Internal
Prescaler and an 8 bit Counter. It can use internal
or external Start/Stop signals and clock.
An internal prog rammable Watchdog is ava il able
to avoid loop errors and to reset the ICU.
ST52x420 includes an 8-bit Analog to Digital
Converter with an 8-analog channel Multiplexer.
Single/Multiple channels and Single/Sequence
conversion modes are supported.
In order to optimize energy consumption, two
different power saving modes are availabl e: Wait
mode and Halt mode.
Program Memory (EPROM/O TP) addressing
capability addresses up to 8 K bytes of memory
locations to store both program instructions and
permanent data.
EPROM can be locked by the user to prevent
external undesired operations.
Operations may be performed on data stored in
RAM, allowing the direct combination of new input
and feedback data. All bytes of RAM are used like
Register File.
OTP (One Time Programmable) v ersion devices
are fully compatible with t he EPROM windowed
version, which m ay be used for prototyping and
pre-production phases of development.
A powerful d ev elopment env ironment c ons isting of
a board a nd software too ls allows an easy
configuration and us e of ST52T410/ST52x420.
TM
TheVISUALFIVE
software tool al lows
development of projects through a user-friendly
graphical interface and optimization of generated
code.
1.2 Functional Description
ST52T410/ST52x420 ICUs can work in two
modes:
■ Memory Programming Mode
■ Working Mode
according to RESET and Vpp signals levels (see
pins description).
Note: When RESET=0 it is advisable n o t to use
the sequence “101010“ to port P A (7 : 2).
1.2.1 Memory Programming Mode.
The ST52T410/ST52x420 memory is loaded in the
Memory Programming Phas e. All fuzzy and
standard instructions are written inside the
memory.
This phase starts by setting the control signals as
illustrated below:
RESET
V
ss
TEST V
V
ss
12V/V
PP
DD
7/84
ST52T410/T420/E420
When this phase starts, the ST52T410/ST52x420
core are set to RESET status; then 12V are applied
to the Vpp pin in order t o start EPRO M
programming. A signal app lied to PB1 is used to
increment the m emory address; the da ta is
supplied to PORT A (see EPROM programming for
further details).
1.2.2 Working mode.
Below are the cont ro l signals of this mode:
RESET TEST V
V
DD
V
SS
PP
V
SS
The processor sta rts the working phase following
the instructions, whic h have been previousl y
loaded in the memory.
ST52T410/ST52x 420’s internal struct ure includes
a computational block, CO NTROL UNIT (CU) /
DATA PROCESSIN G UNIT (DPU), which allows
Figure 1.1 ST52x420 SO28 Pin Configuration
proces sing of boolean f unctions and fuz zy
algorithms.
The CU/DPU can m anage up to 334 different
Membership Functions for the f uzzy rules
antecedent part. The rule consequents are “crisp”
values (real numbers). The maxim um number of
rules that can be defined is limited by the
dimens ions of the i mplemented stan dard
algorithm.
EPROM is then sh ared betw een fuzzy and
standard algorithms. The Membership Function
data is stored inside the first 1024 mem ory
locations. The Fuzzy rules are parts of the program
instructions.
The Control Unit (CU) reads the information and
the status deriving from the peripherals.
Arithmetic calculus can be performed on these
values by using the internal CU and the 128 bytes
of RAM, which supports all computations. The
peripheral input c an be fuz zy and/or arithmetic
output, or the values contained in Data RAM and
EPROM locations.
RESET
OSCOUT
OSCIN
TEST
INT/PC0
T0OUT/PC1
T1OUT/PC2
T2OUT/PC3
Ain0/PB0
Ain1/PB1
Ain2/PB2
Ain3/PB3
V
DDA
GNDA
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SO28
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
VSS
VPP
PA0/T0RES
PA1/T0OUT
PA2/T1OUT
PA3/T2OUT
PA4/T0STRT
PA5/T0CLK
PA6
PA7/PB7/Ain7
PB6/Ain6
PB5/Ain5
PB4/Ain4
8/84
Figure 1.2 ST52x420 PDIP28 Pin Configuration
ST52T410/T420/E420
RESET
OSCOUT
OSCIN
TEST
INT/PC0
T0OUT/PC1
T1OUT/PC2
T2OUT/PC3
Ain0/PB0
Ain1/PB1
Ain2/PB2
Ain3/PB3
DDA
V
GNDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Figure 1.3 ST52T410 SO28 Pin Configuration
PDIP28
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
VSS
VPP
PA0/T0RES
PA1/T0OUT
PA2/T1OUT
PA3/T2OUT
PA4/T0STRT
PA5/T0CLK
PA6
PA7/PB7/Ain7
PB6/Ain6
PB5/Ain5
PB4/Ain4
RESET
OSCOUT
OSCIN
TEST
INT/PC0
T0OUT/PC1
T1OUT/PC2
T2OUT/PC3
PB0
PB1
PB2
PB3
V
DDA
GNDA
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SO28
V
28
27
VSS
26
VPP
25
PA0/T0RES
24
PA1/T0OUT
23
PA2/T1OUT
22
PA3/T2OUT
21
PA4/T0STRT
20
PA5/T0CLK
19
PA6
18
PA7/PB7
17
PB6
16
15
PB5
PB4
9/84
ST52T410/T420/E420
Figure 1.4 ST52410 PDIP28 Pin Configuration
RESET
OSCOUT
OSCIN
TEST
INT/PC0
T0OUT/PC1
T1OUT/PC2
T2OUT/PC3
PB0
PB1
PB2
PB3
V
DDA
GNDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PDIP28
VDD
28
27
VSS
26
VPP
25
24
23
22
21
20
19
18
17
16
15
PA0/T0RES
PA1/T0OUT
PA2/T1OUT
PA3/T2OUT
PA4/T0STRT
PA5/T0CLK
PA6
PA7/PB7
PB6
PB5
PB4
10/84
Table 1.1 ST52T410/ST52x420 SO28 & PDIP28 Pin list
ST52T410/T420/E420
SO28
Pins
1 RESET
NAME Programming Phase Working Phase
General Reset General Reset
2 OSCOUT Oscillator Output
3 OSCIN Oscillator Input
4 TEST Must be tied to V
ss Must be tied to Vss
5 INT/PC0 PHASE signal (PHASE) External interrupt, Digital I/O
6 T0OUT/PC1 Timer/PWM 0 output, Digital I/O
7 T1OUT/PC2 Timer/PWM 1 output, Digital I/O
8 T2OUT/PC3 Timer/PWM 2 output, Digital I/O
9 Ain0/PB0 Address Reset (RST_ADD) Analog Input (*), Digital I/O
10 Ain1/PB1 Address Increment (INC_ADD) Analog Input (*), Digital I/O
11 Ain2/PB2 Configuration Reset (RST_CONF) Analog Input (*), Digital I/O
12 Ain3/PB3 Configuration Increment Analog Input (*), Digital I/O
13 V
DDA Analog Power Supply Analog Power Supply (*)
14 GNDA Analog Ground Analog Ground (*)
15 Ain4/PB4 Analog Input (*), Digital I/O
16 Ain5/PB5 Analog Input (*), Digital I/O
17 Ain6/PB6 Analog Input (*), Digital I/O
18 Ain7/PB7/PA7 I/O EPROM Data Analog Input (*), Digital I/O
19 PA6 I/O EPROM Data Digital I/O
20 T0CLK/PA5 I/O EPROM Data Timer/PWM 0 clock, Digital I/O
21 T0STRT/PA4 I/O EPROM Data Timer/PWM 0 start/stop, Digital I/O
22 T2OUT
/PA3 I/O EPROM Data
23 T1OUT/PA2 I/OEPROM Data
24 T0OUT/PA1 I/OEPROM Data
Timer/PWM 2 compl. output, Digital I/O
Timer/PWM 1 compl. output, Digital I/O
Timer/PWM 0 compl. output, Digital I/O
25 T0RES/PA0 I/O EPROM Data Timer/PWM 0 Reset, Digital I/O
26 V
PP
EPROM Programming Power
supply (12V ± 5%)
EPROM VDD or Vss
27 V
28 V
(*) ST52x420 only
ss Digital Ground Digital Ground
DD Digital Power Supply Digital Power Supply
11/84
ST52T410/T420/E420
1.3 Pin Description
V
DD
, VSS, V
, GNDA, VPP. In order to avoid
DDA
noise disturbances, t he power supply of the digital
part is kept separate from t he power s upply of the
analog part.
Main Power Supply Voltage (5V± 10%).
V
DD.
In t he ST52x410 version the two VDDpins must be
connected togheter.
VSS. Digital circuit ground.
In the ST52x410 version the two VSSpins must be
connected togheter.
V
.AnalogVDDoftheAnalogtoDigital
DDA
Converter.
GNDA. Analog V
Converter. Must be tied to V
of the Analog to Digital
SS
SS
.
VPP. Ma in Power Supply for internal EPRO M
(12.5V±5%, in programming phase) and Operating
MODE selector. During the Programming phase
(programming), V
Working phase V
must be set at 12V. In the
PP
must be equal to VSS.
PP
OSCin and OSCout. Th ese pins are i nte rnally
connect ed with the on-chip osci llato r circuit . A
quartz crystal or a ceram ic resonator can be
connected between these two pins in order to allow
the correct operations of ST52T410/ST52x420
with various s tability/cost t rade-off. An external
clock signal can be applied to OSC in, in this case
OSCout must be floating.
RESET. This signal is used to restart ST52T410/
ST52x420 at the begi nning of its program and to
select the program mode for EPROM.
Ain0-Ain7. Thes e 8 lines are connec ted to the
input of the analog multiplex er. They allow the
acquisition of 8 analog input (ST52x420 only).
During th e Programming phase, Ain0, Ain1, Ain2
and Ain3 are used to manage EPROM operation.
PA0-PA7, PB0-PB7, PC0-PC3. These lines are
organized as I/O port. Each pin can be co nfi gured
as input or output. PA7/P B7 are tied to the same
output. During Programming phas e PA port is used
for EPROM read/write data.
T0RES, T0CLK, T0STRT. These pins are related
with the internal Programmable Timer/PWM 0.
This Timer can be reset externally by using
T0RES. In Working Mode, T0RES resets the
address counter of the Timer. T0RES is active at
low level.
TheTimer0Clockcanbetheinternalclockorcan
be supplied externally by using pin T0CLK.
An external Start/Stop signal can be used to
control the Timer t hrough T0STRT pin .
T0OUT, T1OUT, T2OUT. The TIMER/PWM
outputs are availa ble on these pin s.
T0OUT
, T1OUT, T2OUT.TheTIMER/PWM
complementary outputs are available on these
pins.
TEST. During the Programming and Working
phase it must be set to Vss.
INT. This pin is used to start t he External Interrupt
routine.
12/84
Figure 1.5 ST52X420 Block Diagram
ST52T410/T420/E420
PROGRAM
MEMORY
EPROM
CORE
INTERRUPTS
CONTROLLER
ALU &
DPU
DECISION
PROCESSOR
CONTROL
UNIT
RegisterFile
128 bytes
Input
registers
TIMER/PWM 0
TIMER/PWM 1
TIMER/PWM 2
PORT A
PORT C
PORT B
ADC
PA7:0
PC3:0
PB7:0
VDDA
GNDA
PC FLAGS
POWER SUPPLY OSCILLATOR
VDD VPP VSS OSCIN OSCOUT RESET
WATCHDOG
RESET CIRCUIT
13/84
ST52T410/T420/E420
Figure 1.6 ST52X410 Block Diagram
PROGR AM
MEMORY
EPROM
CORE
INTERRUPTS
CONTROLL ER
ALU &
DPU
TIMER/PWM 0
TIMER/PWM 1
TIMER/PWM 2
PORT A
PA7:0
DECISION
PROCESSOR
CONTROL
UNIT
Regist erFile
128 bytes
Input
registers
PORT C
PORT B
WATCHDOG
PC FLAGS
POWER SUPPLY OSCILLATOR
VDD VPP VSS OSCIN OSCOUT RESET
RESET CIRCUIT
PC3:0
PB7:0
14/84
ST52T410/ST52T420/E420
2 INTERNAL ARCHITECTURE
ST52T410/ST52x420 are made up of the f ollowing
blocks and peripherals:
■ Control Unit (CU) and Data Processing Unit
(DPU)
■ ALU / Fuzzy Co re
■ EPROM
■ 128 Byte RAM
■ Clock Oscillator
■ Analog Multiplexer and A/D Converter
(ST52x420 only)
■ 3PWM/Timers
■ Digital I/O port
2.1 ST52T410/ST52x420 O perating Modes
ST52T410/ST52x420 works in two modes ,
Programming and Working Modes, depending on
the control signals level RESET, TEST and V
PP
The Operating modes are selec ted by setting the
control signal level as specified in the Control
Signals Setting table.
Table 2.1 Control Signals Setting
Control
Signal
RESET V
TEST VSS
VPP 12 V
Pro-
gramming
SS VSS VDD
Reset Working
VSS VSS
SS VSS
V
2.2 Con trol Unit and Data P rocessing Unit
The Control Unit (CU) formally includes five main
blocks. Each blo ck decodes a set of instructions,
generating the appropriate control signals. The
main parts of the CU are illustrated in Figure 2.1.
The five different parts of the CU manage Loading,
Logic/Arithmetic, Jump, Control and the Fuzzy
instruction set.
The block called “Collector” manages the signals
deriving from the different parts of t he CU, defining
the signals for the Data P roc essi ng Unit (DPU) and
the different peripherals of the microcontroller.
The block called “Arbiter” manages the different-
parts of the CU so that only one part of the system
is activated during working mode.
The CU structure is ve ry flexible. It was designed
with the purpose of e asily adapting the c ore of the
microcontroller to market needs. New instruction
sets or new peripherals can be easily included
without changing the structure of the
microcontroller, maintaining c ode compatibility.
The CU reads the instructions stored on EPR OM
(Fetch) and decodes them. According to the
instruction types, the arbiter activates one of the
main blocks of the CU. A fterwards, all the cont rol
signals for the DPU are ge nerated.
A set of 46 different arithmetic, fuzzy and logic
instructions is available. Each instruction r equires
6(fuzzyinstructions)to26(DIVISION)clock
pulses to be performed.
The DPU receives, stores and s ends instructions
deriving from EPROM, RA M or peri pherals in order
to execute t hem.
2.2.1 Program Counter.
The Program Counter (PC) is a 12-bit register that
contains the address of the next memory location
to be proc es s ed by the core. This memory location
may be a n opcode, operand, or an address of an
operand.
The 12-bit length allows direct addressing of a
maximum of 4,096 bytes in t he program spac e.
After having read the c urrent instruction a ddres s,
the PC value is incremented. The result of this
operation is shifted back into the PC.
The PC can be changed in the following ways:
■ JP (Jump)PC = Jump Address
■ InterruptPC = Interrupt Vector
■ RETIPC = Pop (stack)
■ RETPC = Pop (stack)
■ CALLPC = Subroutines address
■ ResetPC = Reset Vector
■ Normal InstructionPC = PC + 1
2.2.2 Fla gs.
The ST52T 410/ ST 52x 420 core i nc ludes a different set of flags that correspond to 2 different
modes: normal mode and interrupt mode. Each
set of flags consists o f a CARRY flag (C), ZE RO
flag (Z) and SIGN flag (S).
One set (CN, ZN, SN) is used during norm al
operation and one is used during interrupt mode
(CI, ZI, SI). Formally, the user has to manage
only one set of flags: C, Z and S.
15/84
ST52T410/ST52T420/E420
Figure 2.1 Data Processing Unit (DPU)
Figure 2 .2 CU/DP U Block Diagram
16/84
ST52T410/ST52T420/E420
The ST5 2T410/ST52x420 core uses flags that
correspond to the actual mode. As soon as an
interrupt is generated t he ST52T410/ST52x420
core uses the interrupt flags instead of the normal
flags.
Each interrupt lev el has its own set of flags, which
is saved in the STACK together with the Program
Counter. These flags are restored from the STACK
automatically when a RE TI ins truct ion is executed.
Ifthe MCU was in norma l mode before aninterrupt,
the normal flags are restored when the RETI
instruction is executed.
Note:
A CALL subroutine is a normal mode
execution. For this reason, a RET instruction,
consequent to a CALL instruction does not affect
the normal m ode set of flags.
Flags are not cleared during context switching and
remain in the state they were at the end of the last
interrupt routine switching.
The Carry flag is set when an overflow occurs
during arithmetic operations, otherwise it is
cleared.
The Sign flag is set when an underflow occurs
during arithmetic operations, otherwise it is
cleared.
2.3 Address Spaces
ST52T410/ST52x420 has four separat e address
spaces:
Figure 2.3 Address Spaces Description
■ RAM: 128 Bytes
■ Input Registers: 18 8-bit registers
■ Output Registers 9 8-bit registers
■ Configuration Registers: 17 8-bit registers
■ Programmemory up to 4K Bytes
Program memory will be described in further
details in the M EMORY section
2.3.1 RAM and STACK.
RAM memory consists of 128 general purpose 8bit RAM registers.
All the registers in RAM can be specified by using
a decimal address. For example, 0 identifies the
first register of RAM.
To read or write RAM registers LOAD instructions
must be used. See Table 2.5
Each interrupt level has its own set of flags, which
is saved in the STACK together with the Program
Counter. These flags are restored from th e STACK
automatically when a RETI instruction is executed.
When the instructions like Interrupt request or
CALL are executed, a STACK level is used to push
the PC.
The STACK is located in RAM. For each level of
stack, 2 bytes of RAM are use d. The v alues of this
stack are stored from the last RAM register
(address 127). The maximum level of stack
must be less than 128.
17/84
ST52T410/ST52T420/E420
The STACK POINTER indicates the first level
available to store data. When a subroutine c all o r
interrupt request occurs, the content of the PC and
the current s et of flags are stored into the level
locatedby the STACK POINTER.
When a interrupt return occ urs (RETI instruction),
the data stored in the highest stack level is
restored back into the PC and current flags.
Instead, when a subrout ine return occurs (RET
instruction) the data stored in the highest st ac k
level are restored in the PC not affecting the flags.
These operating modes are illustrated in Figure
2.4.
The user must pay clos e attention to avoid
Note:
overwritingRAM locations where the STACK could
be stored
.
2.3.2 Input Registers Bench.
The Input Registers (IR) bench consists of 18 8-bit
registers containing data or the status of the
peripherals.
Figure 2.4 S tack Operation
All t he registers can be specified by using a
decimal address (for example, 0 identifies the first
register of the IR).
The assembler instruction:
LDRI RAM_Reg. IR_i
loads the value of the i-th I R in the RAM location
identified by the RAM_Reg address.
The first inpu t register is dedicated to s tore the
value of th e stack pointer. The next 8 reg isters
(ADC_OUT_0:7) of the IR are dedicated to the 8
converted values d eriving f rom the ADC
(ST52x420 only). The last 9 Input Registers
contain data from the I/O ports and PWM/Timers.
The following table summarizes t he IR address
and the relative peripherals. In order to simplify the
concept, a mnemonic name is assigned to the
registers. The same name is used in
VISUALSTUDIO
®
development tools
18/84
ST52T410/ST52T420/E420
Table 2.2 Input Registers
IR MNEMONIC NAME PERIPHERAL REGISTER ADDRESS
STACK_POINTER STACK POINTER 0
CHAN 0 (*) A/D CHANNEL 0 (*) 1
CHAN 1 (*) A/D CHANNEL 1 (*) 2
CHAN 2 (*) A/D CHANNEL 2 (*) 3
CHAN 3 (*) A/D CHANNEL 3 (*) 4
CHAN 4 (*) A/D CHANNEL 4 (*) 5
CHAN 5 (*) A/D CHANNEL 5 (*) 6
CHAN 6 (*) A/D CHANNEL 6 (*) 7
CHAN 7 (*) A/D CHANNEL 7 (*) 8
PORT_A PORT A INPUT REGISTER 9
PORT_B PORT B INPUT REGISTER 10
PORT_C PORT C INPUT REGISTER 11
PWM_ 0_COUNT PWM/TIMER 0 COUNTER 12
PWM_ 0_ STATUS PWM/TIMER 0 STATUS REGISTER 13
PWM_ 1_ COUNT PWM/TIMER 1 COUNTER 14
PWM_ 1_ STATUS PWM/TIMER 1 STATUS REGISTER 15
PWM_ 2_ COUNT PWM/TIMER 2 COUNTER 16
PWM_ 2_ STATUS PWM/TIMER 2 STATUS REGISTER 17
2.3.3 Configuration Registers.
The ST52T410/ST52x420 con figurati on R egisters
allow the configuration of all the blocks of the fuzzy
microcontroller. Table 2.3 describes the functions
and the related peripherals of each of the
instructions, the Configuration Registers can be
set by using values stored in the Program Memory
(EPROM) or in RAM.
Use and meaning of eac h register will be described
in further details in the corresponding sec tion.
Configuration Registers. By using the load
Table 2.3 Configuration Registers
CONFIGURATION REGISTER PERIPHERAL DESCRIPTION
REG_CONF 0 INTERRUPT MASK Interrupts mask setting
REG_CONF 1 INTERRUPT PRIORITY INTERRUPT PRIORITY
REG_CONF 2 WATCHDOG TIMER Watchdog Timer Configuration
REG_CONF 3 (*) A/D CONVERTER A/D configuration
REG_CONF 4 PORT A
Set the relative bit like digital input
or digital output
19/84
ST52T410/ST52T420/E420
Table 2.3 Configuration Registers (continued)
CONFIGURATION REGISTER PERIPHERAL DESCRIPTION
REG_CONF 5 PWM/TIMER 0
REG_CONF 6 PWM/TIMER 0
REG_CONF 7 PWM/TIMER 0
REG_CONF 8 PWM/TIMER 1
REG_CONF 9 PWM/TIMER 1
REG_CONF 10 PWM/TIMER 2
REG_CONF 11 PWM/TIMER 2
REG_CONF 12 PORT A
REG_CONF 13 PORT B
REG_CONF 14 PORT B
PWM/Timer 0 Working mode
Configuration
PWM/TIMER 0 Prescaler
configuration and output waveform
selection.
PWM/TIMER 0 Working Mode
Configuration
PWM/TIMER 1 Working Mode
Configuration
PWM/TIMER 1 Prescaler
configuration and output waveform
selection.
PWM/TIMER 2 Working Mode
Configuration
PWM/Timer 2 Prescaler
configuration and output waveform
selection.
Set the bit 0,1 and 2 like Digital I/O
or complementary Timers Output.
Set the relative bit like digital input
or digital output.
Set the relative I/O like Digital or
Analog (*).
REG_CONF 15 PORT C
REG_CONF 16 PORT C
(*) ST52x420 only
2.3.4 Output Registers.
The Out put Registers (OR) c ons ist of 9 registers
containing data f or the microcontroller peripherals
including the I/O Port s.
All registers can be specified by using a decimal
address (for example, 1 identifies the second OR).
By using LOAD instructions the Output Regist ers
(OR) may be set by using values stored in the
Program Memory (LDPE) or in RAM (LDP R)
The assembler instruction:
LDPR OR_i RAM_Reg.
Set the relative I/O like digital input
Set the relative I/O like Digital I/O
or digital output
or Timers Output
loads the value of the RAM location identified by
theaddressRAM_RegintheORi-thTable2.4
describes OR.
In order to simplify the concep t, a mnemonic name
is assigned to OR. The same names are us ed in
VISUALFIVE
TM
5.0 development tools.
Use and meaning of eac h register will be described
in further details in the corresponding sec tion.
20/84
ST52T410/ST52T420/E420
Table 2.4 Output Registers
OR MNEMONIC NAME PERIPHERAL REGISTER ADDRESS
PORT_ A PORT A OR 0
PORT_ B PORT B OR 1
PORT_C PORT C OR 2
PWM_0_COUNT TIMER/PWM 0 COUNTER 3
PWM_0_RELOAD TIMER/PWM 0 RELOAD REGISTER 4
PWM_1_COUNT TIMER/PWM 1 COUNTER 5
PWM_1_RELOAD TIMER/PWM 1 RELOAD REGISTER 6
PWM_ 2_ COUNT TIMER/PWM 2 COUNTER 7
PWM_2_RELOAD TIMER/PWM 2 RELOAD REGISTER 8
2.4 Ari thmetic Logic Unit
The 8-bit Arithmetic Logic Unit (ALU) allows the
performance of arithmetic c alculations and logic
instructions, which can be divided into 5 groups:
Load, Arithmetic, Jump, Interrupts and Program
Control instructions (ref er to the ST52T4 10/
ST52x420 Assembler S et for further details).
The ALU of the ST52T410/ST52x420 can perform
multiplication (MULT) and division (DI V).
Multiplication is performed by using 8 bit operands
storing the resu lt in 2 registers (16 bit values), see
Figure 2.5 and Figure 2.6.
WARNING 1: The current page register value
set with the PGSET instruction is lost after a
jump, call, or an interrupt jump.
The computational time required for each
instruction consists of one clock pulse for each
Cycle plus 3 clock pulses for the decoding phase.
WARNING 2: If the LSB of the multiplication
result is 0, the Zero flag is set alth ough the
result is not 0.
Table 2.5 Load instructions
Load Instructions
Mnemonic Instruction Bytes Cycles Z S C
LDCE LDCE conf, EPROM 3 17 - - -
LDCR LDCR conf, RAM 3 14 - - -
LDFR LDFR FUZZY_i_RAM RAM 3 14 - - -
LDPE LDPE per, EPROM 3 17 - - -
LDPE LDPE per, (RAM) 3 17 - - -
LDPR LDPR reg, RAM 3 14 - - -
LDRC LDRC RAM, const 3 14 - - -
LDRE LDRE RAMi, EPROMi 3 16 - - -
LDRE LDRE (RAMi), (RAMj) 3 18 - - -
21/84
ST52T410/ST52T420/E420
Table 2.5 Load instructions
LDRI LDRI RAM, inp_reg 3 15 - - -
LDRR LDRR RAMi, RAMj 3 16 - - -
PGSET PGSET const 2 9 - - -
Table 2.6 Arithmetic & Logic instructions set
Arithmetic Instructions
Mnemonic Instruction Bytes Cycles Z S C
ADD ADD regi, regj 3 17 I - I
ADDO ADDO regi, regj 3 20 I I I
AND AND regi, regj 3 17 I - -
ASL ASL regi 2 15 I - I
ASR ASR regi 2 15 I I DEC DEC regi 2 15 I I -
DIV DIV regi, regj 3 26 I I I
INC INC regi 2 15 I - I
MULT MULT regi, regj 3 19 I - -
NOT NOT regi 2 15 I - -
OR OR regi, regj 3 17 I - -
SUB SUB regi, regj 3 17 I I -
SUBO SUBO regi, regj 3 20 I I I
MIRROR MIRROR regi 2 15 I - -
Table 2.7 Jump I nstruction Set
Jump instructions
mnemonic instruction bytes cycles z s c
CALL CALL addr 3 18 - - -
JP JP addr 3 12 - - -
JPC JPC addr 3 10/12 - - -
JPNC JPNC addr 3 10/12 - - JPNS JPNS addr 3 10/12 - - -
JPNZ JPNZ addr 3 10/12 - - -
JPS JPS addr 3 10/12 - - -
JPZ JPZ addr 3 10/12 - - RET RET 1 13 - - -
22/84
ST52T410/ST52T420/E420
Table 2.8 Interrupt Instructions Set
Interrupt Instructions
Mnemonic Instruction Bytes Cycles Z S C
HALT HALT 1 7/15 - - MEGI MEGI 1 7/15 - - -
MDGI MDGI 1 6 - - -
RETI RETI 1 12 - - -
RINT RINT INT 2 8 - - -
UDGI UDGI 1 6 - - -
UEGI UEGI 1 7/15 - - -
WAITI WAITI 1 7/14 - - -
Table 2.9 Control Instructions Set
Control Instructions
Mnemonic Instruction Bytes Cycles Z S C
FUZZY FUZZY 1 5 - - -
NOP NOP 1 6 ---
WDTRFR WDTRFR 1 7 - - -
WDTSLP WDTSLP 1 6 - - -
Notes:
I affected
- not affected
Figure 2.5 Multiplication Figure 2.6 Division
23/84
ST52T410/ST52T420/E430
3 EPROM
EPROM memory provides an on-chip userprogrammable non-volatile m emory, which allows
fast and reliable storage of user data.
EPROM memory c an be locked by the user. In
fact, a memo ry location called Lock Cell i s devoted
to lock EPROM and avoid external operations. A
software identification code, called ID CODE,
distinguishes which software version is stored i n
the memory.
32 kbits of memory s pac e with an 8-bit internal
parallelism (up to 4 kbytes) addressed by a 12-bit
bus are available. The data bus is 8 bits.
Memory has a double supply: V
12V±5% in Programming Phase or to V
Working Phase. V
is equal to 5V± 10% .
DD
is equal to
PP
SS
during
ST52T410/ST52x42 0 EPROM memory is divided
into three main blocks (see Figure ):
■
Interrupt Vectors memory block
(3 through 17)
contains the addresses for the interrupt routines.
Each address is composed of three bytes.
Figure 3.1 Program Memory Organization
■
Mbfs Setting memory block
MemAdd
) contains the coordinates of t he
(18 through
vertexes of every Mbf defined in the program.
■ The maximum value of MemAdd is 1023. This
area is dynamica lly assigned according to the
size of the fuzzy routines. The unused memory
area, if any, is assigned to the Program
Instruction Set memory block.
■ The Program Instructions Set memory block
(MemAdd through 4095) c onta ins theinstruction
set of the us er program.
Locations 0, 1 and 2 contain the address of the first
microcode instruction.The operations that can be
performed o n EPROM during the Program ming
Phase are: Stand By, Memory Writing, Reading
and Verify/Margin Mode, Memory Lock, IDCode
Writing and Verify.
24/84
Table 3.1 EPROM Control Register
VER
GINMODE
D
A
V
ALIDDATAVA
LIDDAT
A
T
A
OUT
OPERATION REGISTER VALUE
Stand By 0
Memory Reading/Verify 1
ST52T410/ST52T420/E430
The operations above are managed by using the
internal 4-bit EPROM Control Register. The
reading phase isexecuted withV
the verify/Margin Mode phase needs V
12V±5%. The Blank Check mus t be a r eading
operation with V
=5V±5%.
PP
Table 3.1 illustrates EPROM Control Register
codes used to identify the operation running.
=5V±5%, while
PP
PP
=
Memory Unlock and
Lock Status Reading
2
Memory Writing 3
Memory Lock 4
ID CODE Writing 5
Memory Lock Status
Reading/Verify
ID CODE Reading/
Verify
9
10
Figure 3.2 Eprom Programming Timing
PA(0:7)
OUT
RST_ADD
3.1 EPROM Pr ogramming Phase Procedure
The Programming mod e is selected by applying
12V±5% voltage or 5V±5% voltage to t he V
PP
pin
and setting the control signal as following:
RESET =Vss
TEST =Vss
If the V
performed.
voltage is 5V ± 5% only readi ng may be
PP
RST_ADD, INC_ADD, RST_CONF, INC_CONF
and PHA S E are the control s ignals used during the
Programming Mode.
PHASE, RST_CONF and RST_ADD signals are
active on level, the others are active on rising
edge.
VALID
DATA
TA
DATA
IN
DA
DATA
OUT
RST_CONF
INC_ADD
INC_CONF
PHASE
MEMORY UNLOCK
100nS
MEMORY WRITING
LOCATION ADDRESS =1
10
S
µ
MEMORY
MAR
IFY
25/84
ST52T410/ST52T420/E430
PHASE and RST_ADD signals are active low,
RST_CONF signal is ac tive high.
Port A is us ed for the memory data I/O.
(See Tab le
3.1 for pin reference onthe different packages)
Memory may be locked by means of the M emory
Lock Status, which is a flag used to enable
EPROM operations.
If Memory Lock Status is 1 all EPROM operation s
are enabled, otherwise the user may only read
(and verify) the OTP code and the Memory Lock
Status.
Only if E PROM is not locked by means of Lock Cell
(see EPROM Locking may EPROM operations be
enabled by changing the Memory Lock Status from
0to1.
RST_ADD signal resets t he memory address
register and the Memory Lock Status. W hen the
RST_ADD becomes high, the memory must be
unlocked in order to read or write.
INC_ADD signal increments the memory address.
RST_CONF signal resets the EPROM Control
Register. When RST_CONF is high, the DATA I/
O Port A is in outpu t, otherwise it is always i n
input.
INC_CONF signa l increments the EPROM Control
Register value.
PHASE signal validates the operation selected by
means of the EPROM Control R egister value.
3.1.1 EP ROM Operati on.
In order to execute an EPROM operation (See
Table 3.1), the corresponding identification value
must be loaded in the EPROM Control Register.
The s ignal timing is the following: RST_ADD= high
and PHASE= high, RST_CONF changes from low
to high lev el, to reset the EPRO M Control Register,
and INC_CONF signal g enerates a number of
positive pulses equal to the value to be loaded.
After this sequence, a negative pulse of the
PHASE signal will validate the operat ion selected.
The minimum PHASE s ignal pulse wi dth must be
10 µs for EPROM Writing Operation and 100 ns for
the others.
When RST_CONF is high, DATA I/O P ort A is
enabled in output and the reading/verifying
operation results are available.
Aftera writing operat ion, when RST_CONF is high,
Port A is in output without valid data.
3.1.2 EPROM Locking.
The Memory Lock operation, which is ident if ied
with the num ber 4 in the EPROM Control Register,
.
writes “0" in the Memory Lock Cell.
At the beginning of an E xternal Operat ion, when
the R ST_ADD signal changes from low level to
high level, the Memory Lock Stat us is “0", therefore
it must be unlocked before proceeding.
In order to unlock the M emory Lock Status the
operation, which is identified by the number 2 in
the EPROM Control Register must be executed
(see Figure 3.2).
Memory Lock Status can be changed only if
Memory Lock Cel l is “1". After a Memory Lock
operation external operations cannot be ex ec uted
except to read (or verify) the OTP Code and t he
Memory Lock Status.
3.1.3 EPROM Writing.
When the memory is blank, all bits are at logic level
“1". Data is introduced by programming only the
zeros in the desired memory location. However, all
input data mu st contain both ”1" and “0".
The only w ay to c hange “0" into ”1" is t o erase the
entire memory (by exposure to Ultra Violet light)
and reprogram it.
The memo ry is in Writing m ode when the EPROM
Control Register value is 3.
TheV
voltage must be 12V±5%, with stable data
PP
on the dat a bus PA(0:7).
The timing signals are the following (see Figure ):
1) RST_ADD and RST_CONF change from low to
high level,
2) two pulses on INC_CONF signal load the
Memory Unlock operation code,
3) a negative pulse (100 ns ) on the PHASE signal
validates the Memory Unlock o peration,
4) a negative pulse on RST_CONF signal resets
the EPROM Control Register,
5) three positive pulses on INC_CONF load the
Memory Writing operation code,
6) a train of positive pulses on INC_ADD signal
increments the memory location addres s up to the
requested value (generally this is a sequential
operation and only one pulse is used),
7) a negative pulse (10 µ s ) on the PHASE signal
validates the Memory Writing operation.
26/84
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