SGS Thomson Microelectronics ST5080A Datasheet

PROGRAMMABLE ISDN AUDIO FRONT END

FEATURES: Comp leteCODECandFILT ERsyst emin clud in g :

PCM ANALOG TO DIGITAL AND DIGITALTO ANALOGCONVERTERS

POWERFUL ANALOG FRONT END CAPABLE TO INTERFACE DIRECTLY:

- Microphone Dynamic, Piezo or Electrete

- Earpiece down to 100Ω or up to 150nF

- Loudspeakerdown to 50Ω or Buzzer up to 600nF.

TRANSMIT BAND-PASSFILTER ACTIVERC NOISE FILTER RECEIVE LOW-PASS FILTER WITH SIN X/X

CORRECTION MU-LAW OR A-LAW SELECTABLE COM-

PANDINGCODERAND DECODER PRECISIONVOLTAGE REFERENCE

ST5080A

PIAFE

ADVANCE DATA

SO28

ORDERING NUMBER: ST5080D

Phones Features:

DUAL SWITCHABLE MICROPHONE AMPLIFIER INPUTS. GAIN PROGRAMMABLE: 15 dBRANGE, 1 dB STEP.

LOUDSPEAKER AMPLIFIER AUXILIARY OUTPUT. ATTENUATION PROGRAMMABLE: 30 dBRANGE, 2 dB STEP.

SEPARATEEARPIECEAMPLIFIER OUTPUT. ATTENUATION PROGRAMMABLE: 15 dB RANGE, 1 dB STEP

AUXILIARY SWITCHABLE EXTERNAL RING INPUT (EAIN).

TRANSIENT SUPRESSION SIGNAL DURING POWERON.

INTERNAL PROGRAMMABLE SIDETONE CIRCUIT. ATTENUATIONPROGRAMMABLE: 15 dBRANGE, 1 dB STEP.

INTERNAL RING OR TONE GENERATORINCLUDING DTMF TONES, SINEWAVE OR SQUAREWAVE WAVEFORMS. ATTENUATION PROGRAMMABLE: 27 dB RANGE, 3 dB STEP.

COMPATIBLE WITH HANDS-FREE CIRCUIT TEA7540.

ON CHIP SWITCHABLE ANTI-ACOUSTIC FEED-BACKCIRCUIT (ANTI-LARSEN).

GeneralFeatures:

EXTENDED TEMPERATURE RANGE OPERATION(*) –40°C TO+85°C.

EXTEN D EDPOWERSUPPLY RANGE5V±10%. 60 mW OPERATINGPOWER (TYPICAL).

1.0 mW STANDBY POWER(TYPICAL). CMOSDIGITAL INTERFACES. SINGLE+ 5V SUPPLY. DIGITALLOOPBACKTEST MODE. PROGRAMMABLE DIGITAL AND CONTROL

INTERFACES:

–Digital PCM Interface associated with

separate serial Control Interface MICROWIRE compatible.

–GCI interface compatible.

(*) Functionalityguaranteed in the range – 40°C to +85°C;

Timing and Electrical Specifications are guaranteed in the range

–25°Cto+85°C.

APPLICATIONS:

ISDN TERMINALS. DIGITALTELEPHONES CT2 AND GSMAPPLICATIONS

December 1994

This isadvanced information on anew productnow in development or undergoing evaluation. Details are subject to change without notice.

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ST5080A

PIN CONNECTIONS (Topview)

BLOCK DIAGRAM

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TYPICALISDN TELEPHONE SET APPLICATION

ST5080A

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ST5080A

GENERALDESCRIPTION

ST5080APIAFE is a combined PCM CODEC/FILTERdeviceoptimizedfor ISDNTerminalsand Digital Telephone applications. This device is A-law and Mu-law selectableand offersa numberof programmable functions accessed through a serial control channel. Depending on mode selected, channel control is provided by means of a separate serial channel control MICROWIRE compatible or multiplexed with the PCM voice data channel in a GCI compatible format requiring only 4 digital interface pins. When separate serial control interface is selected, PCM interface is compatible with Combo I and Combo II families of devices such as ETC5057/54,TS5070/71. PIAFE is built using SGS-THOMSON’s advanced HCMOSprocess. Transmitsection of PIAFEconsistsof an amplifier with switchable high impedance inputs followed by a programmable gain amplifier, an active RC antialiasingpre-filter to provide attenuationof high frequency noise, an 8th order switched capacitor band pass transmit filter and an A-law/Mu-law selectablecompandigencoder. Receive section consist of an A-law/Mu-law selectable expanding decoder which reconstructs the analog sampled data signal, a 3400 Hz low pass filter with sin X/X correction followed by two

separate programmable attenuation blocks and two power amplifiers: One can be used to drive an earpiece, and the other to drive a 50 Ω loudspeaker. Programmable functions on PIAFE include a Ring/Tone generator which provides one or two tones and can be directed to earpiece or to loudspeaker or alternatively a piezo transducer up to 600nF. A separate programmable gain amplifier allows gain control of the signal injected. Ring/Tone generator provides sinewave or squarewave signal with precise frequencies which may be also directed to the input of the Transmit amplifier for DTMFtone generation. An auxiliary analog input (EAIN) is also provided to enable for example the output of an external band limited Ring signal to the Loudspeaker. Transmit signal may be fed back into the receive ampifier with a programmableattenuation to providea sidetone circuitry. A switchable anti-accoustic feed-back system cancelsthe larsen effect in speech monitoringapplication. Two additional pins are provided for insertion of an external Handfree function in the Loudspeaker receive path. An output latch controlled by register programmingpermitsexternal device control.

PIN FUNCTIONS

Pin Name Description

1,2 HFI, HFO Hands free I/Os:

3,4 V

6,7 LS-,LS+ Receive analog loudspeaker amplifier complementary outputs,

Fr+,VFr–

These two pins can be used to insert an external Handfree circuit such as the TEA 7540 in the receive path. HFO is an output which provides the signal issued from output of the receive low pass filterwhile HFI is a high impendance input which is connected directly to one ofthe inputs of the Loudspeaker amplifier.

Receive analog earpiece amplifier complementary outputs, capable of driving load impedances between 100and 400 Ω or a piezoup to 150nF. These outputs can drive directly earpiece transductor. The signal at this output can drive be the summ of:

- Receive Speech signal from D

- Internal Tone Generator,

- Sidetone signal. Positive power supply input for the digital section.

+5 V + 10%.

intended for driving a Loudspeaker: 80 mW on 50Ω load impedance can be provided at low distorsion meeting specifications. Alternatively this stage can drive a piezo transducer up to 600nF. The signal at these outputs can be the sum of:

- Receive Speech signal from D

- Internal Tone generator,

- External input signal from EAIN input.

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PIN FUNCTIONS (continued)

Pin Name Description

9 MS Mode Select: This input selects COMBO I/II interface mode

10 D

11 N.C. No Connected. 14 D

15 FS Frame Sync input: This signal is a 8kHz clock which defines

16 MCLK Master Clock Input: This signalis used by the switched

17 LO Open drain output:

18 N.C. No Connected. 21 MIC2+ Alternative positive high impedance input to transmit pre-

22 MIC1+ Positive high impedance input to transmit pre-amplifier for

23 MIC1- Negative high impedance input to transmit pre-amplifier for

24 N.C. No connected. 25 V

CCA

26 MIC2- Alternative negative high impedance input to transmit pre-

27 GNDA Analog Ground: All analog signals are referenced to this pin.

28 EAIN External Auxiliary input: This input can be used to provide

with separate MICROWIRE Control interface when tied high and GCImode when tied low.

Transmit Data ouput: Data is shifted out on this pin during the assigned transmit time slots. Elsewhere D

output is in the high

impendance state. In COMBO I/II mode, voice data byte is shifted out from TRISTATE output D

at the MCLK frequency

on the rising edge of MCLK. In GCI mode, voice data byte and control bytes are shifted out from OPEN-DRAIN output D half the MCLK. An external pull up resistor isneeded.

Receive data input: Data is shifted induring the assigned Received time slots. In the COMBO I/IImode, voice data byte is shifted in at the MCLK frequency on the falling edges of MCLK. In the GCI mode, PCM data byte and contol byte are shifted in at halfthe MCLK frequency on the receive rising edges of MCLK. There is one period delay between transmit rising edge and receive rising edge of MCLK.

the start of the transmit and receive frames. Eitherof three formats may be used for this signal: non delayed timing mode, delayed timing and GCI compatible timing mode.

capacitor filters and the encoder/decoder sequencing logic. Values must be 512 kHz, 1.536 MHz, 2.048 MHz or 2.56 MHz selected by means of ControlRegister CRO. MCLK is used also to shift-in and out data. In GCI mode, 2.56 MHz and 512 kHz are not allowed.

a logic1 writteninto DO (CR1) appears at LO pin as a logic 0 a logic0 writteninto DO puts LO pin in high impedance.

amplifier.

microphone symetricalconnection.

Positive power supply input for the analog section.

+5 V + 10% . V

and V

must be directly connected

CCA

together.

amplifier.

GND and GNDA must be connectedtogether close to the device.

alternate signals to the Loudspeaker in placeof Internal Ring generator. Input signal shouldbe voice band limited.

ST5080A

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ST5080A

Following pin definitions are used only when COMBO I/II mode with separate MICROWIRE compatible serial control port is selected. (MS input set equal one)

PIN FUNCTIONS (continued)

Pin Name Description

12 CO Control data Output: Serial control/status information is shifted

13 CI Control data Input: Serial Control information is shifted into the

19 CCLK Control Clock input: This clock shifts serial control information

20 CS- Chip Select input: When this pin is low, control information is

Followingpin definitions are used only when the GCI mode is selected. (MS input set equal zero)

out from the PIAFE on this pin when CS- is low on the falling odges of CCLK.

PIAFE on this pin when CS- is low on the rising edges of CCLK.

into CI and out from CO when the CS- input is low, depending on the current instruction. CCLK may be asynchronous with the other system clocks.

written into and out from the PIAFE via CI and CO pins.

PIN FUNCTIONS (continued)

Pin Name Description

19,13,12,20 A0,A1,A2,A3 These pins select the address of PIAFE on GCI interface and

must be hardwired to either V C4,C5,C6,C7 bits of the first address byte respectively.

or GND. A0,A1,A2,A3 refer to

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ST5080A

FUNCTIONALDESCRIPTION Power on initialization:

When power is first applied, power on reset cicuitryinitializes PIAFE and puts it into the power down state. Gain Control Registersfor the various programmable gain amplifiersand programmable switches are initialized as indicated in the Control Registerdescription section.All CODEC functions are disabled. Digital Interface is configured in GCI modeor in COMBOI/II mode dependingon Mode Selectpin connection. The desired selection for all programmable functions may be intialized prior to a power up command using Monitor channel in GCI mode or MICROWIREport in COMBOI/II mode.

Power up/downcontrol:

Following power-on initialization, power up and powerdown controlmay be accomplishedby writing any of the controlinstructions listed in Table 1 into PIAFE with ”P” bit set to 0 for power up or 1 for powerdown. Normally, it is recommended that all programmable functions be initially programmed while the device is powered down. Power state control can then be included with the last programming instruction or in a separatesingle byte instruction. Any of the programmable registers may also be modified while ST5080A is powered up or down by setting ”P” bit as indicated. When power up or down control is entered as a single byte instruction, bit 1 must be setto a 0. When a power up command is given, all de-activated circuits are activated, but output D

will re-

main in the high impedancestate on B time slots until the second Fspulse after power up,even ifa B channelis selected.

Power downstate:

Following a period of activity, power down state may be reentered by writing a power down instruction. ControlRegistersremain in theircurrent state and canbe changed either by MICROWIRE control interface or GCI control channel depending on modeselected. In addition to the power down instruction, detection of loss MCLK (no transition detected) automaticallyenters the device in ”reset” power down state with D

output in the high impedance state

and L0in high impedance state.

Transmitsection:

Transmit analog interface is designed in two stages to enablegains up to 35 dB tobe realized. Stage 1 is a lownoise differentialamplifier providing 20 dB gain. A microphone may be capacitevely connected to MIC1+, MIC1- inputs,

while the MIC2+ MIC2– inputs may be used to capacitively connect a second microphone (for digital handsfree operation) or an auxiliary audio circuitsuch as TEA 7540 Hands-free circuit. MIC1 or MIC2 source is selected with bit 7 of register CR4. Following the first stage is a programmable gain amplifier which provides from 0 to 15 dB of additional gain in 1 dB step. The total transmit gain should be adjusted so that, at reference point A, see Block Diagram description, the internal 0 dBmO voltage is 0.739 V (overload level is 1.06 Vrms). Second stage amplifier can be programmed with bits 4 to 7 of CR5. To temporarily mute the transmit input, bitTE (6of CR4) maybe set low. In this case, the analog transmit signal is grounded and the sidetone path is alsodisabled. An active RC prefilter then precedes the 8th order band pass switched capacitor filter. A/D converter has a compressing characteristic according to CCITT A or mu255 coding laws, which must be selected by setting bits MA, IA in register CR0. A precisionon chip voltagereferenceensures accurateand highly stable transmissionlevels. Anyoffset voltagearising in the gain-setamplifier, the filters or the comparatoris cancelled by an internalautozero circuit. Each encode cycle begins immediatly at the beginningof theselected Transmittime slot. The total signal delay referenced to the start of the time slotis approximatively195 µs (due to the transmit filter) plus 123 µs (due to encoding delay), which totals 320 µs. Voice data isshifted out on D

during the selected time slot on the transmit rising adgesof MCLK.

Receivesection:

Voice Data is shifted into the decoder’s Receive voice data Register via the D

pin during the se-

lected time slot on the8 receive edges of MCLK. The decoder consists of an expanding DAC with either A or MU255 law decoding characteristic which is selected by the same control instruction used to select the Encode law during intitialization. Following the Decoder is a 3400 Hz 6th order low pass switchedcapacitor filter withintegral SinX/X correctionfor the8 kHzsample and hold. 0 dBmO voltage at this (B) reference point (see Block Diagram description) is 0.49 Vrms. A transcient suppressing circuitry ensure interference noisesuppressionat power up. The analog speech signal output can be routed either to earpiece(V

FR+,VFR-

outputs) or to loudspeaker (LS+, LS- outputs) by setting bits SL and SE(1 and 0 of CR4). Total signal delay is approximatively190 µs (filter plus decoding delay) plus 62.5 µs (1/2 frame) whichgives approximatively252 µs. Differential outputs V

FR+,VFR-

are intendedto di-

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ST5080A

rectly drive an earpiece. Precedingthe outputs is a programmableattenuationamplifier,which must be set by writing to bits 4 to 7 in register CR6. Attenuations in the range 0 to -15 dB relative to the maximum level in 1 dB step can be programmed. The input of this programmable amplifier is the summ of several signals which can be selected by writing to registerCR4.:

- Receive speech signal which has been decodedand filtered,

- Internally generated tone signal, (Tone amplitude is programmed with bits 4 to 7 ofregister CR7),

- Sidetonesignal, the amplitude of which is programmedwith bits 0 to 3 of registerCR5

FR+

andV

outputsarecapableof drivingoutput

FR-

power level up to 14mW into differentially connectedloadimpedancebetween100 and 400Ω.

Differential outputs LS+,LS- are intended to directlydrive a Loudspeaker.Precedingthe outputs is a programmable attenuation amplifier, which must be set by writing to bits 0 to 3 in register CR6. Attenuationsin the range 0 to -30 dB relative to the maximum level in 2.0 dB step can be programmed.The input of this programmable amplifier can be the summ of signals which can be selectedby writing to register CR4:

- Receive speech signal which has been decodedand filtered,

- Internally generated tone signal, (Tone amplitude is programmed with bits 4 to 7 ofregister CR7),

- EAIN input which may be an alternate Ring signal or any voice frequency band limited signal. (An external decoupling capacitor of about0.1µF is necessary).

Receive voice signal may be directed to output HFO by means of bit HFE in Register CR4. After processing,signal must be re-entered through input HFI to Loudspeakeramplifierinput. (An external decoupling capacitor of about 0.1µF is necessary). LS+and LS- outputsare capable of driving output power level up to 80 mW into 50 Ω differentially connectedload impedanceat low distortion meeting PCM channel specifications. When the signal source is a Ring squarewave signal, power levels up to approximatively200 mW can bedelivered.

Anti-acoustic feed-back for loudspeaker to handset microphone loop with squelch effect: on chip switchable anti-larsen for loudspeaker to handset microphone feedback is implemented. A 12dB depth gain control on both transmit and receive path is provided to keep constant the loop gain. On the transmit path the 12dB gain control is provided starting from the CR5 transmit gain definition; at the same time, on the receive path the 12dB gain control is provided starting from CR6

receive gain definition.

Digitaland Control Interface:

PIAFE provides a choice of either of two types of DigitalInterfacefor both control data and PCM. For compatibility with systemswhichuse time slot oriented PCM busses with a separate Control Interface, as used on COMBO I/II families of devices, PIAFE functions are described in next section. Alternatively,for systems in which PCM and control data are multiplexed together using GCI interface scheme, PIAFE functions are described in the section following the next one. PIAFE will automatically switch to one of these two types of interface by sensing the MS pin. Due to Line Transceiverclock recovery circuitry, a low jitter may be provided on F clocks. F

and MCLK must be always in phase.

and MCLK

For ST5421S Transceiver, as an example, maximun value of jitter amplitude is a step of 65 ns at each GCI frame (125µs). So, the maximum jitteramplitude is 130 ns pk-pk.

COMBOI/II mode. Digital Interface (Fig. 1)

Frame Sync input determines the beginningof

frame. It may have any duration from a single cycle of MCLK to a squarewave. Two differentrelationships may be established between the Frame Sync input and the first time slot of frame by settingbit 3 in register CR0. Non delayed data mode is similar to long frame timing on ETC5057/ TS5070 series of devices (COMBO I and COMBO II respectively): first time slot begins nominally coincident with the rising edge of F

Alternativeis to use delayed data mode, which is similar to short framesync timing on COMBO I or COMBOII, in which F

input must be high at least

a half cycle of MCLK earlier the frame beginning. A time slot assignment circuit on chip may be used with both timingmodes, allowing connection to one of the two B1 and B2 voice data channels. Two data formats are available: in Format 1, time slot B1 corresponds to the 8 MCLK cycles following immediately the rising edge of FS, while time slot B2 corresponds to the 8 MCLK cycles following immediatelytime slot B1. In Format 2, time slot B1 is identical to Format1. Time slot B2 appears two bit slots after time slot B1. This two bits space is left available for insertionof the D channeldata. Data format is selected by bit FF (2) in register CR0. Time slot B1 or B2 is selected by bit T0 (0) in ControlRegister CR1. Bit EN (2) in control register CR1 enables or disables the voice data transfer on D

and DRas

appropriate. During the assigned time slot, D

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Figure1: DigitalInterface Format

ST5080A

Figure2: GCI InterfaceFrame Structure

output shifts data out from the voice data register on the rising edges of MCLK. Serialvoice data is shifted into D

input during the same time slot on

the falling edges of MCLK. D

is in the high impedance Tristate condition

when in the non selectedtime slots.

ControlInterface:

Control informationor data is written into or readback from PIAFE via the serial control port consisting of control clock CCLK, serial data input CI and output CO, and Chip Select input, CS-. All controlinstructions require 2 bytes as listedin Ta-

ble 1, with the exception of a single byte powerup/downcommand. To shift control data into ST5080A, CCLK must be pulsed high 8 times while CS- is low. Data on CI input is shifted into the serial input register on the rising edge of each CCLK pulse. After all data is shifted in, the content of the input shift register is decoded, and may indicate that a 2nd byte of control data will follow. This second byte may either be defined by a second byte-wide CSpulse or may follow the first contiguously,i.e. it is not mandatory for CS- to return high in between the first and second control bytes. At the end of

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ST5080A

the 2nd control byte, data is loaded into the appropriate programmable register. CS- must return high at the end of the 2ndbyte. To read-back status information from PIAFE, the first byte of the appropriate instruction is strobed in during the first CS- pulse, as defined in Table

1. CS- must be set low for a further 8 CCLK cycles, during which data is shifted out of the CO pin on the falling edgesof CCLK. When CS- is high, CO pin is in the high impedance Tri-state, enabling CO pins of several devices to be multiplexedtogether. Thus, to summarise, 2 byte READand WRITE instructions may use either two 8-bit wide CSpulses or a single16 bitwide CS-pulse.

Controlchannel access to PCM interface:

It is possible to access the B channel previously selectedin RegisterCR1. A byte written into Control Register CR3 will be automatically transmitted from D

output in the

followingframe in place of the transmit PCMdata. A byte written into Control Register CR2 will be automaticallysent through the receivepath to the Receiveamplifiers. In order to implement a continuousdata flow from the Control MICROWIRE interface to a B channel, it is necessary to send the control byte on eachPCM frame. A current byte received on D

input can be read

in the register CR2. In order to implement a continuous data flow from a B channel to MICROWIREinterface,it is necessaryto read register CR2at each PCM frame.

GCI COMPATIBLE MODE

GCI interface is an European standardized interface to connect ISDN dedicated components in the different configurations of equipment as Terminals,Network Terminations,PBX,etc... In a Terminal equipment, this interface called SCIT for Special Circuit Interface for Terminals allows for example connection between:

- ST5421 (SID-GCI) and ST5451 (HDLC/GCI controller)used for 16 kbit/s D channel packet framesprocessingand SIDcontrol,

- Peripheral devices connected to a 64 kbit/s B channel and ST5451 used for GCI peripheral control.

ST5080A may be assignedto one of the B channels present on the GCI interface and is monitored via a control channel which is multiplexed with the 64 kbit/sVoice Datachannels.

Figure 2 shows the frame structure at the GCI interface.Two 256 kbit/s channel are supported.

a)GCI channel 0: It is structured in four sub-

channels:

–B1 channel8 bits per frame

–B2 channel8 bits per frame –M channel8 bits per frameignored byPIAFE –SC channel 8 bits per frame ignored by

PIAFE Only B1 or B2 channelcan be selectedin PIAFEfor PCM data transfer.

b)GCI channel 1: It is structured also in four

subchannels:

–B1* channel8 bits per frame –B2* channel8 bits per frame –M* channel8 bits per frame

–SC* which is structured as follows: 6 bits ignored by PIAFE A* bit associated with M* channel E* bit associated with M* channel.

B1* or B2* channelcan be selectedin PIAFE for PCM data transfer. M* channeland two associatedbits E* and A* are used for PIAFE control.

Thus, to summarize, B1, B2, B1* or B2* channel can be selected to transmit PCM data and M* channelis used toread/write status/commandperipheral device registers. Protocol for byte exchangeon the M* channel uses E* and A* bits.

PhysicalInterface

Theinterface is physicallyconstitued with 4 wires: InputData wire: D OutputData wire: D

R X

Bit Clock: MCLK Frame Synchronization: F

Data is synchronized by MCLK and FSclock inputs.

insures reinitialization of time slot counter at

each frame beginning. The rising edge or FS is the reference time for the first GCI channelbit. Data is transmitted in both directions at half the MCLK input frequency. Data is transmitted on the the rising edge of MCLK and is sampled one period after the transmitrising edge, also on a rising edge. Note: Transmit data may be sampled by far-end device ie SID ST5421on the falling edge 1.5 periodafter the transmitrisingedge. Unused channel are high impedance. Data outputs are OPEN-DRAINand need an external pull up resistor.

COMBOactivation/deactivation

ST5080A is automatically set in power down modewhen GCIclocks are idle. GCI section is reactivatedwhen GCI clocks are detected. PIAFE is completly reactivated after receiving of a power up command.

Exchangeprotocol on M* channel

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