SGS Thomson Microelectronics ST25W01, ST25C01, ST24W01, ST24C01 Datasheet

1 MILLION ERASE /WRI T E CYCLES with 40 YEARS DATA RETENTION

SINGL E SUPPLY VOLTAGE: – 3V to 5.5V for ST24x01 versions – 2.5V to 5.5V for ST25x01 versions – 1.8V to 5.5V for ST24C01R version only HARDWARE WRITE CONTROL VERSIONS:

ST24W01 and ST25W01 TWO WIRE SERIAL INTERFACE, FULLY I2C

BUS COMPATIBLE BYTE and MULTIBYTE WRITE (up to 4

BYTES) PAGE WRITE (up to 8 BYTES) BYTE, RANDOM and SEQ UE NTIA L READ

MODES SELF TIME D PRO G RA MM ING CY C LE AUTOMATIC ADDRESS INCREMENTING ENHANCED ESD /LATCH UP

PERFORMA NCES

ST24C/W01 are replaced by the M24C01 ST25C/W01 are replaced by the M24C01-W ST24C01R is replaced by the M24C01-R

DESCRIP TION

This specification cov ers a range of 1K bits I

C bus EEPROM products, the ST24/25C01, the ST24C01R and the ST24/ 25W01. In the tex t, products are referred to as ST24/25x01, where "x" is: "C" for Standard version and "W" for hardware Write Control version.

T able 1. Signal Names

ST24/25C01, ST24C01R

ST24/25W01

SERIAL 1K (128 x 8) EEPROM

NOT FOR NEW DESIGN

PSDIP8 (B)

0.25mm Frame

Figure 1. Logic Diag ra m

E0-E2 SDA

ST24x01

SCL

MODE/WC*

ST25x01

ST24C01R

SO8 (M)

150mil Width

E0-E2 Chip Enable Inputs SDA Serial Data Address Input/Output SCL Serial Clock

MODE WC Write Control (W version)

November 1997 1/16

This is information on a product still in production but not recommended for new design

Multibyte/Page Write Mode (C version)

Supply Voltage Ground

Note: WC signal is only available for ST24/25W01 products.

AI00839D

ST24/25C01, ST24C01R, ST24/25W01

Figure 2A. DIP Pin Connect io ns

ST24x01 ST25x01

ST24C01R

E0 V

2 3

T ab le 2. Absolut e Maximu m Ra t ings

Symbol Parameter Value Unit

STG

LEAD

Ambient Operating Temperature –40 to 125 °C

Storage Temperature –65 to 150 °C Lead Temperature, Soldering (SO8 package)

8 7 6 5

AI00840D

MODE/WCE1 SCL SDAV

(1)

(PSDIP8 package)

Figure 2B. SO Pin Connecti ons

ST24x01 ST25x01

ST24C01R

E0 V

1 2

40 sec 10 sec

3 4

8 7 6 5

AI00841E

215 260

MODE/WCE1 SCL SDAV

°C

ESD

Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"

DESCRIP TION (co nt’d)

The ST24/25x01 are 1K bit electrically erasable programmable memories (EEPROM), organized as 128 x 8 bits. They are manufactured in SGSTHOMSON’s Hi-Endurance Advanced CMOS technology which guarantees an endurance of one million erase/write cycles with a data retention of 40 years. The memories operate with a power supply value as low as 1.8V for the ST24C01R only .

Both Plastic Dual- in-Line and Plastic Small Out line packages are available.

The memories are compatible with the I

Input or Output Voltages –0.6 to 6.5 V

Supply Voltage –0.3 to 6.5 V

Electrostatic Discharge Voltage (Human Body model) Electrostatic Discharge Voltage (Machine model)

may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicat ed in the Operati ng sections of this specific ati on is not implied. Expos ure to Absolut e Maximum Rating conditions for extended periods may affect device rel i abi lity. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents.

2. MIL-STD-883C, 3015.7 (100pF, 1500 Ω).

3. EIAJ IC-121 (Condition C) (200pF, 0 Ω).

(2)

(3)

4000 V

500 V

tional data bus and serial clock. The memories carry a built-in 4 bit, unique device identification code (1010) corresponding to the I

C bus definition. This is used t ogether with 3 chip enable inputs (E2, E1, E0) so that up to 8 x 1K devices may be attached to the I

C bus and selected individually. The memories behave as a s lave devic e in the I protocol with all memory operations synchronized by the serial clock. Read and write operations are initiated by a START condition generated by the bus master . The START condition is followed by a stream of 7 bits (identification code 1010), plus one

C stand-

read/write bit and terminated by an acknowledge bit.

ard, two wire serial interface whic h uses a bi- direc-

2/16

ST24/25C01, ST24C01R, ST24/25W01

T ab le 3. Device Select Co de

Device Code Chip Enable RW

Bit b7 b6 b5 b4 b3 b2 b1 b0 Device Select 1 0 1 0 E2 E1 E0 R

Note: The MSB b7 is sent first.

T ab le 4. Operating Modes

Mode RW bit MODE Bytes Initial Sequence

Current Address Read ’1’ X 1 START, Device Select, R

Random Address Read

Sequential Read ’1’ X 1 to 128 Similar to Current or Random Mode Byte Write ’0’ X 1 START, Device Select, R Multibyte Write Page Write ’0’ V

Notes: 1. X = VIH or V

2. Multibyte Write not available in ST24/25W01 versions.

(2)

When writing data to the mem ory it responds to th e 8 bits received by asserting an acknowledge bit during the 9th bit time. When data is read by the bus master , it acknowledges the receipt of the data bytes in the same way. Data transfers are terminated with a STOP condition.

Power On Reset: V

order to prevent data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is implemented. Until the V voltage has reached the POR threshold v alue, th e internal reset is active, all operations are disabled and the device will not respond to any command. In the same way, when V operating voltage to below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable V must be applied before applying any logic signal.

SIGNAL DES CRIPTIONS Serial Clock (SCL). The SCL input pin is used to

synchronize all data in and out of the memory. A resistor can be connected from the SCL line to V to act as a pull up (see Figure 3).

(1)

’0’ ’1’ reSTART, Device Select, R

’0’ V

4 START, Device Select, RW = ’0’ 8 START, Device Select, RW = ’0’

START, Device Select, R

Serial Data (SDA). The SDA pin is bi-directional and is used to transfer data in or out of the memory . It is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A res istor must be connected from the SDA

to act as pull up (see Figure 3).

lock out write protect. In

bus line to V Chip Enable (E0 - E2). These chip enable inputs

are used to set the 3 least significant bits (b3, b2, b1) of the 7 bit device select code. These inputs

may be driven dynamically or t ied to VCC or VSS to establish the device select code.

Mode (MO DE). T he MODE input is available on pin

drops down from the

7 (see also cally. It must be at V mode, V

WC feature) and may be driven dynami-

for Multibyte Write mode or VIL for Page

Write mode. When unconnected, the MODE input

is internally read as V

Write Control (

feature (

WC) is offered only for ST24W01 and

WC). An hardware Write Control

ST25W01 versions on pin 7. This feature is usefull to protect the contents of the memory from any erroneous erase/write cy cle. The W rite Control s ig-

nal is used to enable ( V

) the internal write protection. When uncon-

nected, the

WC input is internally read as VIL and

W = ’1’ W = ’0’, Address,

W = ’1’

W = ’0’

or VIH for the Byte Write

(Multibyte Writ e mode) .

WC = VIH) or disable (WC =

the memory area is not write protected.

3/16

ST24/25C01, ST24C01R, ST24/25W01

SIGNAL DESCRIPTION (cont’d)

The devices with this Write Control feature no longer support the Multibyte Write mode of operation, however all other write modes are fully supported.

Refer to the AN404 Application Note for more detailed information about Write Contr ol feature.

DEVICE OPER ATION

C Bus Background

The ST24/25x01 support the I2C protocol. This protocol defines any device that sends data onto the bus as a transmitter and any device t hat reads the data as a receiver . The device that c ontrols th e data transfer is known as the master and the other as the slave. The master will alway s initiate a dat a transfer and will provide the serial clock for synchronisation. The ST24/25x01 are always slave devices in all communications.

Start Condition. START is identified by a high to low transition of the SDA line while the clock SCL is stable in the high state. A START condition must precede any command for data transfer. Except during a programming cycle, the ST24/25x01 continuously monitor the SDA and SCL signals for a START condition and will not respond unless one is given.

Stop Condition. STOP is identified by a low to high transition of the SDA line while the clock SCL is stable in the high state. A STOP condition terminates communication between the ST24/25x01 and the bus master. A STOP condition at the end of a Read command, after and only after a No Acknowledge, forces the standby state. A STOP condition at the end of a Write command triggers the internal EEPROM write cycle.

Acknowledge Bit (ACK). An acknowledge signal is used to indicate a successfull data transfer. The bus transmitter , either master or slave, will release the SDA bus after sending 8 bits of data. During the 9th clock pulse period the receiver pulls the SDA bus low to acknowledge the receipt of the 8 bits of data.

Data Input. During data input the ST24/25x01 sample the SDA bus signal on the rising edge of the clock SCL. Note that for correct device operation the SDA signal must be stable during the c lock low to high transition and the data must change ONLY when the SCL line is lo w.

Memory Addressi ng. To start com munic ation between the bus master and the slave ST24/25x01, the master must initiate a ST ART co ndition. Following this, the master sends onto the SDA bus line 8 bits (MSB first) corresponding to the device select code (7 bits) and a READ or WRITE bit.

Figure 3. Maximum RL Value versus Bus Capacitance (C

max (kΩ)

VCC = 5V

100 200 300 400

(pF)

BUS

) for an I2C Bus

BUS

SDA

MASTER

SCL

BUS

AI01100

4/16

ST24/25C01, ST24C01R, ST24/25W01

T able 5. Input Parameters

(1)

(TA = 25 °C, f = 100 kHz )

Symbol Parameter Test Condition Min Max Unit

WCL

WCH

Note: 1. Sampled only, n ot 100% tested.

Input Capacitance (SDA) 8 pF Input Capacitance (other pins) 6 pF WC Input Impedance (ST24/25W01) VIN ≤ 0.3 V WC Input Impedance (ST24/25W01) VIN ≥ 0.7 V Low-pass filter input time constant

(SDA and SCL)

520kΩ

500 kΩ

100 ns

T ab le 6. DC Characteristics

= 0 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 3V to 5.5V, 2.5V to 5.5V or 1.8V to 5.5V)

Symbol Parameter Test Condition Min Max Unit

CC1

CC2

CC3

CC4

Input Leakage Current 0V ≤ VIN ≤ V Output Leakage Current

Supply Current (ST24 series) Supply Current (ST25 series) V

Supply Current (Standby) (ST24 series)

Supply Current (Standby) (ST25 series)

Supply Current (Standby) (ST24C01R)

0V ≤ V

SDA in Hi-Z

= 5V, fC = 100kHz

(Rise/Fall time < 10ns)

= 2.5V, fC = 100kHz 1 mA

= VSS or VCC,

= 5V, fC = 100kHz

= VSS or VCC,

= 2.5V, fC = 100kHz

= VSS or VCC,

= 3.6V, fC = 100kHz

= VSS or VCC,

= 1.8V, fC = 100kHz

≤ VCC

OUT

= 5V

= 2.5V

= 3.6V

= 1.8V

Input Low Voltage (SCL, SDA) –0.3 0.3 V Input High Voltage (SCL, SDA) 0.7 V Input Low Voltage

(E0-E2, MODE,

WC)

Input High Voltage (E0-E2, MODE,

WC)

–0.3 0.5 V

– 0.5 VCC + 1 V

Output Low Voltage (ST24 series) IOL = 3mA, VCC = 5V 0.4 V

Output Low Voltage (ST25 series) I Output Low Voltage

(ST24C01R)

= 2.1mA, VCC = 2.5V 0.4 V

= 1mA, VCC = 1.8V 0.3 V

±2 µA ±2 µA

2mA

100 µA

300 µA

5 µA

50 µA

20 µA

60 µA

10 µA

20 µA

VCC + 1 V

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